OV - exec - Function randomDisplacements.omp

	Function: randomDisplacements.omp_outlined	Module: exec	Source: initAtoms.c:194-202	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 194 - 202

--------------------------------------------------------------------------------

194:    #pragma omp parallel for

195:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

196:    {

197:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

198:       {

199:          uint64_t seed = mkSeed(s->atoms->gid[iOff], 457);

200:          s->atoms->r[iOff][0] += (2.0*lcg61(&seed)-1.0) * delta;

201:          s->atoms->r[iOff][1] += (2.0*lcg61(&seed)-1.0) * delta;

202:          s->atoms->r[iOff][2] += (2.0*lcg61(&seed)-1.0) * delta;

0x407440 SUB	SP, SP, #144

0x407444 STP	D9, D8, [SP, #32]

0x407448 STP	X29, X30, [SP, #48]

0x40744c STP	X28, X27, [SP, #64]

0x407450 STP	X26, X25, [SP, #80]

0x407454 STP	X24, X23, [SP, #96]

0x407458 STP	X22, X21, [SP, #112]

0x40745c STP	X20, X19, [SP, #128]

0x407460 ADD	X29, SP, #48

0x407464 LDR	X25, [X2]

0x407468 LDR	X8, [X25, #24]

0x40746c LDR	W8, [X8, #12]

0x407470 SUBS	W22, W8, #1

0x407474 B.LT	4074e8

0x407478 LDR	W21, [X0]

0x40747c ORR	X19, XZR, X3

0x407480 ORR	X20, XZR, X2

0x407484 MOVZ	W8, #1

0x407488 ADRP	X0,

0x40748c ADD	X0, X0, #2792

0x407490 ADD	X3, SP, #16

0x407494 SUB	X4, X29, #20

0x407498 ADD	X5, SP, #24

0x40749c STUR	WZR, [X29, #492]

0x4074a0 STR	WZR, [SP, #16]

0x4074a4 STP	W8, W22, [SP, #20]

0x4074a8 ADD	X6, SP, #20

0x4074ac MOVZ	W2, #34

0x4074b0 MOVZ	W7, #1

0x4074b4 STR	W8, [SP]

0x4074b8 ORR	W1, WZR, W21

0x4074bc BL	4023c0

0x4074c0 LDR	W8, [SP, #24]

0x4074c4 CMP	W8, W22

0x4074c8 CSEL	W8, W8, W22, #11

0x4074cc LDURSW	X22, [X29, #492]

0x4074d0 CMP	W22, W8

0x4074d4 B.LE	40750c

(88) 0x4074d8 ADRP	X0,

(88) 0x4074dc ADD	X0, X0, #2816

(88) 0x4074e0 ORR	W1, WZR, W21

(88) 0x4074e4 BL	402450

(88) 0x4074e8 LDP	D9, D8, [SP, #32]

(88) 0x4074ec LDP	X20, X19, [SP, #128]

(88) 0x4074f0 LDP	X22, X21, [SP, #112]

(88) 0x4074f4 LDP	X24, X23, [SP, #96]

(88) 0x4074f8 LDP	X26, X25, [SP, #80]

(88) 0x4074fc LDP	X28, X27, [SP, #64]

(88) 0x407500 LDP	X29, X30, [SP, #48]

(88) 0x407504 ADD	SP, SP, #144

(88) 0x407508 RET

(88) 0x40750c FMOV	D8, #-1.0000000

(88) 0x407510 FMOV	D9, #2.0000000

(88) 0x407514 UBFM	W23, W22, #26, #25

(88) 0x407518 ADD	W24, W8, #1

(88) 0x40751c B	407530

  (89) 0x407520 ADD	X22, X22, #1

  (89) 0x407524 ADD	W23, W23, #64

  (89) 0x407528 CMP	W24, W22

  (89) 0x40752c B.EQ	4074d8

  (89) 0x407530 LDR	X8, [X25, #24]

  (89) 0x407534 LDR	X8, [X8, #120]

  (89) 0x407538 LDR	W8, [X8, X22,LSL #2]

  (89) 0x40753c CMP	W8, #1

  (89) 0x407540 B.LT	407520

  (89) 0x407544 SBFM	X8, X23, #0, #31

  (89) 0x407548 SBFM	X27, X23, #62, #31

  (89) 0x40754c ORR	W26, WZR, WZR

  (89) 0x407550 ADD	X8, X8, W23,SXTW #1

  (89) 0x407554 UBFM	X28, X8, #61, #60

  (89) 0x407558 LDR	X8, [X25, #32]

  (89) 0x40755c HINT	#0

    (90) 0x407560 LDR	X8, [X8, #8]

    (90) 0x407564 MOVZ	W1, #457

    (90) 0x407568 LDR	W0, [X8, X27]

    (90) 0x40756c BL	409e30

    (90) 0x407570 STR	X0, [SP, #8]

    (90) 0x407574 ADD	X0, SP, #8

    (90) 0x407578 BL	409df0

    (90) 0x40757c LDR	X8, [X20]

    (90) 0x407580 LDR	D1, [X19]

    (90) 0x407584 FMADD	D0, D0, D9, D8

    (90) 0x407588 ADD	X0, SP, #8

    (90) 0x40758c LDR	X8, [X8, #32]

    (90) 0x407590 LDR	X8, [X8, #24]

    (90) 0x407594 LDR	D2, [X8, X28]

    (90) 0x407598 FMADD	D0, D0, D1, D2

    (90) 0x40759c STR	D0, [X8, X28]

    (90) 0x4075a0 BL	409df0

    (90) 0x4075a4 LDR	X8, [X20]

    (90) 0x4075a8 LDR	D1, [X19]

    (90) 0x4075ac FMADD	D0, D0, D9, D8

    (90) 0x4075b0 ADD	X0, SP, #8

    (90) 0x4075b4 LDR	X8, [X8, #32]

    (90) 0x4075b8 LDR	X8, [X8, #24]

    (90) 0x4075bc ADD	X8, X8, X28

    (90) 0x4075c0 LDR	D2, [X8, #8]

    (90) 0x4075c4 FMADD	D0, D0, D1, D2

    (90) 0x4075c8 STR	D0, [X8, #8]

    (90) 0x4075cc BL	409df0

    (90) 0x4075d0 LDR	X25, [X20]

    (90) 0x4075d4 LDR	D1, [X19]

    (90) 0x4075d8 FMADD	D0, D0, D9, D8

    (90) 0x4075dc ADD	W26, W26, #1

    (90) 0x4075e0 ADD	X27, X27, #4

    (90) 0x4075e4 LDP	X9, X8, [X25, #24]

    (90) 0x4075e8 LDR	X10, [X8, #24]

    (90) 0x4075ec LDR	X9, [X9, #120]

    (90) 0x4075f0 ADD	X10, X10, X28

    (90) 0x4075f4 LDR	W9, [X9, X22,LSL #2]

    (90) 0x4075f8 ADD	X28, X28, #24

    (90) 0x4075fc LDR	D2, [X10, #16]

    (90) 0x407600 FMADD	D0, D0, D1, D2

    (90) 0x407604 STR	D0, [X10, #16]

    (90) 0x407608 CMP	W26, W9

    (90) 0x40760c B.LT	407560

  (89) 0x407610 B	407520

0x407614 HINT	#0

0x407618 HINT	#0

0x40761c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	initAtoms.c:194-202
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:194-202.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 1.17 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.83 to 4.58 cycles (1.27x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
9% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	5.83	5.50	5.67	5.00	5.00
cycles	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	5.83	5.50	5.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Overall L1	5.83

Vectorization ratios

all	4%
load	0%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

5% of peak load performance is reached (5.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4074e8 <randomDisplacements.omp_outlined+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f488>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2792	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR WZR, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W8, W22, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X6, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023c0 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDURSW X22, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 40750c <randomDisplacements.omp_outlined+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	initAtoms.c:194-202
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:194-202.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 1.17 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
9% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 132 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	5.83	5.50	5.67	5.00	5.00
cycles	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	0.50	0.50	0.00	0.00	5.83	5.50	5.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Overall L1	5.83

Vectorization ratios

all	4%
load	0%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

5% of peak load performance is reached (5.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
47% of peak store performance is reached (22.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4074e8 <randomDisplacements.omp_outlined+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f488>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2792	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR WZR, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W8, W22, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X6, SP, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023c0 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDURSW X22, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 40750c <randomDisplacements.omp_outlined+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼randomDisplacements.omp_outlined–	0.02	0.00
▼Loop 88 - initAtoms.c:194-202 - exec–	0.00	0.00
▼Loop 89 - initAtoms.c:195-202 - exec–	0.00	0.00
○Loop 90 - initAtoms.c:197-202 - exec	0.02	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code