OV - exec - Function setTemperature.omp

	Function: setTemperature.omp_outlined	Module: exec	Source: initAtoms.c:151-162	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 151 - 162

--------------------------------------------------------------------------------

151:    #pragma omp parallel for

152:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

153:    {

154:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

155:       {

156:          int iType = s->atoms->iSpecies[iOff];

157:          real_t mass = s->species[iType].mass;

158:          real_t sigma = sqrt(kB_eV * temperature/mass);

159:          uint64_t seed = mkSeed(s->atoms->gid[iOff], 123);

160:          s->atoms->p[iOff][0] = mass * sigma * gasdev(&seed);

161:          s->atoms->p[iOff][1] = mass * sigma * gasdev(&seed);

162:          s->atoms->p[iOff][2] = mass * sigma * gasdev(&seed);

0x407050 SUB	SP, SP, #160

0x407054 STR	D10, [SP, #32]

0x407058 STP	D9, D8, [SP, #48]

0x40705c STP	X29, X30, [SP, #64]

0x407060 STP	X28, X27, [SP, #80]

0x407064 STP	X26, X25, [SP, #96]

0x407068 STP	X24, X23, [SP, #112]

0x40706c STP	X22, X21, [SP, #128]

0x407070 STP	X20, X19, [SP, #144]

0x407074 ADD	X29, SP, #64

0x407078 LDR	X23, [X2]

0x40707c LDR	X8, [X23, #24]

0x407080 LDR	W8, [X8, #12]

0x407084 SUBS	W22, W8, #1

0x407088 B.LT	4070f8

0x40708c LDR	W21, [X0]

0x407090 ORR	X19, XZR, X3

0x407094 ORR	X20, XZR, X2

0x407098 MOVZ	W8, #1

0x40709c ADRP	X0,

0x4070a0 ADD	X0, X0, #2648

0x4070a4 ADD	X3, SP, #24

0x4070a8 SUB	X4, X29, #20

0x4070ac SUB	X5, X29, #24

0x4070b0 STP	W22, WZR, [X29, #488]

0x4070b4 STP	WZR, W8, [SP, #24]

0x4070b8 ADD	X6, SP, #28

0x4070bc MOVZ	W2, #34

0x4070c0 MOVZ	W7, #1

0x4070c4 STR	W8, [SP]

0x4070c8 ORR	W1, WZR, W21

0x4070cc BL	4023c0

0x4070d0 LDUR	W8, [X29, #488]

0x4070d4 CMP	W8, W22

0x4070d8 CSEL	W8, W8, W22, #11

0x4070dc LDURSW	X22, [X29, #492]

0x4070e0 CMP	W22, W8

0x4070e4 B.LE	407120

(81) 0x4070e8 ADRP	X0,

(81) 0x4070ec ADD	X0, X0, #2672

(81) 0x4070f0 ORR	W1, WZR, W21

(81) 0x4070f4 BL	402450

(81) 0x4070f8 LDP	D9, D8, [SP, #48]

(81) 0x4070fc LDR	D10, [SP, #32]

(81) 0x407100 LDP	X20, X19, [SP, #144]

(81) 0x407104 LDP	X22, X21, [SP, #128]

(81) 0x407108 LDP	X24, X23, [SP, #112]

(81) 0x40710c LDP	X26, X25, [SP, #96]

(81) 0x407110 LDP	X28, X27, [SP, #80]

(81) 0x407114 LDP	X29, X30, [SP, #64]

(81) 0x407118 ADD	SP, SP, #160

(81) 0x40711c RET

(81) 0x407120 ADD	W25, W8, #1

(81) 0x407124 ADRP	X8,

(81) 0x407128 UBFM	W24, W22, #26, #25

(81) 0x40712c LDR	D8, [X8, #1472]

(81) 0x407130 B	407150

0x407134 HINT	#0

0x407138 HINT	#0

0x40713c HINT	#0

(81) 0x407140 ADD	X22, X22, #1

(81) 0x407144 ADD	W24, W24, #64

(81) 0x407148 CMP	W25, W22

(81) 0x40714c B.EQ	4070e8

(81) 0x407150 LDR	X8, [X23, #24]

(81) 0x407154 LDR	X8, [X8, #120]

(81) 0x407158 LDR	W8, [X8, X22,LSL #2]

(81) 0x40715c CMP	W8, #1

(81) 0x407160 B.LT	407140

(81) 0x407164 SBFM	X8, X24, #0, #31

(81) 0x407168 SBFM	X27, X24, #62, #31

(81) 0x40716c ORR	W26, WZR, WZR

(81) 0x407170 ADD	X8, X8, W24,SXTW #1

(81) 0x407174 UBFM	X28, X8, #61, #60

(81) 0x407178 LDR	X8, [X23, #32]

(81) 0x40717c HINT	#0

  (82) 0x407180 LDP	X8, X9, [X8, #8]

  (82) 0x407184 LDR	X10, [X23, #40]

  (82) 0x407188 LDR	D0, [X19]

  (82) 0x40718c MOVZ	W1, #123

  (82) 0x407190 FMUL	D0, D0, D8

  (82) 0x407194 LDRSW	X9, [X9, X27]

  (82) 0x407198 LDR	W0, [X8, X27]

  (82) 0x40719c ADD	X9, X10, X9,LSL #4

  (82) 0x4071a0 LDR	D9, [X9, #8]

  (82) 0x4071a4 FDIV	D0, D0, D9

  (82) 0x4071a8 FSQRT	D10, D0

  (82) 0x4071ac BL	409e30

  (82) 0x4071b0 STR	X0, [SP, #16]

  (82) 0x4071b4 ADD	X0, SP, #16

  (82) 0x4071b8 FMUL	D9, D10, D9

  (82) 0x4071bc BL	409d20

  (82) 0x4071c0 LDR	X8, [X20]

  (82) 0x4071c4 FMUL	D0, D0, D9

  (82) 0x4071c8 ADD	X0, SP, #16

  (82) 0x4071cc LDR	X8, [X8, #32]

  (82) 0x4071d0 LDR	X8, [X8, #32]

  (82) 0x4071d4 STR	D0, [X8, X28]

  (82) 0x4071d8 BL	409d20

  (82) 0x4071dc LDR	X8, [X20]

  (82) 0x4071e0 FMUL	D0, D0, D9

  (82) 0x4071e4 ADD	X0, SP, #16

  (82) 0x4071e8 LDR	X8, [X8, #32]

  (82) 0x4071ec LDR	X8, [X8, #32]

  (82) 0x4071f0 ADD	X8, X8, X28

  (82) 0x4071f4 STR	D0, [X8, #8]

  (82) 0x4071f8 BL	409d20

  (82) 0x4071fc LDR	X23, [X20]

  (82) 0x407200 FMUL	D0, D0, D9

  (82) 0x407204 ADD	W26, W26, #1

  (82) 0x407208 ADD	X27, X27, #4

  (82) 0x40720c LDP	X9, X8, [X23, #24]

  (82) 0x407210 LDR	X9, [X9, #120]

  (82) 0x407214 LDR	X10, [X8, #32]

  (82) 0x407218 LDR	W9, [X9, X22,LSL #2]

  (82) 0x40721c ADD	X10, X10, X28

  (82) 0x407220 ADD	X28, X28, #24

  (82) 0x407224 STR	D0, [X10, #16]

  (82) 0x407228 CMP	W26, W9

  (82) 0x40722c B.LT	407180

(81) 0x407230 B	407140

0x407234 HINT	#0

0x407238 HINT	#0

0x40723c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	initAtoms.c:151-162
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 1.33 cycles (4.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 60% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.83 to 4.71 cycles (1.24x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
9% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	1.00	1.00	0.00	0.00	5.83	5.50	5.67	4.50	4.50
cycles	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	1.00	1.00	0.00	0.00	5.83	5.50	5.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Overall L1	5.83

Vectorization ratios

all	4%
load	0%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

5% of peak load performance is reached (5.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407050

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4070f8 <setTemperature.omp_outlined+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f09c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2648	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W22, WZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X6, SP, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023c0 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDURSW X22, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 407120 <setTemperature.omp_outlined+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	initAtoms.c:151-162
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:151-162.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.83 to 1.33 cycles (4.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
9% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.83 to 0.50 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 140 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	1.00	1.00	0.00	0.00	5.83	5.50	5.67	4.50	4.50
cycles	1.50	1.50	3.25	3.25	3.17	3.17	3.08	3.08	1.00	1.00	0.00	0.00	5.83	5.50	5.67	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Overall L1	5.83

Vectorization ratios

all	4%
load	0%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.83 cycles. At this rate:

5% of peak load performance is reached (5.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
50% of peak store performance is reached (24.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407050

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X8, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4070f8 <setTemperature.omp_outlined+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f09c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2648	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W22, WZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP WZR, W8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X6, SP, #28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023c0 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W8, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDURSW X22, [X29, #492]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W22, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 407120 <setTemperature.omp_outlined+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼setTemperature.omp_outlined–	0.02	0.00
▼Loop 81 - initAtoms.c:151-162 - exec–	0.00	0.00
○Loop 82 - initAtoms.c:154-162 - exec	0.02	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code