OV - exec - Function sortAtomsById

	Function: sortAtomsById	Module: exec	Source: haloExchange.c:654-661	Coverage (incl. loops): 0.06% \| (excl. loops): 0.06%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 654 - 661

--------------------------------------------------------------------------------

654:    int aId = ((AtomMsg*) a)->gid;

655:    int bId = ((AtomMsg*) b)->gid;

656:    assert(aId != bId);

657:

658:    if (aId < bId)

659:       return -1;

660:    return 1;

661: }

0x406510 LDR	W8, [X0]

0x406514 LDR	W9, [X1]

0x406518 CMP	W8, W9

0x40651c B.EQ	40652c

0x406520 MOVN	W8, #0

0x406524 CSNEG	W0, W8, W8, #11

0x406528 RET

0x40652c STP	X29, X30, [SP, #1008]!

0x406530 ADD	X29, SP, #0

0x406534 ADRP	X0,

0x406538 ADD	X0, X0, #3148

0x40653c ADRP	X1,

0x406540 ADD	X1, X1, #2694

0x406544 ADRP	X3,

0x406548 ADD	X3, X3, #3159

0x40654c MOVZ	W2, #656

0x406550 BL	402360

0x406554 HINT	#0

0x406558 HINT	#0

0x40655c HINT	#0

Coverage (%)	Name	Source Location	Module
►10.08+	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►9.30+	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►8.53+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►7.75+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►6.98+	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►6.98+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►6.20+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►5.43+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►5.43+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►4.65+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►4.65+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►3.88+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►3.88+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►3.10+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►3.10+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►2.33+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►2.33+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►1.55+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so
►1.55+	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	msort_with_tmp.part.0		libc.so.6
○	__GI___qsort_r		libc.so.6
○	sortAtomsInCell	haloExchange.c:633	exec
○	redistributeAtoms.omp_outlined	timestep.c:153	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.06% of application time for run armclang_5

Source file and lines	haloExchange.c:654-661
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:654-661.

The structure of this function is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 40% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 2.08 to 1.83 cycles (1.14x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.08 to 0.50 cycles (4.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	18.50
loop length	74
nb stack references	0

Front-end

front end

1.94 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.25	1.25	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	1.25	1.25	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.94
Overall L1	2.08

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.08 cycles. At this rate:

4% of peak load performance is reached (3.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

The code analyzed by CQA in that panel excludes loops and represents 0.06% of application time for run armclang_5

Source file and lines	haloExchange.c:654-661
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 39% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 2.25 to 2.00 cycles (1.13x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.25 to 0.50 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	1.50	1.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.13
Overall L1	2.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.25 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406510

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40652c <sortAtomsById+0x1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W8, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CSNEG W0, W8, W8, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X29, X30, [SP, #1008]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <40b534>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3148	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40b53c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #2694	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X3, <40b544>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3159	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #656	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402360 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.06% of application time for run armclang_5

Source file and lines	haloExchange.c:654-661
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 41% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 1.92 to 1.67 cycles (1.15x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 1.92 to 0.50 cycles (3.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	1.00	1.00	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.75
Overall L1	1.92

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.92 cycles. At this rate:

4% of peak load performance is reached (4.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 406510

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W9, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40652c <sortAtomsById+0x1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X29, X30, [SP, #1008]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <40b534>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3148	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40b53c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #2694	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X3, <40b544>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #3159	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #656	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402360 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
○sortAtomsById	0.06	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code