OV - exec - Loop 84

	Loop Id: 84	Module: exec	Source: haloExchange.c:621-630	Coverage: 0.98%

0x407d84 ORR	X15, XZR, X5

0x407d88 LDR	D24, [X5, #16]    [1]

0x407d8c ADD	X10, X11, X6

0x407d90 ADD	X9, X12, X6

0x407d94 ORR	X7, XZR, X4

0x407d98 LDR	Q23, [X15], #16    [3]

0x407d9c ADD	X3, X3, #224

0x407da0 LDR	Q28, [X5, #48]    [1]

0x407da4 LDP	D25, D27, [X5, #32]    [1]

0x407da8 LDR	D26, [X15, #8]    [3]

0x407dac LDP	D29, D31, [X5, #64]    [1]

0x407db0 LDP	D30, D22, [X5, #80]    [1]

0x407db4 ADD	X5, X5, #96

0x407db8 LDR	W27, [X12, X6]    [7]

0x407dbc LDR	W16, [X11, X6]    [6]

0x407dc0 ADD	X6, X6, #16

0x407dc4 LDP	W14, W13, [X10, #4]    [5]

0x407dc8 LDR	W8, [X10, #12]    [5]

0x407dcc LDP	W15, W10, [X9, #4]    [4]

0x407dd0 LDR	W9, [X9, #12]    [4]

0x407dd4 STP	W27, W16, [X3, #280]    [8]

0x407dd8 STUR	Q23, [X3, #288]    [8]

0x407ddc STUR	D24, [X3, #304]    [8]

0x407de0 STP	W15, W14, [X3, #336]    [8]

0x407de4 STP	D26, D25, [X3, #856]    [8]

0x407de8 STUR	D27, [X3, #360]    [8]

0x407dec STP	W10, W13, [X3, #392]    [8]

0x407df0 STUR	Q28, [X3, #400]    [8]

0x407df4 STUR	D29, [X3, #416]    [8]

0x407df8 STP	W9, W8, [X3, #448]    [8]

0x407dfc STP	D31, D30, [X3, #968]    [8]

0x407e00 STUR	D22, [X3, #472]    [8]

0x407e04 LDR	Q0, [X7], #16    [2]

0x407e08 LDP	D1, D2, [X4, #32]    [9]

0x407e0c LDR	D7, [X4, #16]    [9]

0x407e10 LDR	D17, [X7, #8]    [2]

0x407e14 LDR	Q16, [X4, #48]    [9]

0x407e18 LDP	D3, D4, [X4, #64]    [9]

0x407e1c LDP	D5, D6, [X4, #80]    [9]

0x407e20 ADD	X4, X4, #96

0x407e24 STUR	Q0, [X3, #312]    [8]

0x407e28 STUR	D7, [X3, #328]    [8]

0x407e2c STP	D17, D1, [X3, #880]    [8]

0x407e30 STUR	D2, [X3, #384]    [8]

0x407e34 STUR	Q16, [X3, #424]    [8]

0x407e38 STUR	D3, [X3, #440]    [8]

0x407e3c STP	D4, D5, [X3, #992]    [8]

0x407e40 STUR	D6, [X3, #496]    [8]

0x407e44 CMP	X17, X6

0x407e48 B.NE	407d84

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 621 - 630

--------------------------------------------------------------------------------

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

630:       tmp[iTmp].pz =   atoms->p[ii][2];

Coverage (%)	Name	Source Location	Module
►13.68+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.97+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.80+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.62+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.44+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.36+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.30+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►10.59+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P12, P13, P14,
Function	sortAtomsInCell
Source	haloExchange.c:621-630
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	13.33
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	9.75
Front-end cycles	6.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.92
P3 cycles	1.92
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	13.33
P13 cycles	13.33
P14 cycles	13.33
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	20.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.60
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	224.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	47.37
Vectorization ratio load	55.56
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	71.71
Vector-efficiency ratio load	73.61
Vector-efficiency ratio store	70.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P12, P13, P14,
Function	sortAtomsInCell
Source	haloExchange.c:621-630
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	13.33
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	13.33
CQA cycles if fully vectorized	9.75
Front-end cycles	6.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.92
P3 cycles	1.92
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	13.33
P13 cycles	13.33
P14 cycles	13.33
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	20.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.60
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	224.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	47.37
Vectorization ratio load	55.56
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	71.71
Vector-efficiency ratio load	73.61
Vector-efficiency ratio store	70.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-630
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-630.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.33 to 10.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 71% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.33 to 9.75 cycles (1.37x speedup).

Details

47% of VPU instructions are used in vector version (process two or more data elements in vector registers):

55% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 224 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.92	1.92	1.83	1.83	1.75	1.75	8.00	8.00	0.00	0.00	13.33	13.33	13.33	2.00	2.00
cycles	0.50	0.50	1.92	1.92	1.83	1.83	1.75	1.75	8.00	8.00	0.00	0.00	13.33	13.33	13.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.25
Data deps.	1.00
Overall L1	13.33

Vectorization ratios

all	47%
load	55%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

17% of peak load performance is reached (16.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 407d84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X15, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X10, X11, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X12, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X7, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X15], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X3, X3, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q28, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D25, D27, [X5, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D26, [X15, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D29, D31, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D30, D22, [X5, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X5, X5, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR W27, [X12, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W16, [X11, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP W14, W13, [X10, #4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W8, [X10, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP W15, W10, [X9, #4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X9, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP W27, W16, [X3, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR Q23, [X3, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D24, [X3, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP W15, W14, [X3, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D26, D25, [X3, #856]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D27, [X3, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP W10, W13, [X3, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR Q28, [X3, #400]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D29, [X3, #416]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP W9, W8, [X3, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D31, D30, [X3, #968]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D22, [X3, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR Q0, [X7], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D1, D2, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D7, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D17, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR Q16, [X4, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D3, D4, [X4, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D5, D6, [X4, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X4, X4, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STUR Q0, [X3, #312]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D7, [X3, #328]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D17, D1, [X3, #880]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D2, [X3, #384]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STUR Q16, [X3, #424]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D3, [X3, #440]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D4, D5, [X3, #992]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D6, [X3, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X17, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 407d84 <sortAtomsInCell+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-630
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-630.

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

47% of VPU instructions are used in vector version (process two or more data elements in vector registers):

55% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 224 bytes. The binary loop is storing 224 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.92	1.92	1.83	1.83	1.75	1.75	8.00	8.00	0.00	0.00	13.33	13.33	13.33	2.00	2.00
cycles	0.50	0.50	1.92	1.92	1.83	1.83	1.75	1.75	8.00	8.00	0.00	0.00	13.33	13.33	13.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.25
Data deps.	1.00
Overall L1	13.33

Vectorization ratios

all	47%
load	55%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

17% of peak load performance is reached (16.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 407d84

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X15, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X10, X11, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X12, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X7, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X15], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X3, X3, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q28, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D25, D27, [X5, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D26, [X15, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D29, D31, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D30, D22, [X5, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X5, X5, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR W27, [X12, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W16, [X11, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP W14, W13, [X10, #4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W8, [X10, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP W15, W10, [X9, #4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X9, #12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP W27, W16, [X3, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR Q23, [X3, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D24, [X3, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP W15, W14, [X3, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D26, D25, [X3, #856]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D27, [X3, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP W10, W13, [X3, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR Q28, [X3, #400]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D29, [X3, #416]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP W9, W8, [X3, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D31, D30, [X3, #968]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D22, [X3, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR Q0, [X7], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D1, D2, [X4, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D7, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D17, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR Q16, [X4, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D3, D4, [X4, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D5, D6, [X4, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X4, X4, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STUR Q0, [X3, #312]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D7, [X3, #328]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D17, D1, [X3, #880]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D2, [X3, #384]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STUR Q16, [X3, #424]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D3, [X3, #440]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D4, D5, [X3, #992]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STUR D6, [X3, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X17, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 407d84 <sortAtomsInCell+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code