OV - exec - Loop 83

	Loop Id: 83	Module: exec	Source: haloExchange.c:633-642	Coverage: 0.21%

0x408080 LDR	W10, [X22]    [5]

0x408084 ORR	X27, XZR, X22

0x408088 ADD	X19, X13, #1

0x40808c ORR	X5, XZR, X4

0x408090 ORR	X6, XZR, X15

0x408094 LDR	D25, [X22, #8]    [5]

0x408098 ADD	X4, X4, #48

0x40809c ADD	X22, X22, #112

0x4080a0 ADD	X15, X15, #48

0x4080a4 STR	W10, [X23, X13,LSL #2]    [6]

0x4080a8 LDUR	W2, [X22, #404]    [4]

0x4080ac STR	W2, [X11, X13,LSL #2]    [3]

0x4080b0 ADD	X13, X13, #2

0x4080b4 LDUR	W9, [X22, #456]    [4]

0x4080b8 STUR	D25, [X4, #464]    [9]

0x4080bc LDUR	D24, [X22, #416]    [4]

0x4080c0 STUR	D24, [X4, #472]    [9]

0x4080c4 LDUR	D27, [X22, #424]    [4]

0x4080c8 STUR	D27, [X4, #480]    [9]

0x4080cc LDUR	D28, [X22, #432]    [4]

0x4080d0 STUR	D28, [X15, #464]    [7]

0x4080d4 LDUR	D29, [X22, #440]    [4]

0x4080d8 STUR	D29, [X15, #472]    [7]

0x4080dc LDUR	D31, [X22, #448]    [4]

0x4080e0 STUR	D31, [X15, #480]    [7]

0x4080e4 LDR	D30, [X27, #64]    [8]

0x4080e8 STR	W9, [X23, X19,LSL #2]    [6]

0x4080ec LDR	W12, [X27, #60]    [8]

0x4080f0 STR	W12, [X11, X19,LSL #2]    [3]

0x4080f4 STUR	D30, [X4, #488]    [9]

0x4080f8 LDR	D22, [X27, #72]    [8]

0x4080fc STUR	D22, [X4, #496]    [9]

0x408100 LDR	D26, [X27, #80]    [8]

0x408104 STR	D26, [X5, #40]    [1]

0x408108 LDR	D0, [X27, #88]    [8]

0x40810c STUR	D0, [X15, #488]    [7]

0x408110 LDR	D1, [X27, #96]    [8]

0x408114 STR	D1, [X6, #32]    [2]

0x408118 LDR	D2, [X27, #104]    [8]

0x40811c STR	D2, [X6, #40]    [2]

0x408120 CMP	W20, W13

0x408124 B.GT	408080

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 633 - 642

--------------------------------------------------------------------------------

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

Coverage (%)	Name	Source Location	Module
►17.55+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►14.69+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►13.88+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►13.47+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►13.06+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►9.39+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►9.39+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.35+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P12, P13, P14,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	4.67
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	10.67
P13 cycles	10.67
P14 cycles	10.67
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	112.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	43.75
Vector-efficiency ratio load	43.75
Vector-efficiency ratio store	43.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P12, P13, P14,
Function	sortAtomsInCell
Source	haloExchange.c:633-642
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	4.67
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.58
P3 cycles	1.58
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.42
P7 cycles	1.42
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	10.67
P13 cycles	10.67
P14 cycles	10.67
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	112.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	43.75
Vector-efficiency ratio load	43.75
Vector-efficiency ratio store	43.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:633-642.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 43% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.67 to 4.67 cycles (2.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	6.00	6.00	0.00	0.00	10.67	10.67	10.67	2.00	2.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	6.00	6.00	0.00	0.00	10.67	10.67	10.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

10% of peak load performance is reached (10.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X27, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X5, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X6, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X4, X4, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X22, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR W10, [X23, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR W2, [X22, #404]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR W2, [X11, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X13, X13, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR W9, [X22, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR D25, [X4, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D24, [X22, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D24, [X4, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D27, [X22, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D27, [X4, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D28, [X22, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D28, [X15, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D29, [X22, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D29, [X15, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D31, [X22, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D31, [X15, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D30, [X27, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR W9, [X23, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W12, [X27, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR W12, [X11, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR D30, [X4, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D22, [X27, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D22, [X4, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D26, [X27, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D26, [X5, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X27, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D0, [X15, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X27, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D1, [X6, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X27, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D2, [X6, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP W20, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 408080 <sortAtomsInCell+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	sortAtomsInCell
Source file and lines	haloExchange.c:633-642
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.67 to 8.00 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	6.00	6.00	0.00	0.00	10.67	10.67	10.67	2.00	2.00
cycles	0.50	0.50	1.58	1.58	1.50	1.50	1.42	1.42	6.00	6.00	0.00	0.00	10.67	10.67	10.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

10% of peak load performance is reached (10.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.50 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W10, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X27, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X19, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X5, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ORR X6, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X4, X4, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X22, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X15, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR W10, [X23, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDUR W2, [X22, #404]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR W2, [X11, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X13, X13, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR W9, [X22, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STUR D25, [X4, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D24, [X22, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D24, [X4, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D27, [X22, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D27, [X4, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D28, [X22, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D28, [X15, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D29, [X22, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D29, [X15, #472]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDUR D31, [X22, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D31, [X15, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D30, [X27, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR W9, [X23, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W12, [X27, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR W12, [X11, X19,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR D30, [X4, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D22, [X27, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D22, [X4, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D26, [X27, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D26, [X5, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X27, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STUR D0, [X15, #488]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X27, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D1, [X6, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X27, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D2, [X6, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP W20, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 408080 <sortAtomsInCell+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code