OV - exec - Loop 154

	Loop Id: 154	Module: exec	Source: timestep.c:110-116	Coverage: 0.02%

0x40dde8 LDR	W2, [X16, X13,LSL #2]

0x40ddec CMP	W2, #0

0x40ddf0 B.LE	40df88

0x40ddf4 LDP	X7, X3, [X19, #32]

0x40ddf8 ADD	X5, X13, X13,LSL #1

0x40ddfc ANDS	X6, X2, #4160

0x40de00 SBFM	X23, X12, #0, #31

0x40de04 ADD	X11, X12, W2,SXTW

0x40de08 UBFM	X8, X5, #55, #54

0x40de0c LDR	X9, [X7, #32]

0x40de10 LDR	X4, [X7, #16]

0x40de14 ADD	X15, X9, X8

0x40de18 B.EQ	40dec4

0x40de1c CMP	X6, #1

0x40de20 B.EQ	40de8c

0x40de24 CMP	X6, #2

0x40de28 B.EQ	40de5c

0x40de2c LDRSW	X10, [X4, X12,SXTW #2]

0x40de30 ADD	X23, X23, #1

0x40de34 LDP	D28, D31, [X15, #8]

0x40de38 ADD	X15, X15, #24

0x40de3c LDR	D29, [X9, X8]

0x40de40 ADD	X14, X3, X10,LSL #4

0x40de44 LDR	D27, [X14, #8]

0x40de48 FMUL	D0, D28, D28

0x40de4c FMADD	D1, D29, D29, D0

0x40de50 FDIV	D3, D21, D27

0x40de54 FMADD	D2, D31, D31, D1

0x40de58 FMADD	D30, D3, D2, D30

0x40de5c LDRSW	X18, [X4, X23,LSL #2]

0x40de60 ADD	X23, X23, #1

0x40de64 LDP	D4, D5, [X15]

0x40de68 ADD	X15, X15, #24

0x40de6c LDUR	D18, [X15, #504]

0x40de70 ADD	X30, X3, X18,LSL #4

0x40de74 LDR	D16, [X30, #8]

0x40de78 FMUL	D6, D5, D5

0x40de7c FMADD	D7, D4, D4, D6

0x40de80 FDIV	D17, D21, D16

0x40de84 FMADD	D19, D18, D18, D7

0x40de88 FMADD	D30, D17, D19, D30

0x40de8c LDRSW	X21, [X4, X23,LSL #2]

0x40de90 ADD	X23, X23, #1

0x40de94 LDP	D20, D22, [X15]

0x40de98 ADD	X15, X15, #24

0x40de9c LDUR	D29, [X15, #504]

0x40dea0 ADD	X22, X3, X21,LSL #4

0x40dea4 LDR	D25, [X22, #8]

0x40dea8 FMUL	D23, D22, D22

0x40deac FMADD	D24, D20, D20, D23

0x40deb0 FDIV	D26, D21, D25

0x40deb4 FMADD	D28, D29, D29, D24

0x40deb8 FMADD	D30, D26, D28, D30

0x40debc CMP	X23, X11

0x40dec0 B.EQ	40df88

  (155) 0x40dec4 LDP	D31, D0, [X15]

  (155) 0x40dec8 ADD	X2, X23, #1

  (155) 0x40decc ADD	X10, X15, #24

  (155) 0x40ded0 ADD	X0, X23, #2

  (155) 0x40ded4 ADD	X14, X23, #3

  (155) 0x40ded8 LDRSW	X1, [X4, X23,LSL #2]

  (155) 0x40dedc ADD	X9, X15, #48

  (155) 0x40dee0 ADD	X8, X15, #72

  (155) 0x40dee4 ADD	X23, X23, #4

  (155) 0x40dee8 LDP	D5, D6, [X15, #16]

  (155) 0x40deec ADD	X15, X15, #96

  (155) 0x40def0 FMUL	D1, D0, D0

  (155) 0x40def4 LDRSW	X5, [X4, X2,LSL #2]

  (155) 0x40def8 ADD	X7, X3, X1,LSL #4

  (155) 0x40defc LDP	D27, D3, [X10, #8]

  (155) 0x40df00 LDRSW	X6, [X4, X0,LSL #2]

  (155) 0x40df04 FMADD	D2, D31, D31, D1

  (155) 0x40df08 ADD	X18, X3, X5,LSL #4

  (155) 0x40df0c LDR	D31, [X7, #8]

  (155) 0x40df10 LDR	D22, [X18, #8]

  (155) 0x40df14 FMUL	D4, D27, D27

  (155) 0x40df18 ADD	X30, X3, X6,LSL #4

  (155) 0x40df1c FMADD	D24, D5, D5, D2

  (155) 0x40df20 LDRSW	X21, [X4, X14,LSL #2]

  (155) 0x40df24 FDIV	D2, D21, D31

  (155) 0x40df28 LDR	D28, [X30, #8]

  (155) 0x40df2c LDP	D7, D16, [X9, #8]

  (155) 0x40df30 FMADD	D18, D6, D6, D4

  (155) 0x40df34 ADD	X22, X3, X21,LSL #4

  (155) 0x40df38 LDUR	D19, [X15, #464]

  (155) 0x40df3c FDIV	D29, D21, D22

  (155) 0x40df40 LDR	D26, [X22, #8]

  (155) 0x40df44 FMADD	D23, D3, D3, D18

  (155) 0x40df48 FMUL	D17, D7, D7

  (155) 0x40df4c LDUR	D7, [X15, #488]

  (155) 0x40df50 FDIV	D1, D21, D28

  (155) 0x40df54 FMADD	D20, D19, D19, D17

  (155) 0x40df58 FMADD	D27, D2, D24, D30

  (155) 0x40df5c LDP	D3, D30, [X8, #8]

  (155) 0x40df60 FDIV	D0, D21, D26

  (155) 0x40df64 FMADD	D25, D16, D16, D20

  (155) 0x40df68 FMADD	D5, D29, D23, D27

  (155) 0x40df6c FMUL	D4, D3, D3

  (155) 0x40df70 FMADD	D16, D7, D7, D4

  (155) 0x40df74 FMADD	D6, D1, D25, D5

  (155) 0x40df78 FMADD	D17, D30, D30, D16

  (155) 0x40df7c FMADD	D30, D0, D17, D6

  (155) 0x40df80 CMP	X23, X11

  (155) 0x40df84 B.NE	40dec4

0x40df88 ADD	X13, X13, #1

0x40df8c ADD	X12, X12, #64

0x40df90 CMP	W17, W13

0x40df94 B.GT	40dde8

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.46 - 3.50
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.41 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38 - 1.42
Bottlenecks	P8, P10,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.38 - 10.49
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	4.75 - 5.24
CQA cycles if fully vectorized	5.22 - 5.24
Front-end cycles	7.38
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.58
P7 cycles	3.58
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	3.75
P11 cycles	3.75
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.25 - 2.29
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.73 - 19.53
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.57
Vectorization ratio load	23.08
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.71
Vector-efficiency ratio load	53.85
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.00

Metric	Value
CQA speedup if no scalar integer	2.46 - 3.50
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	1.41 - 2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38 - 1.42
Bottlenecks	P8, P10,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.38 - 10.49
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	4.75 - 5.24
CQA cycles if fully vectorized	5.22 - 5.24
Front-end cycles	7.38
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.58
P7 cycles	3.58
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	3.75
P11 cycles	3.75
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	59.00
Nb uops	59.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.25 - 2.29
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.73 - 19.53
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.57
Vectorization ratio load	23.08
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.71
Vector-efficiency ratio load	53.85
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.49 to 3.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 50% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 10.49 to 5.24 cycles (2.00x speedup).

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

23% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 9 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.75	3.75	3.67	3.67	3.58	3.58	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00
cycles	3.00	3.00	3.75	3.75	3.67	3.67	3.58	3.58	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	7.38
Overall L1	7.38-10.49

Vectorization ratios

INT

all	15%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.49 cycles. At this rate:

14% of peak load performance is reached (13.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40dde8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR W2, [X16, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP W2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40df88 <kineticEnergy._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X3, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
ADD X5, X13, X13,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X6, X2, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SBFM X23, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X12, W2,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X8, X5, #55, #54	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X7, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X4, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X15, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 40dec4 <kineticEnergy._omp_fn.0+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40de8c <kineticEnergy._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40de5c <kineticEnergy._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X4, X12,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP D28, D31, [X15, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X15, X15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D29, [X9, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X14, X3, X10,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D0, D28, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D1, D29, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FDIV D3, D21, D27	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D2, D31, D31, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D30, D3, D2, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDRSW X18, [X4, X23,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP D4, D5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X15, X15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR D18, [X15, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X30, X3, X18,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D7, D4, D4, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FDIV D17, D21, D16	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D19, D18, D18, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D30, D17, D19, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDRSW X21, [X4, X23,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP D20, D22, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X15, X15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR D29, [X15, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X22, X3, X21,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D23, D22, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D24, D20, D20, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FDIV D26, D21, D25	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D28, D29, D29, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D30, D26, D28, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X23, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40df88 <kineticEnergy._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W17, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 40dde8 <kineticEnergy._omp_fn.0+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.49 to 3.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

23% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 9 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	3.75	3.75	3.67	3.67	3.58	3.58	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00
cycles	3.00	3.00	3.75	3.75	3.67	3.67	3.58	3.58	3.75	3.75	3.75	3.75	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	7.38
Overall L1	7.38-10.49

Vectorization ratios

INT

all	15%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.49 cycles. At this rate:

14% of peak load performance is reached (13.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40dde8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR W2, [X16, X13,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP W2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40df88 <kineticEnergy._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X3, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
ADD X5, X13, X13,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X6, X2, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SBFM X23, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X12, W2,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
UBFM X8, X5, #55, #54	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X7, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X4, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X15, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 40dec4 <kineticEnergy._omp_fn.0+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40de8c <kineticEnergy._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40de5c <kineticEnergy._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X10, [X4, X12,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP D28, D31, [X15, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X15, X15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D29, [X9, X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X14, X3, X10,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D0, D28, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D1, D29, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FDIV D3, D21, D27	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D2, D31, D31, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D30, D3, D2, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDRSW X18, [X4, X23,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP D4, D5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X15, X15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR D18, [X15, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X30, X3, X18,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D16, [X30, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D6, D5, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D7, D4, D4, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FDIV D17, D21, D16	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D19, D18, D18, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D30, D17, D19, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDRSW X21, [X4, X23,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
ADD X23, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP D20, D22, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X15, X15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDUR D29, [X15, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X22, X3, X21,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D23, D22, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D24, D20, D20, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FDIV D26, D21, D25	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D28, D29, D29, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D30, D26, D28, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
CMP X23, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 40df88 <kineticEnergy._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W17, W13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 40dde8 <kineticEnergy._omp_fn.0+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code