OV - exec - Loop 134

	Loop Id: 134	Module: exec	Source: ljForce.c:191-216 [...]	Coverage: 78.15%

0x40b2c0 LDP	D6, D7, [X0]    [5]

0x40b2c4 LDP	D2, D31, [X1]    [9]

0x40b2c8 LDR	D27, [X0, #16]    [5]

0x40b2cc LDR	D29, [X1, #16]    [9]

0x40b2d0 FSUB	D3, D6, S2

0x40b2d4 FSUB	D28, D7, S31

0x40b2d8 FSUB	D30, D27, S29

0x40b2dc FMADD	D4, D3, D3, D25

0x40b2e0 FMADD	D5, D28, D28, D4

0x40b2e4 FMADD	D0, D30, D30, D5

0x40b2e8 FCMPE	D26, D0

0x40b2ec B.GE	40b3c8

0x40b2f0 LDR	D29, [X1, #24]    [9]

0x40b2f4 ADD	X3, X1, #24

0x40b2f8 ADD	W2, W2, #1

0x40b2fc LDP	D27, D5, [X0]    [5]

0x40b300 LDP	D7, D2, [X3, #8]    [10]

0x40b304 LDR	D0, [X0, #16]    [5]

0x40b308 FSUB	D1, D27, S29

0x40b30c FSUB	D3, D5, S7

0x40b310 FSUB	D28, D0, S2

0x40b314 FMADD	D6, D1, D1, D25

0x40b318 FMADD	D31, D3, D3, D6

0x40b31c FMADD	D4, D28, D28, D31

0x40b320 FCMPE	D26, D4

0x40b324 B.GE	40b358

0x40b328 ADD	W2, W2, #1

0x40b32c ADD	X1, X3, #24

0x40b330 CMP	W2, W6

0x40b334 B.LT	40b2c0

0x40b358 FCMPE	D4, #0

0x40b35c B.GT	40b364

0x40b360 B	40b328

0x40b364 FDIV	D30, D22, D4

0x40b368 LDP	X26, X24, [X7, #40]    [1]

0x40b36c FMUL	D27, D19, D16

0x40b370 LDR	D0, [X24, X5]    [3]

0x40b374 ADD	X1, X26, X4

0x40b378 FMUL	D5, D30, D30

0x40b37c FMUL	D29, D5, D30

0x40b380 FMUL	D2, D29, D20

0x40b384 FMADD	D6, D2, D17, D18

0x40b388 FSUB	D31, D2, S22

0x40b38c FMUL	D7, D27, D2

0x40b390 FNMSUB	D4, D31, D2, D21

0x40b394 FMUL	D30, D7, D30

0x40b398 FMADD	D27, D4, D23, D0

0x40b39c FMADD	D24, D4, D23, D24

0x40b3a0 FMUL	D0, D6, D30

0x40b3a4 STR	D27, [X24, X5]    [3]

0x40b3a8 LDR	D5, [X26, X4]    [7]

0x40b3ac FMSUB	D1, D0, D1, D5

0x40b3b0 STR	D1, [X26, X4]    [7]

0x40b3b4 LDP	D29, D2, [X1, #8]    [8]

0x40b3b8 FMSUB	D3, D0, D3, D29

0x40b3bc FMSUB	D28, D0, D28, D2

0x40b3c0 STP	D3, D28, [X1, #8]    [8]

0x40b3c4 B	40b328

0x40b3c8 FCMPE	D0, #0

0x40b3cc B.GT	40b3d4

0x40b3d0 B	40b2f0

0x40b3d4 FDIV	D1, D22, D0

0x40b3d8 LDP	X26, X24, [X7, #40]    [1]

0x40b3dc FMUL	D7, D19, D16

0x40b3e0 LDR	D2, [X24, X5]    [2]

0x40b3e4 ADD	X25, X26, X4

0x40b3e8 FMUL	D6, D1, D1

0x40b3ec FMUL	D31, D6, D1

0x40b3f0 FMUL	D4, D31, D20

0x40b3f4 FMADD	D27, D4, D17, D18

0x40b3f8 FSUB	D5, D4, S22

0x40b3fc FMUL	D0, D7, D4

0x40b400 FNMSUB	D29, D5, D4, D21

0x40b404 FMUL	D1, D0, D1

0x40b408 FMADD	D7, D29, D23, D2

0x40b40c FMADD	D24, D29, D23, D24

0x40b410 FMUL	D2, D27, D1

0x40b414 STR	D7, [X24, X5]    [2]

0x40b418 LDR	D6, [X26, X4]    [6]

0x40b41c FMSUB	D3, D2, D3, D6

0x40b420 STR	D3, [X26, X4]    [6]

0x40b424 LDP	D31, D4, [X25, #8]    [4]

0x40b428 FMSUB	D28, D2, D28, D31

0x40b42c FMSUB	D30, D2, D30, D4

0x40b430 STP	D28, D30, [X25, #8]    [4]

0x40b434 B	40b2f0

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 191 - 216

--------------------------------------------------------------------------------

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►99.07+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.02
CQA speedup if FP arith vectorized	1.74
CQA speedup if fully vectorized	1.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P8, P9, P10, P11,
Function	ljForce._omp_fn.1
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	7.75
CQA cycles if fully vectorized	7.00
Front-end cycles	10.75
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	1.08
P7 cycles	1.08
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	13.50
P12 cycles	7.33
P13 cycles	7.33
P14 cycles	7.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 6.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	86.00
Nb uops	86.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	4.74
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	20.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.96
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.27
Vectorization ratio load	42.86
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	54.58
Vector-efficiency ratio load	71.43
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	45.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.00

Metric	Value
CQA speedup if no scalar integer	2.02
CQA speedup if FP arith vectorized	1.74
CQA speedup if fully vectorized	1.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	P8, P9, P10, P11,
Function	ljForce._omp_fn.1
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.50
CQA cycles if no scalar integer	6.67
CQA cycles if FP arith vectorized	7.75
CQA cycles if fully vectorized	7.00
Front-end cycles	10.75
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	1.08
P7 cycles	1.08
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	13.50
P12 cycles	7.33
P13 cycles	7.33
P14 cycles	7.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 6.99
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	86.00
Nb uops	86.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	4.74
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	20.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.96
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.27
Vectorization ratio load	42.86
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	54.58
Vector-efficiency ratio load	71.43
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	45.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	45.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:191-216
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:191,197-216.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 6.67 cycles (2.03x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.50 to 7.00 cycles (1.93x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

28: addition or subtraction (20 inside FMA instructions)
34: multiply (20 inside FMA instructions)
2: divide

The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	86
loop length	344
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	1.25	1.25	1.17	1.17	1.08	1.08	13.50	13.50	13.50	13.50	7.33	7.33	7.33	0.00	0.00
cycles	4.50	4.50	1.25	1.25	1.17	1.17	1.08	1.08	13.50	13.50	13.50	13.50	7.33	7.33	7.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

3.50-6.99

Cycles summary

Front-end	10.75
Overall L1	13.50

Vectorization ratios

INT

all	34%
load	42%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	11%
load	42%
store	33%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

14% of peak load performance is reached (14.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP D6, D7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D2, D31, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D27, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D3, D6, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D28, D7, S31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D30, D27, S29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMADD D4, D3, D3, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D5, D28, D28, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D0, D30, D30, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D26, D0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40b3c8 <ljForce._omp_fn.1+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D29, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X3, X1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D27, D5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D7, D2, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D1, D27, S29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D3, D5, S7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D28, D0, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMADD D6, D1, D1, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D31, D3, D3, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D4, D28, D28, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D26, D4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40b358 <ljForce._omp_fn.1+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X1, X3, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W2, W6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40b2c0 <ljForce._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 40b364 <ljForce._omp_fn.1+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40b328 <ljForce._omp_fn.1+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D30, D22, D4	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X26, X24, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
FMUL D27, D19, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D0, [X24, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X1, X26, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D5, D30, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D29, D5, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D2, D29, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D6, D2, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D31, D2, S22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D7, D27, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FNMSUB D4, D31, D2, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D30, D7, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D27, D4, D23, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D24, D4, D23, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D0, D6, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D27, [X24, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D5, [X26, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D1, D0, D1, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D1, [X26, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D29, D2, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D3, D0, D3, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D28, D0, D28, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D3, D28, [X1, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b328 <ljForce._omp_fn.1+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMPE D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 40b3d4 <ljForce._omp_fn.1+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40b2f0 <ljForce._omp_fn.1+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D1, D22, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X26, X24, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
FMUL D7, D19, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D2, [X24, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X25, X26, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D6, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D31, D6, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D4, D31, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D27, D4, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D5, D4, S22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D0, D7, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FNMSUB D29, D5, D4, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D1, D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D7, D29, D23, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D24, D29, D23, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D2, D27, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D7, [X24, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D6, [X26, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D3, D2, D3, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D3, [X26, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D31, D4, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D28, D2, D28, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D30, D2, D30, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D28, D30, [X25, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b2f0 <ljForce._omp_fn.1+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:191-216
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 6.67 cycles (2.03x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
33% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

28: addition or subtraction (20 inside FMA instructions)
34: multiply (20 inside FMA instructions)
2: divide

The binary loop is loading 192 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	86
loop length	344
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	1.25	1.25	1.17	1.17	1.08	1.08	13.50	13.50	13.50	13.50	7.33	7.33	7.33	0.00	0.00
cycles	4.50	4.50	1.25	1.25	1.17	1.17	1.08	1.08	13.50	13.50	13.50	13.50	7.33	7.33	7.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

3.50-6.99

Cycles summary

Front-end	10.75
Overall L1	13.50

Vectorization ratios

INT

all	34%
load	42%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	11%
load	42%
store	33%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

14% of peak load performance is reached (14.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP D6, D7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D2, D31, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D27, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D29, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D3, D6, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D28, D7, S31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D30, D27, S29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMADD D4, D3, D3, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D5, D28, D28, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D0, D30, D30, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D26, D0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40b3c8 <ljForce._omp_fn.1+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D29, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X3, X1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D27, D5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D7, D2, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D1, D27, S29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D3, D5, S7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FSUB D28, D0, S2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMADD D6, D1, D1, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D31, D3, D3, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D4, D28, D28, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMPE D26, D4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GE 40b358 <ljForce._omp_fn.1+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W2, W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X1, X3, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP W2, W6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40b2c0 <ljForce._omp_fn.1+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMPE D4, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 40b364 <ljForce._omp_fn.1+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40b328 <ljForce._omp_fn.1+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D30, D22, D4	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X26, X24, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
FMUL D27, D19, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D0, [X24, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X1, X26, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D5, D30, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D29, D5, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D2, D29, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D6, D2, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D31, D2, S22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D7, D27, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FNMSUB D4, D31, D2, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D30, D7, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D27, D4, D23, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D24, D4, D23, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D0, D6, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D27, [X24, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D5, [X26, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D1, D0, D1, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D1, [X26, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D29, D2, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D3, D0, D3, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D28, D0, D28, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D3, D28, [X1, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b328 <ljForce._omp_fn.1+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMPE D0, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.GT 40b3d4 <ljForce._omp_fn.1+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 40b2f0 <ljForce._omp_fn.1+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D1, D22, D0	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDP X26, X24, [X7, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
FMUL D7, D19, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D2, [X24, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X25, X26, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D6, D1, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D31, D6, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D4, D31, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D27, D4, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FSUB D5, D4, S22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMUL D0, D7, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FNMSUB D29, D5, D4, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D1, D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D7, D29, D23, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D24, D29, D23, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D2, D27, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
STR D7, [X24, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D6, [X26, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMSUB D3, D2, D3, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D3, [X26, X4]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDP D31, D4, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMSUB D28, D2, D28, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMSUB D30, D2, D30, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STP D28, D30, [X25, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B 40b2f0 <ljForce._omp_fn.1+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code