OV - exec - Loop 131

	Loop Id: 131	Module: exec	Source: ljForce.c:178-216 [...]	Coverage: 0.26%

0x40b0e0 LDR	W9, [X14]

0x40b0e4 TBNZ	W9, #31, 40b658

0x40b0e8 LDR	W24, [X16, X9,UXTW #2]

0x40b0ec CMP	W17, #0

0x40b0f0 B.LE	40b1f0

0x40b0f4 ORN	W25, WZR, W11

0x40b0f8 UBFM	W10, W9, #26, #25

0x40b0fc UMADDL	X9, W9, W30, XZR

0x40b100 ADD	W26, W25, W12

0x40b104 ADD	W6, W24, W10

0x40b108 AND	W0, W26, #128

0x40b10c ORR	X5, XZR, X18

0x40b110 ORR	W8, WZR, W11

0x40b114 CMP	W24, #0

0x40b118 B.GT	40b214

0x40b11c ADD	W8, W11, #1

0x40b120 ADD	X5, X18, #8

0x40b124 CMP	W8, W12

0x40b128 B.GE	40b1f0

0x40b12c CBZ	W0, 40b1d8

0x40b130 CMP	W0, #1

0x40b134 B.EQ	40b1c0

0x40b138 CMP	W0, #2

0x40b13c B.EQ	40b1b0

0x40b140 CMP	W0, #3

0x40b144 B.EQ	40b1a0

0x40b148 CMP	W0, #4

0x40b14c B.EQ	40b190

0x40b150 CMP	W0, #5

0x40b154 B.EQ	40b180

0x40b158 CMP	W0, #6

0x40b15c B.EQ	40b170

0x40b160 CMP	W24, #0

0x40b164 B.GT	40b214

0x40b168 ADD	W8, W8, #1

0x40b16c ADD	X5, X5, #8

0x40b170 CMP	W24, #0

0x40b174 B.GT	40b214

0x40b178 ADD	W8, W8, #1

0x40b17c ADD	X5, X5, #8

0x40b180 CMP	W24, #0

0x40b184 B.GT	40b214

0x40b188 ADD	W8, W8, #1

0x40b18c ADD	X5, X5, #8

0x40b190 CMP	W24, #0

0x40b194 B.GT	40b214

0x40b198 ADD	W8, W8, #1

0x40b19c ADD	X5, X5, #8

0x40b1a0 CMP	W24, #0

0x40b1a4 B.GT	40b214

0x40b1a8 ADD	W8, W8, #1

0x40b1ac ADD	X5, X5, #8

0x40b1b0 CMP	W24, #0

0x40b1b4 B.GT	40b214

0x40b1b8 ADD	W8, W8, #1

0x40b1bc ADD	X5, X5, #8

0x40b1c0 CMP	W24, #0

0x40b1c4 B.GT	40b214

0x40b1c8 ADD	W8, W8, #1

0x40b1cc ADD	X5, X5, #8

0x40b1d0 CMP	W8, W12

0x40b1d4 B.GE	40b1f0

  (135) 0x40b1d8 CMP	W24, #0

  (135) 0x40b1dc B.GT	40b214

  (135) 0x40b1e0 ADD	W8, W8, #8

  (135) 0x40b1e4 ADD	X5, X5, #64

  (135) 0x40b1e8 CMP	W8, W12

  (135) 0x40b1ec B.LT	40b1d8

0x40b1f0 ADD	X14, X14, #4

0x40b1f4 CMP	X21, X14

0x40b1f8 B.NE	40b0e0

0x40b214 LDR	X7, [X20, #32]

0x40b218 HINT	#0

0x40b21c HINT	#0

  (133) 0x40b220 ADD	X4, X5, X5,LSL #1

  (133) 0x40b224 ORN	W1, WZR, W10

  (133) 0x40b228 LDR	X24, [X7, #24]

  (133) 0x40b22c ADD	W2, W1, W6

  (133) 0x40b230 AND	W3, W2, #0

  (133) 0x40b234 LDR	D27, [X24, X4]

  (133) 0x40b238 ADD	X0, X24, X4

  (133) 0x40b23c ADD	X25, X24, X9

  (133) 0x40b240 LDR	D31, [X24, X9]

  (133) 0x40b244 LDP	D28, D30, [X0, #8]

  (133) 0x40b248 LDP	D1, D29, [X25, #8]

  (133) 0x40b24c FSUB	D0, D27, S31

  (133) 0x40b250 FSUB	D2, D28, S1

  (133) 0x40b254 FSUB	D28, D30, S29

  (133) 0x40b258 FMADD	D3, D0, D0, D25

  (133) 0x40b25c FMADD	D4, D2, D2, D3

  (133) 0x40b260 FMADD	D5, D28, D28, D4

  (133) 0x40b264 FCMPE	D26, D5

  (133) 0x40b268 B.GE	40b438

  (133) 0x40b26c ADD	W2, W10, #1

  (133) 0x40b270 ADD	X1, X25, #24

  (133) 0x40b274 CMP	W2, W6

  (133) 0x40b278 B.GE	40b338

  (133) 0x40b27c CBZ	W3, 40b2c0

  (133) 0x40b280 LDR	D3, [X24, X4]

  (133) 0x40b284 LDR	D29, [X25, #24]

  (133) 0x40b288 LDP	D4, D5, [X0, #8]

  (133) 0x40b28c LDP	D7, D30, [X1, #8]

  (133) 0x40b290 FSUB	D27, D3, S29

  (133) 0x40b294 FSUB	D0, D4, S7

  (133) 0x40b298 FSUB	D1, D5, S30

  (133) 0x40b29c FMADD	D6, D27, D27, D25

  (133) 0x40b2a0 FMADD	D31, D0, D0, D6

  (133) 0x40b2a4 FMADD	D2, D1, D1, D31

  (133) 0x40b2a8 FCMPE	D26, D2

  (133) 0x40b2ac B.GE	40b4a8

  (133) 0x40b2b0 ADD	W2, W2, #1

  (133) 0x40b2b4 ADD	X1, X1, #24

  (133) 0x40b2b8 CMP	W2, W6

  (133) 0x40b2bc B.GE	40b338

    (134) 0x40b2c0 LDP	D6, D7, [X0]

    (134) 0x40b2c4 LDP	D2, D31, [X1]

    (134) 0x40b2c8 LDR	D27, [X0, #16]

    (134) 0x40b2cc LDR	D29, [X1, #16]

    (134) 0x40b2d0 FSUB	D3, D6, S2

    (134) 0x40b2d4 FSUB	D28, D7, S31

    (134) 0x40b2d8 FSUB	D30, D27, S29

    (134) 0x40b2dc FMADD	D4, D3, D3, D25

    (134) 0x40b2e0 FMADD	D5, D28, D28, D4

    (134) 0x40b2e4 FMADD	D0, D30, D30, D5

    (134) 0x40b2e8 FCMPE	D26, D0

    (134) 0x40b2ec B.GE	40b3c8

    (134) 0x40b2f0 LDR	D29, [X1, #24]

    (134) 0x40b2f4 ADD	X3, X1, #24

    (134) 0x40b2f8 ADD	W2, W2, #1

    (134) 0x40b2fc LDP	D27, D5, [X0]

    (134) 0x40b300 LDP	D7, D2, [X3, #8]

    (134) 0x40b304 LDR	D0, [X0, #16]

    (134) 0x40b308 FSUB	D1, D27, S29

    (134) 0x40b30c FSUB	D3, D5, S7

    (134) 0x40b310 FSUB	D28, D0, S2

    (134) 0x40b314 FMADD	D6, D1, D1, D25

    (134) 0x40b318 FMADD	D31, D3, D3, D6

    (134) 0x40b31c FMADD	D4, D28, D28, D31

    (134) 0x40b320 FCMPE	D26, D4

    (134) 0x40b324 B.GE	40b358

    (134) 0x40b328 ADD	W2, W2, #1

    (134) 0x40b32c ADD	X1, X3, #24

    (134) 0x40b330 CMP	W2, W6

    (134) 0x40b334 B.LT	40b2c0

  (133) 0x40b338 ADD	W8, W8, #1

  (133) 0x40b33c ADD	X5, X5, #8

  (133) 0x40b340 CMP	W12, W8

  (133) 0x40b344 B.GT	40b220

0x40b348 ADD	X14, X14, #4

0x40b34c CMP	X21, X14

0x40b350 B.NE	40b0e0

    (134) 0x40b358 FCMPE	D4, #0

    (134) 0x40b35c B.GT	40b364

    (134) 0x40b360 B	40b328

    (134) 0x40b364 FDIV	D30, D22, D4

    (134) 0x40b368 LDP	X26, X24, [X7, #40]

    (134) 0x40b36c FMUL	D27, D19, D16

    (134) 0x40b370 LDR	D0, [X24, X5]

    (134) 0x40b374 ADD	X1, X26, X4

    (134) 0x40b378 FMUL	D5, D30, D30

    (134) 0x40b37c FMUL	D29, D5, D30

    (134) 0x40b380 FMUL	D2, D29, D20

    (134) 0x40b384 FMADD	D6, D2, D17, D18

    (134) 0x40b388 FSUB	D31, D2, S22

    (134) 0x40b38c FMUL	D7, D27, D2

    (134) 0x40b390 FNMSUB	D4, D31, D2, D21

    (134) 0x40b394 FMUL	D30, D7, D30

    (134) 0x40b398 FMADD	D27, D4, D23, D0

    (134) 0x40b39c FMADD	D24, D4, D23, D24

    (134) 0x40b3a0 FMUL	D0, D6, D30

    (134) 0x40b3a4 STR	D27, [X24, X5]

    (134) 0x40b3a8 LDR	D5, [X26, X4]

    (134) 0x40b3ac FMSUB	D1, D0, D1, D5

    (134) 0x40b3b0 STR	D1, [X26, X4]

    (134) 0x40b3b4 LDP	D29, D2, [X1, #8]

    (134) 0x40b3b8 FMSUB	D3, D0, D3, D29

    (134) 0x40b3bc FMSUB	D28, D0, D28, D2

    (134) 0x40b3c0 STP	D3, D28, [X1, #8]

    (134) 0x40b3c4 B	40b328

    (134) 0x40b3c8 FCMPE	D0, #0

    (134) 0x40b3cc B.GT	40b3d4

    (134) 0x40b3d0 B	40b2f0

    (134) 0x40b3d4 FDIV	D1, D22, D0

    (134) 0x40b3d8 LDP	X26, X24, [X7, #40]

    (134) 0x40b3dc FMUL	D7, D19, D16

    (134) 0x40b3e0 LDR	D2, [X24, X5]

    (134) 0x40b3e4 ADD	X25, X26, X4

    (134) 0x40b3e8 FMUL	D6, D1, D1

    (134) 0x40b3ec FMUL	D31, D6, D1

    (134) 0x40b3f0 FMUL	D4, D31, D20

    (134) 0x40b3f4 FMADD	D27, D4, D17, D18

    (134) 0x40b3f8 FSUB	D5, D4, S22

    (134) 0x40b3fc FMUL	D0, D7, D4

    (134) 0x40b400 FNMSUB	D29, D5, D4, D21

    (134) 0x40b404 FMUL	D1, D0, D1

    (134) 0x40b408 FMADD	D7, D29, D23, D2

    (134) 0x40b40c FMADD	D24, D29, D23, D24

    (134) 0x40b410 FMUL	D2, D27, D1

    (134) 0x40b414 STR	D7, [X24, X5]

    (134) 0x40b418 LDR	D6, [X26, X4]

    (134) 0x40b41c FMSUB	D3, D2, D3, D6

    (134) 0x40b420 STR	D3, [X26, X4]

    (134) 0x40b424 LDP	D31, D4, [X25, #8]

    (134) 0x40b428 FMSUB	D28, D2, D28, D31

    (134) 0x40b42c FMSUB	D30, D2, D30, D4

    (134) 0x40b430 STP	D28, D30, [X25, #8]

    (134) 0x40b434 B	40b2f0

  (133) 0x40b438 FCMPE	D5, #0

  (133) 0x40b43c B.GT	40b444

  (133) 0x40b440 B	40b26c

  (133) 0x40b444 FDIV	D27, D22, D5

  (133) 0x40b448 LDP	X2, X26, [X7, #40]

  (133) 0x40b44c FMUL	D7, D19, D16

  (133) 0x40b450 LDR	D30, [X26, X5]

  (133) 0x40b454 ADD	X1, X2, X4

  (133) 0x40b458 FMUL	D6, D27, D27

  (133) 0x40b45c FMUL	D31, D6, D27

  (133) 0x40b460 FMUL	D1, D31, D20

  (133) 0x40b464 FMADD	D3, D1, D17, D18

  (133) 0x40b468 FSUB	D29, D1, S22

  (133) 0x40b46c FMUL	D4, D7, D1

  (133) 0x40b470 FNMSUB	D5, D29, D1, D21

  (133) 0x40b474 FMUL	D27, D4, D27

  (133) 0x40b478 FMADD	D7, D5, D23, D30

  (133) 0x40b47c FMADD	D24, D5, D23, D24

  (133) 0x40b480 FMUL	D30, D3, D27

  (133) 0x40b484 STR	D7, [X26, X5]

  (133) 0x40b488 LDR	D6, [X2, X4]

  (133) 0x40b48c FMSUB	D0, D30, D0, D6

  (133) 0x40b490 STR	D0, [X2, X4]

  (133) 0x40b494 LDP	D31, D1, [X1, #8]

  (133) 0x40b498 FMSUB	D2, D30, D2, D31

  (133) 0x40b49c FMSUB	D28, D30, D28, D1

  (133) 0x40b4a0 STP	D2, D28, [X1, #8]

  (133) 0x40b4a4 B	40b26c

  (133) 0x40b4a8 FCMPE	D2, #0

  (133) 0x40b4ac B.GT	40b4b4

  (133) 0x40b4b0 B	40b2b0

  (133) 0x40b4b4 FDIV	D28, D22, D2

  (133) 0x40b4b8 LDP	X24, X25, [X7, #40]

  (133) 0x40b4bc FMUL	D3, D19, D16

  (133) 0x40b4c0 LDR	D4, [X25, X5]

  (133) 0x40b4c4 ADD	X3, X24, X4

  (133) 0x40b4c8 FMUL	D5, D28, D28

  (133) 0x40b4cc FMUL	D29, D5, D28

  (133) 0x40b4d0 FMUL	D30, D29, D20

  (133) 0x40b4d4 FMADD	D6, D30, D17, D18

  (133) 0x40b4d8 FSUB	D31, D30, S22

  (133) 0x40b4dc FMUL	D7, D3, D30

  (133) 0x40b4e0 FNMSUB	D2, D31, D30, D21

  (133) 0x40b4e4 FMUL	D28, D7, D28

  (133) 0x40b4e8 FMADD	D3, D2, D23, D4

  (133) 0x40b4ec FMADD	D24, D2, D23, D24

  (133) 0x40b4f0 FMUL	D4, D6, D28

  (133) 0x40b4f4 STR	D3, [X25, X5]

  (133) 0x40b4f8 LDR	D5, [X24, X4]

  (133) 0x40b4fc FMSUB	D27, D4, D27, D5

  (133) 0x40b500 STR	D27, [X24, X4]

  (133) 0x40b504 LDP	D29, D30, [X3, #8]

  (133) 0x40b508 FMSUB	D0, D4, D0, D29

  (133) 0x40b50c FMSUB	D1, D4, D1, D30

  (133) 0x40b510 STP	D0, D1, [X3, #8]

  (133) 0x40b514 B	40b2b0

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►98.34+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.66+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P0, P1,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.50
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.50
CQA cycles if fully vectorized	2.63
Front-end cycles	8.63
P0 cycles	10.50
P1 cycles	10.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	1.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	69.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.52
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	31.40
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	36.11
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	27.17

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P0, P1,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.50
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.50
CQA cycles if fully vectorized	2.63
Front-end cycles	8.63
P0 cycles	10.50
P1 cycles	10.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	7.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	1.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	71.00
Nb uops	69.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.52
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	31.40
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	36.11
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	27.17

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187,191.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 4457 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 31% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.50 to 2.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	71
loop length	284
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.50	10.50	7.50	7.50	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	10.50	10.50	7.50	7.50	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Overall L1	10.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.50 cycles. At this rate:

1% of peak load performance is reached (1.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b0e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W9, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
TBNZ W9, #31, 40b658 <ljForce._omp_fn.1+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W24, [X16, X9,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W17, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40b1f0 <ljForce._omp_fn.1+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W25, WZR, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM W10, W9, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X9, W9, W30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W26, W25, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W6, W24, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W0, W26, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X5, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W8, WZR, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W8, W12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40b1f0 <ljForce._omp_fn.1+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 40b1d8 <ljForce._omp_fn.1+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b1c0 <ljForce._omp_fn.1+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b1b0 <ljForce._omp_fn.1+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b1a0 <ljForce._omp_fn.1+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b190 <ljForce._omp_fn.1+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b180 <ljForce._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b170 <ljForce._omp_fn.1+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W8, W12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40b1f0 <ljForce._omp_fn.1+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 40b0e0 <ljForce._omp_fn.1+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
ADD X14, X14, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 40b0e0 <ljForce._omp_fn.1+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	71
loop length	284
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.50	10.50	7.50	7.50	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	10.50	10.50	7.50	7.50	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Overall L1	10.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.50 cycles. At this rate:

1% of peak load performance is reached (1.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b0e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR W9, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
TBNZ W9, #31, 40b658 <ljForce._omp_fn.1+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W24, [X16, X9,UXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W17, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40b1f0 <ljForce._omp_fn.1+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W25, WZR, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM W10, W9, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UMADDL X9, W9, W30, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W26, W25, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W6, W24, W10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W0, W26, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X5, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W8, WZR, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W8, W12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40b1f0 <ljForce._omp_fn.1+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 40b1d8 <ljForce._omp_fn.1+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b1c0 <ljForce._omp_fn.1+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b1b0 <ljForce._omp_fn.1+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b1a0 <ljForce._omp_fn.1+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b190 <ljForce._omp_fn.1+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b180 <ljForce._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40b170 <ljForce._omp_fn.1+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W24, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40b214 <ljForce._omp_fn.1+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W8, W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W8, W12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40b1f0 <ljForce._omp_fn.1+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X14, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 40b0e0 <ljForce._omp_fn.1+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
ADD X14, X14, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 40b0e0 <ljForce._omp_fn.1+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code