OV - exec - Loop 128

	Loop Id: 128	Module: exec	Source: ljForce.c:161-161 [...]	Coverage: 2.06%

0x40ada4 ORR	X9, XZR, X2

0x40ada8 STR	Q31, [X0, #32]    [8]

0x40adac ADD	X14, X0, #48

0x40adb0 STP	Q31, Q31, [X0]    [8]

0x40adb4 STR	Q31, [X9], #16    [2]

0x40adb8 ADD	X13, X0, #96

0x40adbc ADD	X12, X0, #144

0x40adc0 STR	Q31, [X0, #48]    [8]

0x40adc4 ADD	X11, X0, #192

0x40adc8 ADD	X10, X0, #240

0x40adcc STP	Q31, Q31, [X14, #16]    [9]

0x40add0 STR	Q31, [X2, #16]    [12]

0x40add4 ADD	X7, X0, #288

0x40add8 ADD	X15, X0, #336

0x40addc STR	Q31, [X0, #96]    [8]

0x40ade0 ADD	X2, X2, #128

0x40ade4 ADD	X0, X0, #384

0x40ade8 STP	Q31, Q31, [X13, #16]    [6]

0x40adec STR	Q31, [X9, #16]    [2]

0x40adf0 STUR	Q31, [X0, #272]    [7]

0x40adf4 STP	Q31, Q31, [X12, #16]    [5]

0x40adf8 STUR	Q31, [X2, #432]    [11]

0x40adfc STUR	Q31, [X0, #320]    [7]

0x40ae00 STP	Q31, Q31, [X11, #16]    [4]

0x40ae04 STUR	Q31, [X2, #448]    [11]

0x40ae08 STUR	Q31, [X0, #368]    [7]

0x40ae0c STP	Q31, Q31, [X10, #16]    [3]

0x40ae10 STUR	Q31, [X2, #464]    [11]

0x40ae14 STUR	Q31, [X0, #416]    [7]

0x40ae18 STP	Q31, Q31, [X7, #16]    [1]

0x40ae1c STUR	Q31, [X2, #480]    [11]

0x40ae20 STUR	Q31, [X0, #464]    [7]

0x40ae24 STP	Q31, Q31, [X15, #16]    [10]

0x40ae28 STUR	Q31, [X2, #496]    [11]

0x40ae2c CMP	X20, X2

0x40ae30 B.NE	40ada4

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 161 - 161

--------------------------------------------------------------------------------

161:       s->atoms->U[ii] = 0.;

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

Coverage (%)	Name	Source Location	Module
►98.78+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.22+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	ljForce	ljForce.c:164	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P8, P9, P12, P13,
Function	ljForce._omp_fn.0
Source	ljForce.c:161-161,mytype.h:22-24
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	4.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	12.00
P13 cycles	12.00
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P8, P9, P12, P13,
Function	ljForce._omp_fn.0
Source	ljForce.c:161-161,mytype.h:22-24
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	4.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	12.00
P13 cycles	12.00
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	8.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	NA
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.0
Source file and lines	ljForce.c:161-161
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 512 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.50
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

88% of peak store performance is reached (42.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40ada4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
ORR X9, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X0, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X14, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STR Q31, [X9], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X13, X0, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X12, X0, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X0, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X11, X0, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X10, X0, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X14, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STR Q31, [X2, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X7, X0, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X15, X0, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X0, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X2, X2, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X0, X0, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X13, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STR Q31, [X9, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X12, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #432]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X11, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #448]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X10, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #416]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X7, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X15, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
CMP X20, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 40ada4 <ljForce._omp_fn.0+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce._omp_fn.0
Source file and lines	ljForce.c:161-161
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161
/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 512 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00
cycles	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	12.00	12.00	0.00	0.00	12.00	12.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.50
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

88% of peak store performance is reached (42.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40ada4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
ORR X9, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X0, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X14, X0, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STR Q31, [X9], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X13, X0, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X12, X0, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X0, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X11, X0, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X10, X0, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X14, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STR Q31, [X2, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X7, X0, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X15, X0, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STR Q31, [X0, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
ADD X2, X2, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD X0, X0, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
STP Q31, Q31, [X13, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STR Q31, [X9, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X12, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #432]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X11, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #448]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X10, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #416]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X7, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STUR Q31, [X0, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
STP Q31, Q31, [X15, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	1	vect (100.0%)
STUR Q31, [X2, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50	vect (100.0%)
CMP X20, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	1	0.33	N/A
B.NE 40ada4 <ljForce._omp_fn.0+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code