OV - exec - Function kineticEnergy._omp

	Function: kineticEnergy._omp_fn.0	Module: exec	Source: timestep.c:107-116	Coverage (incl. loops): 0.08% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

0x40dd80 STP	X29, X30, [SP, #960]!

0x40dd84 ADD	X29, SP, #0

0x40dd88 STP	X19, X20, [SP, #16]

0x40dd8c ORR	X20, XZR, X0

0x40dd90 STP	X21, X22, [SP, #32]

0x40dd94 LDR	X19, [X0]

0x40dd98 STR	X23, [SP, #48]

0x40dd9c BL	4025a0

0x40dda0 ORR	W21, WZR, W0

0x40dda4 BL	4026a0

0x40dda8 LDR	X23, [X19, #24]

0x40ddac ORR	W12, WZR, W0

0x40ddb0 LDR	W22, [X23, #12]

0x40ddb4 SDIV	W15, W22, W21

0x40ddb8 MSUB	W0, W15, W21, W22

0x40ddbc CMP	W12, W0

0x40ddc0 B.LT	40dfd0

(153) 0x40ddc4 MADD	W1, W15, W12, W0

(153) 0x40ddc8 MOVI	D30, #0

(153) 0x40ddcc ADD	W17, W15, W1

(153) 0x40ddd0 CMP	W1, W17

(153) 0x40ddd4 B.GE	40df98

(153) 0x40ddd8 LDR	X16, [X23, #120]

(153) 0x40dddc FMOV	D21, #0.5000000

(153) 0x40dde0 SBFM	X13, X1, #0, #31

(153) 0x40dde4 SBFM	X12, X1, #58, #31

  (154) 0x40dde8 LDR	W2, [X16, X13,LSL #2]

  (154) 0x40ddec CMP	W2, #0

  (154) 0x40ddf0 B.LE	40df88

  (154) 0x40ddf4 LDP	X7, X3, [X19, #32]

  (154) 0x40ddf8 ADD	X5, X13, X13,LSL #1

  (154) 0x40ddfc ANDS	X6, X2, #4160

  (154) 0x40de00 SBFM	X23, X12, #0, #31

  (154) 0x40de04 ADD	X11, X12, W2,SXTW

  (154) 0x40de08 UBFM	X8, X5, #55, #54

  (154) 0x40de0c LDR	X9, [X7, #32]

  (154) 0x40de10 LDR	X4, [X7, #16]

  (154) 0x40de14 ADD	X15, X9, X8

  (154) 0x40de18 B.EQ	40dec4

  (154) 0x40de1c CMP	X6, #1

  (154) 0x40de20 B.EQ	40de8c

  (154) 0x40de24 CMP	X6, #2

  (154) 0x40de28 B.EQ	40de5c

  (154) 0x40de2c LDRSW	X10, [X4, X12,SXTW #2]

  (154) 0x40de30 ADD	X23, X23, #1

  (154) 0x40de34 LDP	D28, D31, [X15, #8]

  (154) 0x40de38 ADD	X15, X15, #24

  (154) 0x40de3c LDR	D29, [X9, X8]

  (154) 0x40de40 ADD	X14, X3, X10,LSL #4

  (154) 0x40de44 LDR	D27, [X14, #8]

  (154) 0x40de48 FMUL	D0, D28, D28

  (154) 0x40de4c FMADD	D1, D29, D29, D0

  (154) 0x40de50 FDIV	D3, D21, D27

  (154) 0x40de54 FMADD	D2, D31, D31, D1

  (154) 0x40de58 FMADD	D30, D3, D2, D30

  (154) 0x40de5c LDRSW	X18, [X4, X23,LSL #2]

  (154) 0x40de60 ADD	X23, X23, #1

  (154) 0x40de64 LDP	D4, D5, [X15]

  (154) 0x40de68 ADD	X15, X15, #24

  (154) 0x40de6c LDUR	D18, [X15, #504]

  (154) 0x40de70 ADD	X30, X3, X18,LSL #4

  (154) 0x40de74 LDR	D16, [X30, #8]

  (154) 0x40de78 FMUL	D6, D5, D5

  (154) 0x40de7c FMADD	D7, D4, D4, D6

  (154) 0x40de80 FDIV	D17, D21, D16

  (154) 0x40de84 FMADD	D19, D18, D18, D7

  (154) 0x40de88 FMADD	D30, D17, D19, D30

  (154) 0x40de8c LDRSW	X21, [X4, X23,LSL #2]

  (154) 0x40de90 ADD	X23, X23, #1

  (154) 0x40de94 LDP	D20, D22, [X15]

  (154) 0x40de98 ADD	X15, X15, #24

  (154) 0x40de9c LDUR	D29, [X15, #504]

  (154) 0x40dea0 ADD	X22, X3, X21,LSL #4

  (154) 0x40dea4 LDR	D25, [X22, #8]

  (154) 0x40dea8 FMUL	D23, D22, D22

  (154) 0x40deac FMADD	D24, D20, D20, D23

  (154) 0x40deb0 FDIV	D26, D21, D25

  (154) 0x40deb4 FMADD	D28, D29, D29, D24

  (154) 0x40deb8 FMADD	D30, D26, D28, D30

  (154) 0x40debc CMP	X23, X11

  (154) 0x40dec0 B.EQ	40df88

    (155) 0x40dec4 LDP	D31, D0, [X15]

    (155) 0x40dec8 ADD	X2, X23, #1

    (155) 0x40decc ADD	X10, X15, #24

    (155) 0x40ded0 ADD	X0, X23, #2

    (155) 0x40ded4 ADD	X14, X23, #3

    (155) 0x40ded8 LDRSW	X1, [X4, X23,LSL #2]

    (155) 0x40dedc ADD	X9, X15, #48

    (155) 0x40dee0 ADD	X8, X15, #72

    (155) 0x40dee4 ADD	X23, X23, #4

    (155) 0x40dee8 LDP	D5, D6, [X15, #16]

    (155) 0x40deec ADD	X15, X15, #96

    (155) 0x40def0 FMUL	D1, D0, D0

    (155) 0x40def4 LDRSW	X5, [X4, X2,LSL #2]

    (155) 0x40def8 ADD	X7, X3, X1,LSL #4

    (155) 0x40defc LDP	D27, D3, [X10, #8]

    (155) 0x40df00 LDRSW	X6, [X4, X0,LSL #2]

    (155) 0x40df04 FMADD	D2, D31, D31, D1

    (155) 0x40df08 ADD	X18, X3, X5,LSL #4

    (155) 0x40df0c LDR	D31, [X7, #8]

    (155) 0x40df10 LDR	D22, [X18, #8]

    (155) 0x40df14 FMUL	D4, D27, D27

    (155) 0x40df18 ADD	X30, X3, X6,LSL #4

    (155) 0x40df1c FMADD	D24, D5, D5, D2

    (155) 0x40df20 LDRSW	X21, [X4, X14,LSL #2]

    (155) 0x40df24 FDIV	D2, D21, D31

    (155) 0x40df28 LDR	D28, [X30, #8]

    (155) 0x40df2c LDP	D7, D16, [X9, #8]

    (155) 0x40df30 FMADD	D18, D6, D6, D4

    (155) 0x40df34 ADD	X22, X3, X21,LSL #4

    (155) 0x40df38 LDUR	D19, [X15, #464]

    (155) 0x40df3c FDIV	D29, D21, D22

    (155) 0x40df40 LDR	D26, [X22, #8]

    (155) 0x40df44 FMADD	D23, D3, D3, D18

    (155) 0x40df48 FMUL	D17, D7, D7

    (155) 0x40df4c LDUR	D7, [X15, #488]

    (155) 0x40df50 FDIV	D1, D21, D28

    (155) 0x40df54 FMADD	D20, D19, D19, D17

    (155) 0x40df58 FMADD	D27, D2, D24, D30

    (155) 0x40df5c LDP	D3, D30, [X8, #8]

    (155) 0x40df60 FDIV	D0, D21, D26

    (155) 0x40df64 FMADD	D25, D16, D16, D20

    (155) 0x40df68 FMADD	D5, D29, D23, D27

    (155) 0x40df6c FMUL	D4, D3, D3

    (155) 0x40df70 FMADD	D16, D7, D7, D4

    (155) 0x40df74 FMADD	D6, D1, D25, D5

    (155) 0x40df78 FMADD	D17, D30, D30, D16

    (155) 0x40df7c FMADD	D30, D0, D17, D6

    (155) 0x40df80 CMP	X23, X11

    (155) 0x40df84 B.NE	40dec4

  (154) 0x40df88 ADD	X13, X13, #1

  (154) 0x40df8c ADD	X12, X12, #64

  (154) 0x40df90 CMP	W17, W13

  (154) 0x40df94 B.GT	40dde8

(153) 0x40df98 ADD	X20, X20, #8

(153) 0x40df9c LDR	X1, [X20]

  (152) 0x40dfa0 FMOV	D21, X1

  (152) 0x40dfa4 ORR	X19, XZR, X1

  (152) 0x40dfa8 FADD	D24, D30, D21

  (152) 0x40dfac FMOV	X17, D24

  (152) 0x40dfb0 CAS	X19, X17, [X20]

  (152) 0x40dfb4 CMP	X1, X19

  (152) 0x40dfb8 B.NE	40dfdc

(153) 0x40dfbc LDR	X23, [SP, #48]

(153) 0x40dfc0 LDP	X19, X20, [SP, #16]

(153) 0x40dfc4 LDP	X21, X22, [SP, #32]

(153) 0x40dfc8 LDP	X29, X30, [SP], #64

(153) 0x40dfcc RET

(153) 0x40dfd0 ADD	W15, W15, #1

(153) 0x40dfd4 MOVZ	W0, #0

(153) 0x40dfd8 B	40ddc4

  (152) 0x40dfdc ORR	X1, XZR, X19

  (152) 0x40dfe0 B	40dfa0

Coverage (%)	Name	Source Location	Module
►98.97+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.03+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	timestep	timestep.c:120	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.13
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40dd80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W12, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W15, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W15, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W12, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 40dfd0 <kineticEnergy._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	2.13
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40dd80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [X19, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W12, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W22, [X23, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SDIV W15, W22, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W0, W15, W21, W22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W12, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 40dfd0 <kineticEnergy._omp_fn.0+0x250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼kineticEnergy._omp_fn.0–	0.08	0.01
▼Loop 153 - timestep.c:107-116 - exec–	0.00	0.00
▼Loop 154 - timestep.c:110-116 - exec–	0.02	0.01
○Loop 155 - timestep.c:110-116 - exec	0.07	0.01
○Loop 152 - timestep.c:107-107 - exec	0.00	0.00

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code