OV - exec - Function advanceVelocity._omp

	Function: advanceVelocity._omp_fn.0	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 2.16% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x40d920 STP	X29, X30, [SP, #976]!

0x40d924 ADD	X29, SP, #0

0x40d928 STP	X19, X20, [SP, #16]

0x40d92c ORR	X20, XZR, X0

0x40d930 STR	X21, [SP, #32]

0x40d934 LDR	W21, [X0, #16]

0x40d938 BL	4025a0

0x40d93c ORR	W19, WZR, W0

0x40d940 BL	4026a0

0x40d944 ORR	W3, WZR, W0

0x40d948 SDIV	W11, W21, W19

0x40d94c MSUB	W1, W11, W19, W21

0x40d950 CMP	W0, W1

0x40d954 B.LT	40dd70

0x40d958 MADD	W2, W11, W3, W1

0x40d95c ADD	W30, W11, W2

0x40d960 CMP	W2, W30

0x40d964 B.GE	40dba8

0x40d968 LDR	X13, [X20]

0x40d96c MOVZ	W0, #1536

0x40d970 SBFM	X10, X2, #0, #31

0x40d974 MOVZ	W15, #24

0x40d978 MOVZ	W14, #48

0x40d97c LDR	D31, [X20, #8]

0x40d980 SMADDL	X3, W2, W0, XZR

0x40d984 LDR	X4, [X13, #24]

0x40d988 DUP	V30.2D, V31.D[0]

0x40d98c LDR	X12, [X4, #120]

    (148) 0x40d990 LDR	W20, [X12, X10,LSL #2]

    (148) 0x40d994 CMP	W20, #0

    (148) 0x40d998 B.LE	40db98

    (148) 0x40d99c LDR	X5, [X13, #32]

    (148) 0x40d9a0 LDP	X16, X8, [X5, #32]

    (148) 0x40d9a4 ADD	X18, X16, X3

    (148) 0x40d9a8 ADD	X6, X8, X3

    (148) 0x40d9ac CMP	W20, #1

    (148) 0x40d9b0 B.EQ	40dbb8

    (148) 0x40d9b4 ADD	X7, X3, #48

    (148) 0x40d9b8 ADD	X6, X8, X3

    (148) 0x40d9bc ADD	X9, X16, X7

    (148) 0x40d9c0 ADD	X17, X8, X7

    (148) 0x40d9c4 CMP	X6, X9

    (148) 0x40d9c8 ADD	X18, X16, X3

    (148) 0x40d9cc CCMP	X18, X17, #2, #3

    (148) 0x40d9d0 B.CC	40dbb8

    (148) 0x40d9d4 UBFM	W21, W20, #1, #31

    (148) 0x40d9d8 ORR	X19, XZR, #3841

    (148) 0x40d9dc MOVK	X19, #43691

    (148) 0x40d9e0 ORR	X0, XZR, X18

    (148) 0x40d9e4 UMADDL	X11, W21, W14, X18

    (148) 0x40d9e8 MOVK	X19, #2730

    (148) 0x40d9ec ORR	X1, XZR, X6

    (148) 0x40d9f0 SUB	X2, X11, X18

    (148) 0x40d9f4 SUB	X4, X2, #48

    (148) 0x40d9f8 UBFM	X5, X4, #4, #63

    (148) 0x40d9fc MADD	X7, X5, X19, XZR

    (148) 0x40da00 ADD	X9, X7, #1

    (148) 0x40da04 ANDS	X17, X9, #4160

    (148) 0x40da08 B.EQ	40daa0

    (148) 0x40da0c CMP	X17, #1

    (148) 0x40da10 B.EQ	40da70

    (148) 0x40da14 CMP	X17, #2

    (148) 0x40da18 B.EQ	40da48

    (148) 0x40da1c LDP	Q1, Q0, [X18, #16]

    (148) 0x40da20 ADD	X0, X18, #48

    (148) 0x40da24 ADD	X1, X6, #48

    (148) 0x40da28 LDP	Q3, Q2, [X6, #16]

    (148) 0x40da2c LDR	Q21, [X8, X3]

    (148) 0x40da30 LDR	Q20, [X16, X3]

    (148) 0x40da34 FMLA	V1.2D, V30.2D, V3.2D

    (148) 0x40da38 FMLA	V20.2D, V30.2D, V21.2D

    (148) 0x40da3c FMLA	V0.2D, V30.2D, V2.2D

    (148) 0x40da40 STR	Q20, [X16, X3]

    (148) 0x40da44 STP	Q1, Q0, [X18, #16]

    (148) 0x40da48 LDR	Q22, [X1, #32]

    (148) 0x40da4c LDP	Q6, Q19, [X0]

    (148) 0x40da50 ADD	X0, X0, #48

    (148) 0x40da54 LDP	Q7, Q23, [X1], #48

    (148) 0x40da58 LDUR	Q18, [X0, #496]

    (148) 0x40da5c FMLA	V18.2D, V30.2D, V22.2D

    (148) 0x40da60 FMLA	V19.2D, V30.2D, V23.2D

    (148) 0x40da64 FMLA	V6.2D, V30.2D, V7.2D

    (148) 0x40da68 STUR	Q18, [X0, #496]

    (148) 0x40da6c STP	Q6, Q19, [X0, #2000]

    (148) 0x40da70 LDR	Q16, [X1, #32]

    (148) 0x40da74 LDP	Q4, Q25, [X0]

    (148) 0x40da78 ADD	X0, X0, #48

    (148) 0x40da7c LDP	Q5, Q17, [X1], #48

    (148) 0x40da80 LDUR	Q24, [X0, #496]

    (148) 0x40da84 FMLA	V24.2D, V30.2D, V16.2D

    (148) 0x40da88 FMLA	V25.2D, V30.2D, V17.2D

    (148) 0x40da8c FMLA	V4.2D, V30.2D, V5.2D

    (148) 0x40da90 STUR	Q24, [X0, #496]

    (148) 0x40da94 STP	Q4, Q25, [X0, #2000]

    (148) 0x40da98 CMP	X0, X11

    (148) 0x40da9c B.EQ	40db54

      (150) 0x40daa0 LDP	Q27, Q26, [X1, #16]

      (150) 0x40daa4 ORR	X21, XZR, X1

      (150) 0x40daa8 ADD	X19, X0, #48

      (150) 0x40daac ADD	X6, X0, #96

      (150) 0x40dab0 ADD	X18, X1, #96

      (150) 0x40dab4 LDP	Q28, Q3, [X0, #32]

      (150) 0x40dab8 ADD	X2, X0, #144

      (150) 0x40dabc ADD	X4, X1, #144

      (150) 0x40dac0 ADD	X1, X1, #192

      (150) 0x40dac4 LDP	Q21, Q29, [X0]

      (150) 0x40dac8 ADD	X0, X0, #192

      (150) 0x40dacc LDR	Q20, [X21], #48

      (150) 0x40dad0 FMLA	V28.2D, V30.2D, V26.2D

      (150) 0x40dad4 FMLA	V29.2D, V30.2D, V27.2D

      (150) 0x40dad8 FMLA	V21.2D, V30.2D, V20.2D

      (150) 0x40dadc STUR	Q28, [X0, #352]

      (150) 0x40dae0 STP	Q21, Q29, [X0, #1856]

      (150) 0x40dae4 LDP	Q2, Q6, [X19, #16]

      (150) 0x40dae8 LDP	Q1, Q0, [X21, #16]

      (150) 0x40daec LDUR	Q19, [X1, #368]

      (150) 0x40daf0 FMLA	V3.2D, V30.2D, V19.2D

      (150) 0x40daf4 FMLA	V2.2D, V30.2D, V1.2D

      (150) 0x40daf8 FMLA	V6.2D, V30.2D, V0.2D

      (150) 0x40dafc STUR	Q3, [X0, #368]

      (150) 0x40db00 STP	Q2, Q6, [X19, #16]

      (150) 0x40db04 LDP	Q22, Q7, [X6, #16]

      (150) 0x40db08 LDP	Q23, Q18, [X18, #16]

      (150) 0x40db0c LDUR	Q25, [X1, #416]

      (150) 0x40db10 LDUR	Q4, [X0, #416]

      (150) 0x40db14 FMLA	V22.2D, V30.2D, V23.2D

      (150) 0x40db18 FMLA	V4.2D, V30.2D, V25.2D

      (150) 0x40db1c FMLA	V7.2D, V30.2D, V18.2D

      (150) 0x40db20 STUR	Q4, [X0, #416]

      (150) 0x40db24 STP	Q22, Q7, [X6, #16]

      (150) 0x40db28 LDP	Q16, Q5, [X2, #16]

      (150) 0x40db2c LDP	Q24, Q17, [X4, #16]

      (150) 0x40db30 LDUR	Q21, [X0, #464]

      (150) 0x40db34 LDUR	Q29, [X1, #464]

      (150) 0x40db38 FMLA	V16.2D, V30.2D, V24.2D

      (150) 0x40db3c FMLA	V21.2D, V30.2D, V29.2D

      (150) 0x40db40 FMLA	V5.2D, V30.2D, V17.2D

      (150) 0x40db44 STUR	Q21, [X0, #464]

      (150) 0x40db48 STP	Q16, Q5, [X2, #16]

      (150) 0x40db4c CMP	X0, X11

      (150) 0x40db50 B.NE	40daa0

    (148) 0x40db54 AND	W11, W20, #1951

    (148) 0x40db58 TBZ	W20, #0, 40db98

    (148) 0x40db5c ADD	W20, W11, W10,LSL #6

    (148) 0x40db60 SMADDL	X5, W20, W15, XZR

    (148) 0x40db64 LDR	D27, [X8, X5]

    (148) 0x40db68 ADD	X7, X16, X5

    (148) 0x40db6c ADD	X8, X8, X5

    (148) 0x40db70 LDR	D26, [X16, X5]

    (148) 0x40db74 FMADD	D20, D31, D27, D26

    (148) 0x40db78 STR	D20, [X16, X5]

    (148) 0x40db7c LDR	D2, [X8, #8]

    (148) 0x40db80 LDP	D3, D28, [X7, #8]

    (148) 0x40db84 FMADD	D6, D31, D2, D3

    (148) 0x40db88 STR	D6, [X7, #8]

    (148) 0x40db8c LDR	D1, [X8, #16]

    (148) 0x40db90 FMADD	D0, D31, D1, D28

    (148) 0x40db94 STR	D0, [X7, #16]

    (148) 0x40db98 ADD	X10, X10, #1

    (148) 0x40db9c ADD	X3, X3, #1536

    (148) 0x40dba0 CMP	W30, W10

    (148) 0x40dba4 B.GT	40d990

(151) 0x40dba8 LDR	X21, [SP, #32]

(151) 0x40dbac LDP	X19, X20, [SP, #16]

(151) 0x40dbb0 LDP	X29, X30, [SP], #48

(151) 0x40dbb4 RET

  (149) 0x40dbb8 UMADDL	X17, W20, W15, X18

  (149) 0x40dbbc ORR	X16, XZR, #3841

  (149) 0x40dbc0 ORR	X0, XZR, X18

  (149) 0x40dbc4 MOVK	X16, #43691

  (149) 0x40dbc8 ORR	X1, XZR, X6

  (149) 0x40dbcc MOVK	X16, #2730

  (149) 0x40dbd0 SUB	X9, X17, X18

  (149) 0x40dbd4 SUB	X21, X9, #24

  (149) 0x40dbd8 UBFM	X19, X21, #3, #63

  (149) 0x40dbdc MADD	X2, X19, X16, XZR

  (149) 0x40dbe0 ADD	X4, X2, #1

  (149) 0x40dbe4 ANDS	X11, X4, #4160

  (149) 0x40dbe8 B.EQ	40dca0

  (149) 0x40dbec CMP	X11, #1

  (149) 0x40dbf0 B.EQ	40dc64

  (149) 0x40dbf4 CMP	X11, #2

  (149) 0x40dbf8 B.EQ	40dc30

  (149) 0x40dbfc LDR	D23, [X6]

  (149) 0x40dc00 ADD	X0, X18, #24

  (149) 0x40dc04 ADD	X1, X6, #24

  (149) 0x40dc08 LDP	D19, D22, [X18]

  (149) 0x40dc0c LDR	D7, [X18, #16]

  (149) 0x40dc10 FMADD	D18, D31, D23, D19

  (149) 0x40dc14 STR	D18, [X18]

  (149) 0x40dc18 LDR	D4, [X6, #8]

  (149) 0x40dc1c FMADD	D25, D31, D4, D22

  (149) 0x40dc20 STR	D25, [X18, #8]

  (149) 0x40dc24 LDR	D16, [X6, #16]

  (149) 0x40dc28 FMADD	D5, D31, D16, D7

  (149) 0x40dc2c STR	D5, [X18, #16]

  (149) 0x40dc30 LDR	D29, [X1]

  (149) 0x40dc34 ADD	X1, X1, #24

  (149) 0x40dc38 LDP	D24, D17, [X0]

  (149) 0x40dc3c ADD	X0, X0, #24

  (149) 0x40dc40 LDUR	D21, [X0, #504]

  (149) 0x40dc44 FMADD	D27, D31, D29, D24

  (149) 0x40dc48 STUR	D27, [X0, #488]

  (149) 0x40dc4c LDUR	D26, [X1, #496]

  (149) 0x40dc50 FMADD	D20, D31, D26, D17

  (149) 0x40dc54 STUR	D20, [X0, #496]

  (149) 0x40dc58 LDUR	D3, [X1, #504]

  (149) 0x40dc5c FMADD	D28, D31, D3, D21

  (149) 0x40dc60 STUR	D28, [X0, #504]

  (149) 0x40dc64 LDR	D0, [X1]

  (149) 0x40dc68 ADD	X1, X1, #24

  (149) 0x40dc6c LDP	D2, D6, [X0]

  (149) 0x40dc70 ADD	X0, X0, #24

  (149) 0x40dc74 LDUR	D1, [X0, #504]

  (149) 0x40dc78 FMADD	D19, D31, D0, D2

  (149) 0x40dc7c STUR	D19, [X0, #488]

  (149) 0x40dc80 LDUR	D22, [X1, #496]

  (149) 0x40dc84 FMADD	D7, D31, D22, D6

  (149) 0x40dc88 STUR	D7, [X0, #496]

  (149) 0x40dc8c LDUR	D23, [X1, #504]

  (149) 0x40dc90 FMADD	D18, D31, D23, D1

  (149) 0x40dc94 STUR	D18, [X0, #504]

  (149) 0x40dc98 CMP	X17, X0

  (149) 0x40dc9c B.EQ	40db98

    (147) 0x40dca0 LDR	D5, [X1]

    (147) 0x40dca4 ADD	X18, X0, #24

    (147) 0x40dca8 ADD	X6, X0, #48

    (147) 0x40dcac ADD	X5, X0, #72

    (147) 0x40dcb0 ORR	X20, XZR, X1

    (147) 0x40dcb4 LDP	D4, D25, [X0]

    (147) 0x40dcb8 ADD	X1, X1, #96

    (147) 0x40dcbc LDP	D16, D24, [X0, #16]

    (147) 0x40dcc0 ADD	X0, X0, #96

    (147) 0x40dcc4 FMADD	D17, D31, D5, D4

    (147) 0x40dcc8 STUR	D17, [X0, #416]

    (147) 0x40dccc LDUR	D21, [X1, #424]

    (147) 0x40dcd0 FMADD	D29, D31, D21, D25

    (147) 0x40dcd4 STUR	D29, [X0, #424]

    (147) 0x40dcd8 LDUR	D27, [X1, #432]

    (147) 0x40dcdc FMADD	D26, D31, D27, D16

    (147) 0x40dce0 STUR	D26, [X0, #432]

    (147) 0x40dce4 LDUR	D20, [X1, #440]

    (147) 0x40dce8 FMADD	D3, D31, D20, D24

    (147) 0x40dcec STUR	D3, [X0, #440]

    (147) 0x40dcf0 LDUR	D6, [X1, #448]

    (147) 0x40dcf4 LDP	D28, D2, [X18, #8]

    (147) 0x40dcf8 FMADD	D1, D31, D6, D28

    (147) 0x40dcfc STR	D1, [X18, #8]

    (147) 0x40dd00 LDUR	D0, [X1, #456]

    (147) 0x40dd04 FMADD	D19, D31, D0, D2

    (147) 0x40dd08 STR	D19, [X18, #16]

    (147) 0x40dd0c LDUR	D7, [X1, #464]

    (147) 0x40dd10 LDUR	D22, [X0, #464]

    (147) 0x40dd14 FMADD	D23, D31, D7, D22

    (147) 0x40dd18 STUR	D23, [X0, #464]

    (147) 0x40dd1c LDUR	D25, [X1, #472]

    (147) 0x40dd20 LDP	D18, D4, [X6, #8]

    (147) 0x40dd24 FMADD	D16, D31, D25, D18

    (147) 0x40dd28 STR	D16, [X6, #8]

    (147) 0x40dd2c LDUR	D24, [X1, #480]

    (147) 0x40dd30 FMADD	D5, D31, D24, D4

    (147) 0x40dd34 STR	D5, [X6, #16]

    (147) 0x40dd38 LDUR	D17, [X0, #488]

    (147) 0x40dd3c LDUR	D21, [X1, #488]

    (147) 0x40dd40 FMADD	D29, D31, D21, D17

    (147) 0x40dd44 STUR	D29, [X0, #488]

    (147) 0x40dd48 LDUR	D27, [X1, #496]

    (147) 0x40dd4c LDP	D26, D20, [X5, #8]

    (147) 0x40dd50 FMADD	D3, D31, D27, D26

    (147) 0x40dd54 STR	D3, [X5, #8]

    (147) 0x40dd58 LDR	D28, [X20, #88]

    (147) 0x40dd5c FMADD	D2, D31, D28, D20

    (147) 0x40dd60 STR	D2, [X5, #16]

    (147) 0x40dd64 CMP	X17, X0

    (147) 0x40dd68 B.NE	40dca0

  (149) 0x40dd6c B	40db98

0x40dd70 ADD	W11, W11, #1

0x40dd74 MOVZ	W1, #0

0x40dd78 B	40d958

0x40dd7c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.12+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 45% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50
cycles	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.88
Overall L1	5.00-12.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

3% of peak load performance is reached (2.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W11, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W11, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40dd70 <advanceVelocity._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W11, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40dba8 <advanceVelocity._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X10, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVZ W15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W14, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D31, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SMADDL X3, W2, W0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X12, [X4, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 40d958 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 45% of vector register length is used (average across all VPU instructions).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50
cycles	2.50	2.50	3.17	3.25	3.17	3.17	4.00	3.25	0.25	0.25	0.25	0.25	2.83	2.50	2.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	3.88
Overall L1	5.00-12.50

Vectorization ratios

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

3% of peak load performance is reached (2.88 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W3, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W11, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W1, W11, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40dd70 <advanceVelocity._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W11, W3, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W11, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W2, W30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40dba8 <advanceVelocity._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W0, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X10, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
MOVZ W15, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W14, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D31, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SMADDL X3, W2, W0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X4, [X13, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V30.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR X12, [X4, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD W11, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 40d958 <advanceVelocity._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity._omp_fn.0–	2.16	0.18
▼Loop 151 - timestep.c:71-78 - exec–	0.00	0.00
▼Loop 149 - timestep.c:71-78 - exec–	0.00	0.00
▼Loop 148 - timestep.c:74-78 - exec–	0.60	0.04
○Loop 150 - timestep.c:74-76 - exec	1.56	0.09
○Loop 147 - timestep.c:74-78 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code