OV - exec - Function advancePosition._omp

	Function: advancePosition._omp_fn.0	Module: exec	Source: timestep.c:85-94	Coverage (incl. loops): 1.27% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x40d740 STP	X29, X30, [SP, #976]!

0x40d744 ADD	X29, SP, #0

0x40d748 STP	X19, X20, [SP, #16]

0x40d74c ORR	X20, XZR, X0

0x40d750 STR	X21, [SP, #32]

0x40d754 LDR	W21, [X0, #16]

0x40d758 BL	4025a0

0x40d75c ORR	W19, WZR, W0

0x40d760 BL	4026a0

0x40d764 ORR	W9, WZR, W0

0x40d768 SDIV	W13, W21, W19

0x40d76c MSUB	W1, W13, W19, W21

0x40d770 CMP	W0, W1

0x40d774 B.LT	40d910

(144) 0x40d778 MADD	W2, W13, W9, W1

(144) 0x40d77c ADD	W16, W13, W2

(144) 0x40d780 CMP	W2, W16

(144) 0x40d784 B.GE	40d900

(144) 0x40d788 LDR	X14, [X20]

(144) 0x40d78c MOVZ	W0, #1536

(144) 0x40d790 FMOV	D30, #1.0000000

(144) 0x40d794 SBFM	X12, X2, #0, #31

(144) 0x40d798 SBFM	X11, X2, #58, #31

(144) 0x40d79c LDR	D31, [X20, #8]

(144) 0x40d7a0 SMADDL	X9, W2, W0, XZR

(144) 0x40d7a4 LDR	X3, [X14, #24]

(144) 0x40d7a8 LDR	X15, [X3, #120]

  (145) 0x40d7ac LDR	W6, [X15, X12,LSL #2]

  (145) 0x40d7b0 CMP	W6, #0

  (145) 0x40d7b4 B.LE	40d8ec

  (145) 0x40d7b8 LDP	X5, X7, [X14, #32]

  (145) 0x40d7bc SBFM	X4, X11, #0, #31

  (145) 0x40d7c0 ADD	X10, X11, W6,SXTW

  (145) 0x40d7c4 LDR	X18, [X5, #32]

  (145) 0x40d7c8 LDP	X8, X17, [X5, #16]

  (145) 0x40d7cc ADD	X21, X18, X9

  (145) 0x40d7d0 ADD	X19, X17, X9

  (145) 0x40d7d4 TBZ	W6, #0, 40d840

  (145) 0x40d7d8 LDRSW	X30, [X8, X11,SXTW #2]

  (145) 0x40d7dc ADD	X4, X4, #1

  (145) 0x40d7e0 ADD	X21, X21, #24

  (145) 0x40d7e4 LDR	D23, [X18, X9]

  (145) 0x40d7e8 LDR	D22, [X17, X9]

  (145) 0x40d7ec ADD	X20, X7, X30,LSL #4

  (145) 0x40d7f0 LDR	D29, [X20, #8]

  (145) 0x40d7f4 FMUL	D0, D31, D23

  (145) 0x40d7f8 FDIV	D1, D30, D29

  (145) 0x40d7fc FMADD	D2, D1, D0, D22

  (145) 0x40d800 STR	D2, [X17, X9]

  (145) 0x40d804 LDUR	D21, [X21, #496]

  (145) 0x40d808 LDP	D20, D18, [X19, #8]

  (145) 0x40d80c ADD	X19, X19, #24

  (145) 0x40d810 FMUL	D3, D31, D21

  (145) 0x40d814 FMADD	D4, D1, D3, D20

  (145) 0x40d818 STUR	D4, [X19, #496]

  (145) 0x40d81c LDUR	D19, [X21, #504]

  (145) 0x40d820 FMUL	D5, D31, D19

  (145) 0x40d824 FMADD	D6, D1, D5, D18

  (145) 0x40d828 STUR	D6, [X19, #504]

  (145) 0x40d82c CMP	X10, X4

  (145) 0x40d830 B.EQ	40d8ec

  (145) 0x40d834 HINT	#0

  (145) 0x40d838 HINT	#0

  (145) 0x40d83c HINT	#0

    (146) 0x40d840 LDRSW	X13, [X8, X4,LSL #2]

    (146) 0x40d844 ADD	X1, X4, #1

    (146) 0x40d848 ADD	X2, X19, #24

    (146) 0x40d84c ORR	X0, XZR, X21

    (146) 0x40d850 ADD	X4, X4, #2

    (146) 0x40d854 LDR	D17, [X21]

    (146) 0x40d858 ADD	X21, X21, #48

    (146) 0x40d85c LDP	D16, D24, [X19]

    (146) 0x40d860 ADD	X3, X7, X13,LSL #4

    (146) 0x40d864 LDRSW	X6, [X8, X1,LSL #2]

    (146) 0x40d868 LDR	D26, [X3, #8]

    (146) 0x40d86c FMUL	D7, D31, D17

    (146) 0x40d870 LDP	D25, D27, [X19, #16]

    (146) 0x40d874 ADD	X19, X19, #48

    (146) 0x40d878 ADD	X5, X7, X6,LSL #4

    (146) 0x40d87c FDIV	D28, D30, D26

    (146) 0x40d880 FMADD	D23, D28, D7, D16

    (146) 0x40d884 STUR	D23, [X19, #464]

    (146) 0x40d888 LDUR	D22, [X21, #472]

    (146) 0x40d88c FMUL	D0, D31, D22

    (146) 0x40d890 FMADD	D29, D28, D0, D24

    (146) 0x40d894 STUR	D29, [X19, #472]

    (146) 0x40d898 LDUR	D1, [X21, #480]

    (146) 0x40d89c FMUL	D2, D31, D1

    (146) 0x40d8a0 FMADD	D20, D28, D2, D25

    (146) 0x40d8a4 STUR	D20, [X19, #480]

    (146) 0x40d8a8 LDR	D3, [X5, #8]

    (146) 0x40d8ac LDUR	D18, [X21, #488]

    (146) 0x40d8b0 FDIV	D4, D30, D3

    (146) 0x40d8b4 FMUL	D21, D31, D18

    (146) 0x40d8b8 FMADD	D19, D4, D21, D27

    (146) 0x40d8bc STUR	D19, [X19, #488]

    (146) 0x40d8c0 LDUR	D16, [X21, #496]

    (146) 0x40d8c4 LDP	D5, D6, [X2, #8]

    (146) 0x40d8c8 FMUL	D24, D31, D16

    (146) 0x40d8cc FMADD	D25, D4, D24, D5

    (146) 0x40d8d0 STR	D25, [X2, #8]

    (146) 0x40d8d4 LDR	D27, [X0, #40]

    (146) 0x40d8d8 FMUL	D17, D31, D27

    (146) 0x40d8dc FMADD	D7, D4, D17, D6

    (146) 0x40d8e0 STR	D7, [X2, #16]

    (146) 0x40d8e4 CMP	X10, X4

    (146) 0x40d8e8 B.NE	40d840

  (145) 0x40d8ec ADD	X12, X12, #1

  (145) 0x40d8f0 ADD	X9, X9, #1536

  (145) 0x40d8f4 ADD	X11, X11, #64

  (145) 0x40d8f8 CMP	W16, W12

  (145) 0x40d8fc B.GT	40d7ac

(144) 0x40d900 LDR	X21, [SP, #32]

(144) 0x40d904 LDP	X19, X20, [SP, #16]

(144) 0x40d908 LDP	X29, X30, [SP], #48

(144) 0x40d90c RET

(144) 0x40d910 ADD	W13, W13, #1

(144) 0x40d914 MOVZ	W1, #0

(144) 0x40d918 B	40d778

0x40d91c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.04+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 4 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W13, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W13, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40d910 <advancePosition._omp_fn.0+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 4 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.75
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40d740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SDIV W13, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W13, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40d910 <advancePosition._omp_fn.0+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advancePosition._omp_fn.0–	1.27	0.10
▼Loop 144 - timestep.c:85-94 - exec–	0.00	0.00
▼Loop 145 - timestep.c:88-94 - exec–	0.11	0.01
○Loop 146 - timestep.c:88-94 - exec	1.16	0.07

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code