OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.0	Module: exec	Source: ljForce.c:157-161 [...]	Coverage (incl. loops): 2.06% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 157 - 161

--------------------------------------------------------------------------------

157:    #pragma omp parallel for

158:    for (int ii=0; ii<fSize; ++ii)

159:    {

160:       zeroReal3(s->atoms->f[ii]);

161:       s->atoms->U[ii] = 0.;

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

0x40ac40 STP	X29, X30, [SP, #976]!

0x40ac44 ADD	X29, SP, #0

0x40ac48 STP	X19, X20, [SP, #16]

0x40ac4c ORR	X20, XZR, X0

0x40ac50 STR	X21, [SP, #32]

0x40ac54 LDR	W21, [X0, #8]

0x40ac58 BL	4025a0

0x40ac5c ORR	W19, WZR, W0

0x40ac60 BL	4026a0

0x40ac64 SDIV	W4, W21, W19

0x40ac68 MSUB	W1, W4, W19, W21

0x40ac6c CMP	W0, W1

0x40ac70 B.LT	40ae68

(126) 0x40ac74 MADD	W2, W4, W0, WZR

(126) 0x40ac78 ADD	W5, W1, W2

(126) 0x40ac7c ADD	W3, W4, W5

(126) 0x40ac80 CMP	W5, W3

(126) 0x40ac84 B.GE	40ae58

(126) 0x40ac88 LDR	X6, [X20]

(126) 0x40ac8c SUB	W0, W4, #1

(126) 0x40ac90 LDR	X7, [X6, #32]

(126) 0x40ac94 LDP	X8, X17, [X7, #40]

(126) 0x40ac98 CMP	W0, #5

(126) 0x40ac9c B.LS	40ae74

(126) 0x40aca0 SBFM	X9, X2, #0, #31

(126) 0x40aca4 ADD	X10, X9, W1,SXTW

(126) 0x40aca8 ADD	X11, X10, W4,UXTW

(126) 0x40acac ADD	X12, X11, X11,LSL #1

(126) 0x40acb0 ADD	X13, X10, X10,LSL #1

(126) 0x40acb4 ADD	X14, X8, X12,LSL #3

(126) 0x40acb8 ADD	X15, X17, X10,LSL #3

(126) 0x40acbc ADD	X16, X17, X11,LSL #3

(126) 0x40acc0 ADD	X18, X8, X13,LSL #3

(126) 0x40acc4 CMP	X14, X15

(126) 0x40acc8 CCMP	X16, X18, #0, #8

(126) 0x40accc B.HI	40ae74

(126) 0x40acd0 UBFM	W30, W4, #1, #31

(126) 0x40acd4 MOVI	V31.2D, #0

(126) 0x40acd8 ORR	X0, XZR, X18

(126) 0x40acdc ADD	X20, X15, W30,UXTW #4

(126) 0x40ace0 UBFM	X21, X30, #60, #30

(126) 0x40ace4 ORR	X2, XZR, X15

(126) 0x40ace8 SUB	X19, X21, #16

(126) 0x40acec UBFM	X1, X19, #4, #63

(126) 0x40acf0 ADD	X3, X1, #1

(126) 0x40acf4 ANDS	X6, X3, #4224

(126) 0x40acf8 B.EQ	40ada4

(126) 0x40acfc CMP	X6, #1

(126) 0x40ad00 B.EQ	40ad8c

(126) 0x40ad04 CMP	X6, #2

(126) 0x40ad08 B.EQ	40ad7c

(126) 0x40ad0c CMP	X6, #3

(126) 0x40ad10 B.EQ	40ad6c

(126) 0x40ad14 CMP	X6, #4

(126) 0x40ad18 B.EQ	40ad5c

(126) 0x40ad1c CMP	X6, #5

(126) 0x40ad20 B.EQ	40ad4c

(126) 0x40ad24 CMP	X6, #6

(126) 0x40ad28 B.EQ	40ad3c

(126) 0x40ad2c ADD	X0, X18, #48

(126) 0x40ad30 STR	Q31, [X18, #32]

(126) 0x40ad34 STP	Q31, Q31, [X18]

(126) 0x40ad38 STR	Q31, [X2], #16

(126) 0x40ad3c ADD	X0, X0, #48

(126) 0x40ad40 STUR	Q31, [X0, #496]

(126) 0x40ad44 STP	Q31, Q31, [X0, #2000]

(126) 0x40ad48 STR	Q31, [X2], #16

(126) 0x40ad4c ADD	X0, X0, #48

(126) 0x40ad50 STUR	Q31, [X0, #496]

(126) 0x40ad54 STP	Q31, Q31, [X0, #2000]

(126) 0x40ad58 STR	Q31, [X2], #16

(126) 0x40ad5c ADD	X0, X0, #48

(126) 0x40ad60 STUR	Q31, [X0, #496]

(126) 0x40ad64 STP	Q31, Q31, [X0, #2000]

(126) 0x40ad68 STR	Q31, [X2], #16

(126) 0x40ad6c ADD	X0, X0, #48

(126) 0x40ad70 STUR	Q31, [X0, #496]

(126) 0x40ad74 STP	Q31, Q31, [X0, #2000]

(126) 0x40ad78 STR	Q31, [X2], #16

(126) 0x40ad7c ADD	X0, X0, #48

(126) 0x40ad80 STUR	Q31, [X0, #496]

(126) 0x40ad84 STP	Q31, Q31, [X0, #2000]

(126) 0x40ad88 STR	Q31, [X2], #16

(126) 0x40ad8c STP	Q31, Q31, [X0]

(126) 0x40ad90 STR	Q31, [X0, #32]

(126) 0x40ad94 ADD	X0, X0, #48

(126) 0x40ad98 STR	Q31, [X2], #16

(126) 0x40ad9c CMP	X20, X2

(126) 0x40ada0 B.EQ	40ae34

  (128) 0x40ada4 ORR	X9, XZR, X2

  (128) 0x40ada8 STR	Q31, [X0, #32]

  (128) 0x40adac ADD	X14, X0, #48

  (128) 0x40adb0 STP	Q31, Q31, [X0]

  (128) 0x40adb4 STR	Q31, [X9], #16

  (128) 0x40adb8 ADD	X13, X0, #96

  (128) 0x40adbc ADD	X12, X0, #144

  (128) 0x40adc0 STR	Q31, [X0, #48]

  (128) 0x40adc4 ADD	X11, X0, #192

  (128) 0x40adc8 ADD	X10, X0, #240

  (128) 0x40adcc STP	Q31, Q31, [X14, #16]

  (128) 0x40add0 STR	Q31, [X2, #16]

  (128) 0x40add4 ADD	X7, X0, #288

  (128) 0x40add8 ADD	X15, X0, #336

  (128) 0x40addc STR	Q31, [X0, #96]

  (128) 0x40ade0 ADD	X2, X2, #128

  (128) 0x40ade4 ADD	X0, X0, #384

  (128) 0x40ade8 STP	Q31, Q31, [X13, #16]

  (128) 0x40adec STR	Q31, [X9, #16]

  (128) 0x40adf0 STUR	Q31, [X0, #272]

  (128) 0x40adf4 STP	Q31, Q31, [X12, #16]

  (128) 0x40adf8 STUR	Q31, [X2, #432]

  (128) 0x40adfc STUR	Q31, [X0, #320]

  (128) 0x40ae00 STP	Q31, Q31, [X11, #16]

  (128) 0x40ae04 STUR	Q31, [X2, #448]

  (128) 0x40ae08 STUR	Q31, [X0, #368]

  (128) 0x40ae0c STP	Q31, Q31, [X10, #16]

  (128) 0x40ae10 STUR	Q31, [X2, #464]

  (128) 0x40ae14 STUR	Q31, [X0, #416]

  (128) 0x40ae18 STP	Q31, Q31, [X7, #16]

  (128) 0x40ae1c STUR	Q31, [X2, #480]

  (128) 0x40ae20 STUR	Q31, [X0, #464]

  (128) 0x40ae24 STP	Q31, Q31, [X15, #16]

  (128) 0x40ae28 STUR	Q31, [X2, #496]

  (128) 0x40ae2c CMP	X20, X2

  (128) 0x40ae30 B.NE	40ada4

(126) 0x40ae34 AND	W16, W4, #1951

(126) 0x40ae38 TBZ	W4, #0, 40ae58

(126) 0x40ae3c ADD	W4, W5, W16

(126) 0x40ae40 MOVZ	W5, #24

(126) 0x40ae44 SMADDL	X18, W4, W5, XZR

(126) 0x40ae48 ADD	X30, X8, X18

(126) 0x40ae4c STR	D31, [X8, X18]

(126) 0x40ae50 STP	D31, D31, [X30, #8]

(126) 0x40ae54 STR	D31, [X17, X4,SXTW #3]

(126) 0x40ae58 LDR	X21, [SP, #32]

(126) 0x40ae5c LDP	X19, X20, [SP, #16]

(126) 0x40ae60 LDP	X29, X30, [SP], #48

(126) 0x40ae64 RET

(126) 0x40ae68 ADD	W4, W4, #1

(126) 0x40ae6c MOVZ	W1, #0

(126) 0x40ae70 B	40ac74

(126) 0x40ae74 MOVZ	W20, #24

(126) 0x40ae78 SBFM	X21, X5, #0, #31

(126) 0x40ae7c ORN	W19, WZR, W5

(126) 0x40ae80 ADD	X1, X21, #1

(126) 0x40ae84 SMADDL	X8, W5, W20, X8

(126) 0x40ae88 ADD	W6, W3, W19

(126) 0x40ae8c AND	W2, W6, #128

(126) 0x40ae90 STP	XZR, XZR, [X8]

(126) 0x40ae94 ADD	X0, X8, #24

(126) 0x40ae98 STR	XZR, [X8, #16]

(126) 0x40ae9c STR	XZR, [X17, X21,LSL #3]

(126) 0x40aea0 CMP	W3, W1

(126) 0x40aea4 B.LE	40ae58

(126) 0x40aea8 CBZ	W2, 40af70

(126) 0x40aeac CMP	W2, #1

(126) 0x40aeb0 B.EQ	40af54

(126) 0x40aeb4 CMP	W2, #2

(126) 0x40aeb8 B.EQ	40af40

(126) 0x40aebc CMP	W2, #3

(126) 0x40aec0 B.EQ	40af2c

(126) 0x40aec4 CMP	W2, #4

(126) 0x40aec8 B.EQ	40af18

(126) 0x40aecc CMP	W2, #5

(126) 0x40aed0 B.EQ	40af04

(126) 0x40aed4 CMP	W2, #6

(126) 0x40aed8 B.EQ	40aef0

(126) 0x40aedc STP	XZR, XZR, [X0]

(126) 0x40aee0 STR	XZR, [X0, #16]

(126) 0x40aee4 ADD	X0, X8, #48

(126) 0x40aee8 STR	XZR, [X17, X1,LSL #3]

(126) 0x40aeec ADD	X1, X1, #1

(126) 0x40aef0 STP	XZR, XZR, [X0]

(126) 0x40aef4 ADD	X0, X0, #24

(126) 0x40aef8 STUR	XZR, [X0, #504]

(126) 0x40aefc STR	XZR, [X17, X1,LSL #3]

(126) 0x40af00 ADD	X1, X1, #1

(126) 0x40af04 STP	XZR, XZR, [X0]

(126) 0x40af08 ADD	X0, X0, #24

(126) 0x40af0c STUR	XZR, [X0, #504]

(126) 0x40af10 STR	XZR, [X17, X1,LSL #3]

(126) 0x40af14 ADD	X1, X1, #1

(126) 0x40af18 STP	XZR, XZR, [X0]

(126) 0x40af1c ADD	X0, X0, #24

(126) 0x40af20 STUR	XZR, [X0, #504]

(126) 0x40af24 STR	XZR, [X17, X1,LSL #3]

(126) 0x40af28 ADD	X1, X1, #1

(126) 0x40af2c STP	XZR, XZR, [X0]

(126) 0x40af30 ADD	X0, X0, #24

(126) 0x40af34 STUR	XZR, [X0, #504]

(126) 0x40af38 STR	XZR, [X17, X1,LSL #3]

(126) 0x40af3c ADD	X1, X1, #1

(126) 0x40af40 STP	XZR, XZR, [X0]

(126) 0x40af44 ADD	X0, X0, #24

(126) 0x40af48 STUR	XZR, [X0, #504]

(126) 0x40af4c STR	XZR, [X17, X1,LSL #3]

(126) 0x40af50 ADD	X1, X1, #1

(126) 0x40af54 STP	XZR, XZR, [X0]

(126) 0x40af58 ADD	X0, X0, #24

(126) 0x40af5c STUR	XZR, [X0, #504]

(126) 0x40af60 STR	XZR, [X17, X1,LSL #3]

(126) 0x40af64 ADD	X1, X1, #1

(126) 0x40af68 CMP	W3, W1

(126) 0x40af6c B.LE	40ae58

  (127) 0x40af70 STP	XZR, XZR, [X0]

  (127) 0x40af74 ADD	X7, X0, #24

  (127) 0x40af78 ADD	X4, X1, #1

  (127) 0x40af7c ADD	X16, X0, #48

  (127) 0x40af80 ADD	X15, X1, #2

  (127) 0x40af84 ADD	X14, X0, #72

  (127) 0x40af88 ADD	X13, X1, #3

  (127) 0x40af8c STR	XZR, [X0, #16]

  (127) 0x40af90 ADD	X12, X0, #96

  (127) 0x40af94 ADD	X11, X1, #4

  (127) 0x40af98 STR	XZR, [X17, X1,LSL #3]

  (127) 0x40af9c ADD	X10, X0, #120

  (127) 0x40afa0 ADD	X9, X1, #5

  (127) 0x40afa4 STR	XZR, [X0, #24]

  (127) 0x40afa8 ADD	X18, X0, #144

  (127) 0x40afac ADD	X30, X1, #6

  (127) 0x40afb0 STP	XZR, XZR, [X7, #8]

  (127) 0x40afb4 ADD	X20, X0, #168

  (127) 0x40afb8 ADD	X5, X1, #7

  (127) 0x40afbc ADD	X1, X1, #8

  (127) 0x40afc0 ADD	X0, X0, #192

  (127) 0x40afc4 STR	XZR, [X17, X4,LSL #3]

  (127) 0x40afc8 STUR	XZR, [X0, #368]

  (127) 0x40afcc STP	XZR, XZR, [X16, #8]

  (127) 0x40afd0 STR	XZR, [X17, X15,LSL #3]

  (127) 0x40afd4 STUR	XZR, [X0, #392]

  (127) 0x40afd8 STP	XZR, XZR, [X14, #8]

  (127) 0x40afdc STR	XZR, [X17, X13,LSL #3]

  (127) 0x40afe0 STUR	XZR, [X0, #416]

  (127) 0x40afe4 STP	XZR, XZR, [X12, #8]

  (127) 0x40afe8 STR	XZR, [X17, X11,LSL #3]

  (127) 0x40afec STUR	XZR, [X0, #440]

  (127) 0x40aff0 STP	XZR, XZR, [X10, #8]

  (127) 0x40aff4 STR	XZR, [X17, X9,LSL #3]

  (127) 0x40aff8 STUR	XZR, [X0, #464]

  (127) 0x40affc STP	XZR, XZR, [X18, #8]

  (127) 0x40b000 STR	XZR, [X17, X30,LSL #3]

  (127) 0x40b004 STUR	XZR, [X0, #488]

  (127) 0x40b008 STP	XZR, XZR, [X20, #8]

  (127) 0x40b00c STR	XZR, [X17, X5,LSL #3]

  (127) 0x40b010 CMP	W3, W1

  (127) 0x40b014 B.GT	40af70

(126) 0x40b018 B	40ae58

0x40b01c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.78+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.22+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	ljForce	ljForce.c:164	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161
/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 12.50 to 3.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 4 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.33	1.33	1.50	1.50	2.00	1.33	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.33	1.33	1.50	1.50	2.00	1.33	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40ac40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W4, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W4, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40ae68 <ljForce._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161
/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.50 to 1.00 cycles (12.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 4 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.33	1.33	1.50	1.50	2.00	1.33	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.33	1.33	1.50	1.50	2.00	1.33	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-12.50

Cycles summary

Front-end	1.63
Overall L1	5.00-12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

0% of peak load performance is reached (0.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40ac40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W21, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4025a0 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W19, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4026a0 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV W4, W21, W19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (25.0%)
MSUB W1, W4, W19, W21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W0, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 40ae68 <ljForce._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.0–	2.06	0.17
▼Loop 126 - ljForce.c:157-161 - exec–	0.00	0.00
○Loop 128 - ljForce.c:161-161 - exec	2.06	0.12
○Loop 127 - ljForce.c:161-161 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code