OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.27% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40a660 STP	X29, X30, [SP, #928]!

0x40a664 ADD	X29, SP, #0

0x40a668 STP	X21, X22, [SP, #32]

0x40a66c ORR	X21, XZR, X0

0x40a670 LDR	W2, [X0, #12]

0x40a674 STR	X27, [SP, #80]

0x40a678 ORR	X27, XZR, X1

0x40a67c LDR	W1, [X0, #20]

0x40a680 CMP	W2, W1

0x40a684 B.GE	40a6a8

0x40a688 SBFM	X0, X2, #0, #31

0x40a68c LDR	X2, [X21, #120]

(123) 0x40a690 STR	WZR, [X2, X0,LSL #2]

(123) 0x40a694 ADD	X0, X0, #1

(123) 0x40a698 LDR	W3, [X21, #20]

(123) 0x40a69c CMP	W3, W0

(123) 0x40a6a0 B.GT	40a690

0x40a6a4 LDR	W2, [X21, #12]

0x40a6a8 CMP	W2, #0

0x40a6ac B.LE	40a8d8

0x40a6b0 STP	X19, X20, [SP, #16]

0x40a6b4 STP	X23, X24, [SP, #48]

0x40a6b8 MOVZ	X23, #0

0x40a6bc STP	X25, X26, [SP, #64]

0x40a6c0 MOVZ	W26, #24

0x40a6c4 LDR	X5, [X21, #120]

      (119) 0x40a6c8 UBFM	X25, X23, #62, #31

      (119) 0x40a6cc ORR	W20, WZR, W23

      (119) 0x40a6d0 LDR	W4, [X5, X25]

      (119) 0x40a6d4 UBFM	W19, W23, #26, #25

      (119) 0x40a6d8 CMP	W4, #0

      (119) 0x40a6dc B.LE	40a8c0

    (120) 0x40a6e0 LDR	D29, [X21, #64]

    (120) 0x40a6e4 MOVZ	W22, #0

    (120) 0x40a6e8 ORR	W24, WZR, W19

    (120) 0x40a6ec LDP	D31, D30, [X21, #48]

    (120) 0x40a6f0 LDR	X3, [X27, #24]

    (120) 0x40a6f4 LDP	W2, W0, [X21]

    (120) 0x40a6f8 LDR	W1, [X21, #8]

    (120) 0x40a6fc HINT	#0

    (120) 0x40a700 UMADDL	X6, W24, W26, XZR

    (120) 0x40a704 LDR	D4, [X3, X6]

    (120) 0x40a708 ADD	X7, X3, X6

    (120) 0x40a70c LDP	D27, D26, [X7, #8]

    (120) 0x40a710 FCMPE	D4, D31

    (120) 0x40a714 B.MI	40a848

    (120) 0x40a718 ORR	W9, WZR, W2

    (120) 0x40a71c FCMPE	D27, D30

    (120) 0x40a720 B.MI	40a824

    (120) 0x40a724 ORR	W12, WZR, W0

    (120) 0x40a728 FCMPE	D26, D29

    (120) 0x40a72c B.MI	40a7cc

    (120) 0x40a730 LDR	W4, [X21, #12]

    (120) 0x40a734 ADD	W15, W2, #2

    (120) 0x40a738 MADD	W14, W1, W0, WZR

    (120) 0x40a73c ADD	W16, W0, #2

    (120) 0x40a740 ADD	W17, W9, #1

    (120) 0x40a744 MADD	W18, W15, W1, WZR

    (120) 0x40a748 MADD	W30, W12, W15, W15

    (120) 0x40a74c ADD	W6, W4, W14,LSL #1

    (120) 0x40a750 ADD	W7, W6, W18,LSL #1

    (120) 0x40a754 MADD	W9, W16, W15, W7

    (120) 0x40a758 ADD	W8, W9, W30

    (120) 0x40a75c ADD	W4, W8, W17

    (120) 0x40a760 TBNZ	W4, #31, 40a92c

    (120) 0x40a764 LDR	W12, [X21, #20]

    (120) 0x40a768 CMP	W4, W12

    (120) 0x40a76c B.GE	40a94c

    (120) 0x40a770 CMP	W4, W23

    (120) 0x40a774 B.EQ	40a7b4

    (120) 0x40a778 ORR	X1, XZR, X27

    (120) 0x40a77c ORR	W3, WZR, W20

    (120) 0x40a780 ORR	W2, WZR, W22

    (120) 0x40a784 ORR	X0, XZR, X21

    (120) 0x40a788 BL	40a4c4

    (120) 0x40a78c LDR	X5, [X21, #120]

    (120) 0x40a790 LDR	W1, [X5, X25]

    (120) 0x40a794 CMP	W22, W1

    (120) 0x40a798 B.GE	40a8bc

    (120) 0x40a79c LDR	X3, [X27, #24]

    (120) 0x40a7a0 LDR	D29, [X21, #64]

    (120) 0x40a7a4 LDP	D31, D30, [X21, #48]

    (120) 0x40a7a8 LDP	W2, W0, [X21]

    (120) 0x40a7ac LDR	W1, [X21, #8]

    (120) 0x40a7b0 B	40a700

    (120) 0x40a7b4 LDR	W14, [X5, X25]

    (120) 0x40a7b8 ADD	W22, W22, #1

    (120) 0x40a7bc CMP	W14, W22

    (120) 0x40a7c0 B.LE	40a8bc

    (120) 0x40a7c4 ADD	W24, W19, W22

    (120) 0x40a7c8 B	40a700

    (120) 0x40a7cc LDR	D25, [X21, #40]

    (120) 0x40a7d0 LDR	D28, [X21, #112]

    (120) 0x40a7d4 FSUB	D17, D26, S25

    (120) 0x40a7d8 FMUL	D18, D17, D28

    (120) 0x40a7dc FCVTMS	W10, D18

    (120) 0x40a7e0 CMP	W10, W1

    (120) 0x40a7e4 CSINC	W11, WZR, WZR, #1

    (120) 0x40a7e8 SUB	W13, W10, W11

    (120) 0x40a7ec CMN	W13, #1

    (120) 0x40a7f0 B.EQ	40a86c

    (120) 0x40a7f4 CMP	W12, W0

    (120) 0x40a7f8 B.EQ	40a898

    (120) 0x40a7fc CMN	W12, #1

    (120) 0x40a800 B.EQ	40a8e8

    (120) 0x40a804 CMP	W9, W2

    (120) 0x40a808 B.EQ	40a908

    (120) 0x40a80c CMN	W9, #1

    (120) 0x40a810 B.EQ	40a91c

    (120) 0x40a814 MADD	W12, W12, W2, W9

    (120) 0x40a818 MADD	W14, W0, W2, WZR

    (120) 0x40a81c MADD	W4, W14, W13, W12

    (120) 0x40a820 B	40a760

    (120) 0x40a824 LDR	D5, [X21, #32]

    (120) 0x40a828 LDR	D6, [X21, #104]

    (120) 0x40a82c FSUB	D7, D27, S5

    (120) 0x40a830 FMUL	D16, D7, D6

    (120) 0x40a834 FCVTMS	W11, D16

    (120) 0x40a838 CMP	W11, W0

    (120) 0x40a83c CSINC	W13, WZR, WZR, #1

    (120) 0x40a840 SUB	W12, W11, W13

    (120) 0x40a844 B	40a728

    (120) 0x40a848 LDR	D3, [X21, #24]

    (120) 0x40a84c LDR	D2, [X21, #96]

    (120) 0x40a850 FSUB	D0, D4, S3

    (120) 0x40a854 FMUL	D1, D0, D2

    (120) 0x40a858 FCVTMS	W8, D1

    (120) 0x40a85c CMP	W8, W2

    (120) 0x40a860 CSINC	W10, WZR, WZR, #1

    (120) 0x40a864 SUB	W9, W8, W10

    (120) 0x40a868 B	40a71c

    (120) 0x40a86c ADD	W6, W9, #1

    (120) 0x40a870 LDR	W9, [X21, #12]

    (120) 0x40a874 ADD	W30, W2, #2

    (120) 0x40a878 MADD	W18, W1, W0, WZR

    (120) 0x40a87c MADD	W4, W30, W1, WZR

    (120) 0x40a880 MADD	W7, W12, W30, W30

    (120) 0x40a884 ADD	W8, W9, W18,LSL #1

    (120) 0x40a888 ADD	W10, W8, W4,LSL #1

    (120) 0x40a88c ADD	W11, W10, W7

    (120) 0x40a890 ADD	W4, W11, W6

    (120) 0x40a894 B	40a760

    (120) 0x40a898 LDR	W15, [X21, #12]

    (120) 0x40a89c MADD	W11, W1, W0, WZR

    (120) 0x40a8a0 ADD	W12, W2, #2

    (120) 0x40a8a4 ADD	W14, W9, #1

    (120) 0x40a8a8 ADD	W16, W15, W11,LSL #1

    (120) 0x40a8ac MADD	W17, W12, W1, W16

    (120) 0x40a8b0 MADD	W13, W13, W12, W17

    (120) 0x40a8b4 ADD	W4, W13, W14

    (120) 0x40a8b8 B	40a760

    (120) 0x40a8bc LDR	W2, [X21, #12]

      (119) 0x40a8c0 ADD	X23, X23, #1

      (119) 0x40a8c4 CMP	W2, W23

      (119) 0x40a8c8 B.GT	40a6c8

(122) 0x40a8cc LDP	X19, X20, [SP, #16]

(122) 0x40a8d0 LDP	X23, X24, [SP, #48]

(122) 0x40a8d4 LDP	X25, X26, [SP, #64]

(122) 0x40a8d8 LDP	X21, X22, [SP, #32]

(122) 0x40a8dc LDR	X27, [SP, #80]

(122) 0x40a8e0 LDP	X29, X30, [SP], #96

(122) 0x40a8e4 RET

  (121) 0x40a8e8 ADD	W6, W9, #1

  (121) 0x40a8ec LDR	W9, [X21, #12]

  (121) 0x40a8f0 MADD	W7, W1, W0, WZR

  (121) 0x40a8f4 ADD	W4, W2, #2

  (121) 0x40a8f8 ADD	W8, W9, W7,LSL #1

  (121) 0x40a8fc MADD	W10, W4, W13, W8

  (121) 0x40a900 ADD	W4, W10, W6

  (121) 0x40a904 B	40a760

    (120) 0x40a908 LDR	W17, [X21, #12]

    (120) 0x40a90c MADD	W18, W1, W0, W17

    (120) 0x40a910 MADD	W30, W13, W0, W18

    (120) 0x40a914 ADD	W4, W30, W12

    (120) 0x40a918 B	40a760

    (120) 0x40a91c LDR	W15, [X21, #12]

    (120) 0x40a920 MADD	W16, W13, W0, W15

    (120) 0x40a924 ADD	W4, W16, W12

    (120) 0x40a928 B	40a760

0x40a92c ADRP	X5,

0x40a930 ADRP	X22,

0x40a934 ADRP	X23,

0x40a938 ADD	X3, X5, #1136

0x40a93c ADD	X1, X22, #832

0x40a940 ADD	X0, X23, #928

0x40a944 MOVZ	W2, #246

0x40a948 BL	402730

0x40a94c ADRP	X24,

0x40a950 ADRP	X21,

0x40a954 ADRP	X27,

0x40a958 ADD	X3, X24, #1136

0x40a95c ADD	X1, X21, #832

0x40a960 ADD	X0, X27, #944

0x40a964 MOVZ	W2, #247

0x40a968 BL	402730

Coverage (%)	Name	Source Location	Module
►99.05+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.63 to 3.41 cycles (1.36x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.63 to 1.00 cycles (4.62x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	4.17	4.17	4.17	4.17	4.17	4.17	0.00	0.00	0.00	0.00	3.67	3.67	3.67	3.00	3.00
cycles	2.00	2.00	4.17	4.17	4.17	4.17	4.17	4.17	0.00	0.00	0.00	0.00	3.67	3.67	3.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	4.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.63 cycles. At this rate:

6% of peak load performance is reached (6.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W2, [X0, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W1, [X0, #20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W2, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a6a8 <updateLinkCells+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X0, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X2, [X21, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W2, [X21, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40a8d8 <updateLinkCells+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X23, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W26, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X5, [X21, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADRP X5, <41092c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X22, <40f930>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X23, <40f934>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X3, X5, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X22, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X23, #928	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #246	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X24, <41094c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X21, <40f950>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADRP X27, <40f954>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X24, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X21, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X27, #944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #247	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.63 to 1.00 cycles (4.62x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	4.17	4.17	4.17	4.17	4.17	4.17	0.00	0.00	0.00	0.00	3.67	3.67	3.67	3.00	3.00
cycles	2.00	2.00	4.17	4.17	4.17	4.17	4.17	4.17	0.00	0.00	0.00	0.00	3.67	3.67	3.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	4.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.63 cycles. At this rate:

6% of peak load performance is reached (6.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W2, [X0, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W1, [X0, #20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W2, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 40a6a8 <updateLinkCells+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X0, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X2, [X21, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W2, [X21, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 40a8d8 <updateLinkCells+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X23, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W26, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X5, [X21, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADRP X5, <41092c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X22, <40f930>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X23, <40f934>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X3, X5, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X22, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X23, #928	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #246	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X24, <41094c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X21, <40f950>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADRP X27, <40f954>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X24, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X21, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X27, #944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #247	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.27	0.02
▼Loop 122 - linkCells.c:211-385 - exec–	0.00	0.00
▼Loop 121 - linkCells.c:211-385 - exec–	0.00	0.00
▼Loop 120 - linkCells.c:211-385 - exec–	0.27	1.56
○Loop 119 - linkCells.c:291-385 - exec	0.00	0.01
○Loop 123 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code