OV - exec - Function moveAtom

	Function: moveAtom	Module: exec	Source: linkCells.c:257-335 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 257 - 335

--------------------------------------------------------------------------------

257: {

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

270:

271:    return;

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

335: }

0x40a4c4 LDR	X5, [X0, #120]

0x40a4c8 SBFM	X8, X4, #62, #31

0x40a4cc UBFM	W13, W3, #26, #25

0x40a4d0 LDP	X11, X15, [X1, #8]

0x40a4d4 ADD	W2, W2, W13

0x40a4d8 MOVZ	W7, #24

0x40a4dc SBFM	X10, X2, #62, #31

0x40a4e0 SBFM	X12, X2, #61, #31

0x40a4e4 SMADDL	X17, W2, W7, XZR

0x40a4e8 LDR	W6, [X5, X8]

0x40a4ec LDR	W16, [X11, X10]

0x40a4f0 LDR	X2, [X1, #24]

0x40a4f4 ADD	W18, W6, W4,LSL #6

0x40a4f8 SBFM	X14, X18, #62, #31

0x40a4fc SMADDL	X9, W18, W7, XZR

0x40a500 STR	W16, [X11, X14]

0x40a504 ADD	X11, X2, X17

0x40a508 LDR	W16, [X15, X10]

0x40a50c ADD	X5, X2, X9

0x40a510 STR	W16, [X15, X14]

0x40a514 LDP	X14, X15, [X11]

0x40a518 LDR	X6, [X11, #16]

0x40a51c STP	X14, X15, [X5]

0x40a520 STR	X6, [X5, #16]

0x40a524 LDR	X15, [X1, #32]

0x40a528 ADD	X2, X15, X17

0x40a52c ADD	X16, X15, X9

0x40a530 LDP	X14, X15, [X2]

0x40a534 LDR	X11, [X2, #16]

0x40a538 STP	X14, X15, [X16]

0x40a53c STR	X11, [X16, #16]

0x40a540 LDR	X5, [X1, #40]

0x40a544 ADD	X6, X5, X17

0x40a548 ADD	X2, X5, X9

0x40a54c LDP	X14, X15, [X6]

0x40a550 LDR	X9, [X6, #16]

0x40a554 STP	X14, X15, [X2]

0x40a558 STR	X9, [X2, #16]

0x40a55c LDR	X15, [X1, #48]

0x40a560 LDR	X16, [X15, X12]

0x40a564 STR	X16, [X15, X18,SXTW #3]

0x40a568 LDR	X18, [X0, #120]

0x40a56c LDR	W11, [X18, X8]

0x40a570 ADD	W5, W11, #1

0x40a574 STR	W5, [X18, X8]

0x40a578 CMP	W5, #63

0x40a57c B.GT	40a634

0x40a580 SBFM	X8, X3, #62, #31

0x40a584 LDR	W6, [X18, X8]

0x40a588 SUB	W2, W6, #1

0x40a58c STR	W2, [X18, X8]

0x40a590 CBNZ	W2, 40a5b0

(118) 0x40a594 LDR	W12, [X0, #12]

(118) 0x40a598 CMP	W12, W4

(118) 0x40a59c B.GE	40a5ac

(118) 0x40a5a0 LDR	W4, [X1]

(118) 0x40a5a4 SUB	W0, W4, #1

(118) 0x40a5a8 STR	W0, [X1]

(118) 0x40a5ac RET

(118) 0x40a5b0 LDP	X15, X16, [X1, #8]

(118) 0x40a5b4 ADD	W14, W2, W13

(118) 0x40a5b8 SBFM	X9, X14, #62, #31

(118) 0x40a5bc SMADDL	X18, W14, W7, XZR

(118) 0x40a5c0 LDR	X11, [X1, #24]

(118) 0x40a5c4 LDR	W13, [X15, X9]

(118) 0x40a5c8 ADD	X7, X11, X18

(118) 0x40a5cc ADD	X5, X11, X17

(118) 0x40a5d0 STR	W13, [X15, X10]

(118) 0x40a5d4 LDR	W3, [X16, X9]

(118) 0x40a5d8 STR	W3, [X16, X10]

(118) 0x40a5dc LDP	X10, X11, [X7]

(118) 0x40a5e0 LDR	X8, [X7, #16]

(118) 0x40a5e4 STP	X10, X11, [X5]

(118) 0x40a5e8 STR	X8, [X5, #16]

(118) 0x40a5ec LDR	X6, [X1, #32]

(118) 0x40a5f0 ADD	X2, X6, X18

(118) 0x40a5f4 ADD	X15, X6, X17

(118) 0x40a5f8 LDP	X10, X11, [X2]

(118) 0x40a5fc LDR	X9, [X2, #16]

(118) 0x40a600 STP	X10, X11, [X15]

(118) 0x40a604 STR	X9, [X15, #16]

(118) 0x40a608 LDR	X16, [X1, #40]

(118) 0x40a60c ADD	X18, X16, X18

(118) 0x40a610 ADD	X17, X16, X17

(118) 0x40a614 LDP	X8, X9, [X18]

(118) 0x40a618 LDR	X13, [X18, #16]

(118) 0x40a61c STP	X8, X9, [X17]

(118) 0x40a620 STR	X13, [X17, #16]

(118) 0x40a624 LDR	X11, [X1, #48]

(118) 0x40a628 LDR	X14, [X11, X14,SXTW #3]

(118) 0x40a62c STR	X14, [X11, X12]

(118) 0x40a630 B	40a594

0x40a634 ADRP	X3,

0x40a638 ADRP	X1,

0x40a63c STP	X29, X30, [SP, #1008]!

0x40a640 ADD	X4, X3, #1136

0x40a644 ADRP	X0,

0x40a648 ADD	X29, SP, #0

0x40a64c ADD	X3, X4, #32

0x40a650 ADD	X1, X1, #832

0x40a654 ADD	X0, X0, #1064

0x40a658 MOVZ	W2, #262

0x40a65c BL	402730

Coverage (%)	Name	Source Location	Module
►100.00+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	linkCells.c:257-335
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-271,327-335.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 10.33 to 8.50 cycles (1.22x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.33 to 0.50 cycles (20.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	63
loop length	252
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	10.33	10.33	10.33	6.00	6.00
cycles	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	10.33	10.33	10.33	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.88
Overall L1	10.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.33 cycles. At this rate:

16% of peak load performance is reached (15.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a4c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X5, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X4, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM W13, W3, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X11, X15, [X1, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD W2, W2, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X10, X2, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X12, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SMADDL X17, W2, W7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR W6, [X5, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W16, [X11, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X1, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W18, W6, W4,LSL #6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
SBFM X14, X18, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SMADDL X9, W18, W7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W16, [X11, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X2, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W16, [X15, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X2, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W16, [X15, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X15, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X6, [X11, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X15, [X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X6, [X5, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X1, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X15, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X16, X15, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP X14, X15, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X2, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X15, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [X16, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X1, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X5, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X2, X5, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP X14, X15, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X6, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X14, X15, [X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X9, [X2, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X1, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X15, X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X15, X18,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X18, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W5, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W5, [X18, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W5, #63	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40a634 <moveAtom+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X8, X3, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W6, [X18, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W2, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W2, [X18, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ W2, 40a5b0 <moveAtom+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <410634>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X1, <40f638>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #1008]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X4, X3, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <40f644>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X4, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X1, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #1064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #262	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	linkCells.c:257-335
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-271,327-335.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.33 to 0.50 cycles (20.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	63
loop length	252
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	10.33	10.33	10.33	6.00	6.00
cycles	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	10.33	10.33	10.33	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.88
Overall L1	10.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.33 cycles. At this rate:

16% of peak load performance is reached (15.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a4c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X5, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X4, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM W13, W3, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X11, X15, [X1, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD W2, W2, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X10, X2, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SBFM X12, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SMADDL X17, W2, W7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR W6, [X5, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W16, [X11, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X1, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W18, W6, W4,LSL #6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
SBFM X14, X18, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SMADDL X9, W18, W7, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR W16, [X11, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X11, X2, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W16, [X15, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X2, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W16, [X15, X14]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X14, X15, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X6, [X11, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X15, [X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X6, [X5, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X1, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X15, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X16, X15, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP X14, X15, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X2, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X14, X15, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [X16, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X1, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X5, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X2, X5, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP X14, X15, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X6, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X14, X15, [X2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X9, [X2, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X1, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X15, X12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X16, [X15, X18,SXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W11, [X18, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W5, W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W5, [X18, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W5, #63	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 40a634 <moveAtom+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X8, X3, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR W6, [X18, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W2, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR W2, [X18, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CBNZ W2, 40a5b0 <moveAtom+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <410634>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X1, <40f638>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #1008]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X4, X3, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X0, <40f644>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X4, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X1, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, X0, #1064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #262	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼moveAtom–	0.01	0.00
○Loop 118 - linkCells.c:268-335 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code