OV - exec - Function getBoxFromTuple

	Function: getBoxFromTuple	Module: exec	Source: linkCells.c:204-250	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 204 - 250

--------------------------------------------------------------------------------

204: {

205:    int iBox = 0;

206:    const int* gridSize = boxes->gridSize; // alias

207:

208:    // Halo in Z+

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

248:

249:    return iBox;

250: }

0x40a1e0 STP	X29, X30, [SP, #1008]!

0x40a1e4 ORR	X5, XZR, X0

0x40a1e8 ADD	X29, SP, #0

0x40a1ec LDP	W6, W4, [X0]

0x40a1f0 LDR	W0, [X0, #8]

0x40a1f4 CMP	W0, W3

0x40a1f8 B.EQ	40a274

0x40a1fc CMN	W3, #1

0x40a200 B.EQ	40a248

0x40a204 CMP	W2, W4

0x40a208 B.EQ	40a2c8

0x40a20c CMN	W2, #1

0x40a210 B.EQ	40a2a8

0x40a214 CMP	W1, W6

0x40a218 B.EQ	40a2ec

0x40a21c CMN	W1, #1

0x40a220 B.EQ	40a300

0x40a224 MADD	W2, W2, W6, W1

0x40a228 MADD	W1, W4, W6, WZR

0x40a22c MADD	W0, W1, W3, W2

(116) 0x40a230 TBNZ	W0, #31, 40a310

(116) 0x40a234 LDR	W1, [X5, #20]

(116) 0x40a238 CMP	W1, W0

(116) 0x40a23c B.LE	40a330

(116) 0x40a240 LDP	X29, X30, [SP], #16

(116) 0x40a244 RET

(116) 0x40a248 LDR	W3, [X5, #12]

(116) 0x40a24c MADD	W8, W0, W4, WZR

(116) 0x40a250 ADD	W7, W6, #2

(116) 0x40a254 ADD	W1, W1, #1

(116) 0x40a258 MADD	W9, W0, W7, WZR

(116) 0x40a25c MADD	W10, W2, W7, W7

(116) 0x40a260 ADD	W11, W3, W8,LSL #1

(116) 0x40a264 ADD	W12, W11, W9,LSL #1

(116) 0x40a268 ADD	W13, W12, W10

(116) 0x40a26c ADD	W0, W13, W1

(116) 0x40a270 B	40a230

0x40a274 ADD	W14, W6, #2

0x40a278 LDR	W6, [X5, #12]

0x40a27c MADD	W15, W0, W4, WZR

0x40a280 ADD	W16, W4, #2

0x40a284 ADD	W17, W1, #1

0x40a288 MADD	W18, W14, W0, WZR

0x40a28c MADD	W30, W2, W14, W14

0x40a290 ADD	W4, W6, W15,LSL #1

0x40a294 ADD	W0, W4, W18,LSL #1

0x40a298 MADD	W2, W16, W14, W0

0x40a29c ADD	W7, W2, W30

0x40a2a0 ADD	W0, W7, W17

0x40a2a4 B	40a230

0x40a2a8 LDR	W14, [X5, #12]

0x40a2ac MADD	W11, W0, W4, WZR

0x40a2b0 ADD	W12, W6, #2

0x40a2b4 ADD	W13, W1, #1

0x40a2b8 ADD	W15, W14, W11,LSL #1

0x40a2bc MADD	W16, W12, W3, W15

0x40a2c0 ADD	W0, W16, W13

0x40a2c4 B	40a230

0x40a2c8 ADD	W18, W6, #2

0x40a2cc LDR	W6, [X5, #12]

0x40a2d0 MADD	W17, W0, W2, WZR

0x40a2d4 ADD	W30, W1, #1

0x40a2d8 ADD	W4, W6, W17,LSL #1

0x40a2dc MADD	W0, W0, W18, W4

0x40a2e0 MADD	W2, W18, W3, W0

0x40a2e4 ADD	W0, W2, W30

0x40a2e8 B	40a230

0x40a2ec LDR	W8, [X5, #12]

0x40a2f0 MADD	W9, W0, W4, W8

0x40a2f4 MADD	W10, W3, W4, W9

0x40a2f8 ADD	W0, W10, W2

0x40a2fc B	40a230

0x40a300 LDR	W7, [X5, #12]

0x40a304 MADD	W3, W3, W4, W7

0x40a308 ADD	W0, W3, W2

0x40a30c B	40a230

0x40a310 ADRP	X5,

0x40a314 ADRP	X8,

0x40a318 ADRP	X9,

0x40a31c ADD	X3, X5, #1136

0x40a320 ADD	X1, X8, #832

0x40a324 ADD	X0, X9, #928

0x40a328 MOVZ	W2, #246

0x40a32c BL	402730

0x40a330 ADRP	X10,

0x40a334 ADRP	X11,

0x40a338 ADRP	X12,

0x40a33c ADD	X3, X10, #1136

0x40a340 ADD	X1, X11, #832

0x40a344 ADD	X0, X12, #944

0x40a348 MOVZ	W2, #247

0x40a34c BL	402730

Coverage (%)	Name	Source Location	Module
►61.54+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec
►15.38+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:424	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec
►15.38+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:424	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec
►7.69+	putAtomInBox	linkCells.c:179	exec
○	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	linkCells.c:204-250
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:204-250.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 31% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 6.50 cycles (2.31x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 1.00 cycles (15.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	8.42	8.42	8.50	8.33	15.00	8.33	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50
cycles	6.50	6.50	8.42	8.42	8.50	8.33	15.00	8.33	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (2.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.07 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a1e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #1008]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X5, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDP W6, W4, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W0, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a274 <getBoxFromTuple+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W3, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a248 <getBoxFromTuple+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W2, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a2c8 <getBoxFromTuple+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W2, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a2a8 <getBoxFromTuple+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, W6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a2ec <getBoxFromTuple+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a300 <getBoxFromTuple+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W2, W6, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W1, W4, W6, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W0, W1, W3, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD W14, W6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W15, W0, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W16, W4, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W17, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W14, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W30, W2, W14, W14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W4, W6, W15,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W4, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W2, W16, W14, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W7, W2, W30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W7, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W14, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W11, W0, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W12, W6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W13, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W15, W14, W11,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W16, W12, W3, W15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W16, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W17, W0, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W6, W17,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W0, W0, W18, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD W2, W18, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W2, W30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W9, W0, W4, W8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W10, W3, W4, W9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W10, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W3, W3, W4, W7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <410310>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADRP X8, <40f314>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X9, <40f318>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X3, X5, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X8, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X9, #928	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #246	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X10, <410330>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X11, <40f334>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X12, <40f338>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X10, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X11, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X12, #944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #247	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	linkCells.c:204-250
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:204-250.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 15.00 to 1.00 cycles (15.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	8.42	8.42	8.50	8.33	15.00	8.33	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50
cycles	6.50	6.50	8.42	8.42	8.50	8.33	15.00	8.33	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.38
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

2% of peak load performance is reached (2.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.07 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40a1e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #1008]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X5, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDP W6, W4, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W0, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a274 <getBoxFromTuple+0x94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W3, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a248 <getBoxFromTuple+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W2, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a2c8 <getBoxFromTuple+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W2, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a2a8 <getBoxFromTuple+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, W6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a2ec <getBoxFromTuple+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN W1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 40a300 <getBoxFromTuple+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W2, W6, W1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W1, W4, W6, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W0, W1, W3, W2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD W14, W6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W15, W0, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W16, W4, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W17, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W18, W14, W0, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W30, W2, W14, W14	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W4, W6, W15,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W4, W18,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MADD W2, W16, W14, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W7, W2, W30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W0, W7, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W14, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W11, W0, W4, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W12, W6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD W13, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W15, W14, W11,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W16, W12, W3, W15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W16, W13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W18, W6, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W6, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W17, W0, W2, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W30, W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W6, W17,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
MADD W0, W0, W18, W4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD W2, W18, W3, W0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W2, W30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W9, W0, W4, W8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
MADD W10, W3, W4, W9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W10, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W7, [X5, #12]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W3, W3, W4, W7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD W0, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 40a230 <getBoxFromTuple+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <410310>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADRP X8, <40f314>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X9, <40f318>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X3, X5, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X8, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X9, #928	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #246	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X10, <410330>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X11, <40f334>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X12, <40f338>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X3, X10, #1136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X11, #832	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X12, #944	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #247	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
BL 402730 <@plt_start@+0x1c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼getBoxFromTuple–	0.01	0.00
○Loop 116 - linkCells.c:217-250 - exec	0.01	0.03

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code