OV - exec - Function sortAtomsInCell

	Function: sortAtomsInCell	Module: exec	Source: haloExchange.c:614-645	Coverage (incl. loops): 1.43% \| (excl. loops): 0.22%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 614 - 645

--------------------------------------------------------------------------------

614: {

615:    int nAtoms = boxes->nAtoms[iBox];

616:

617:    AtomMsg tmp[nAtoms];

618:

619:    int begin = iBox*MAXATOMS;

620:    int end = begin + nAtoms;

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

630:       tmp[iTmp].pz =   atoms->p[ii][2];

631:    }

632:    qsort(&tmp, nAtoms, sizeof(AtomMsg), sortAtomsById);

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

643:    }

644:

645: }

0x407c64 STP	X29, X30, [SP, #928]!

0x407c68 ADD	X29, SP, #0

0x407c6c SBFM	X11, X2, #0, #31

0x407c70 MOVZ	W5, #56

0x407c74 UBFM	W2, W11, #26, #25

0x407c78 STP	X19, X20, [SP, #16]

0x407c7c STP	X21, X22, [SP, #32]

0x407c80 ORR	X21, XZR, X0

0x407c84 STP	X23, X24, [SP, #48]

0x407c88 STP	X25, X26, [SP, #64]

0x407c8c LDR	X1, [X1, #120]

0x407c90 LDR	W0, [X1, X11,SXTW #2]

0x407c94 STR	X27, [SP, #80]

0x407c98 SMADDL	X3, W0, W5, XZR

0x407c9c ADD	W20, W0, W2

0x407ca0 SBFM	X1, X0, #0, #31

0x407ca4 ADD	X4, X3, #15

0x407ca8 AND	X6, X4, #7932

0x407cac SUB	SP, SP, X6,UXTX

0x407cb0 ADD	X19, SP, #0

0x407cb4 CMP	W2, W20

0x407cb8 B.GE	4082cc

0x407cbc LDP	X30, X18, [X21, #8]

0x407cc0 ORR	X22, XZR, X11

0x407cc4 ORR	W8, WZR, W0

0x407cc8 LDP	X24, X23, [X21, #24]

0x407ccc CMP	W0, #1

0x407cd0 B.EQ	408148

0x407cd4 ORR	W9, WZR, W0

0x407cd8 MOVZ	W10, #24

0x407cdc MOVZ	W25, #1536

0x407ce0 ADD	X3, SP, #8

0x407ce4 UMADDL	X13, W9, W10, XZR

0x407ce8 UBFM	X26, X11, #58, #57

0x407cec UBFM	X14, X11, #56, #55

0x407cf0 SMADDL	X25, W11, W25, XZR

0x407cf4 ADD	X15, X26, X9

0x407cf8 ADD	X12, X30, X14

0x407cfc UMADDL	X16, W9, W5, XZR

0x407d00 ADD	X11, X18, X14

0x407d04 ADD	X17, X30, X15,LSL #2

0x407d08 ADD	X27, X13, X25

0x407d0c ADD	X5, X24, X25

0x407d10 ADD	X13, X18, X15,LSL #2

0x407d14 ADD	X4, X24, X27

0x407d18 ADD	X10, SP, X16,UXTX

0x407d1c CMP	X4, X3

0x407d20 ADD	X7, X23, X27

0x407d24 CCMP	X10, X5, #0, #8

0x407d28 ADD	X4, X23, X25

0x407d2c CSINC	W9, WZR, WZR, #8

0x407d30 CMP	X3, X7

0x407d34 SUB	X6, X16, #48

0x407d38 CCMP	X10, X4, #0, #3

0x407d3c ADD	X14, SP, X6,UXTX

0x407d40 CSINC	W15, WZR, WZR, #8

0x407d44 CMP	SP, X17,UXTX

0x407d48 AND	W16, W9, W15

0x407d4c CCMP	X14, X12, #0, #3

0x407d50 CSINC	W17, WZR, WZR, #8

0x407d54 CMP	SP, X13,UXTX

0x407d58 CCMP	X14, X11, #0, #3

0x407d5c CSINC	W27, WZR, WZR, #8

0x407d60 AND	W13, W17, W27

0x407d64 ANDS	WZR, W16, W13

0x407d68 B.EQ	408148

0x407d6c SUB	W10, W0, #1

0x407d70 CMP	W10, #2

0x407d74 B.LS	408300

0x407d78 UBFM	W8, W0, #2, #31

0x407d7c MOVZ	X6, #0

0x407d80 UBFM	X17, X8, #60, #59

(84) 0x407d84 ORR	X15, XZR, X5

(84) 0x407d88 LDR	D24, [X5, #16]

(84) 0x407d8c ADD	X10, X11, X6

(84) 0x407d90 ADD	X9, X12, X6

(84) 0x407d94 ORR	X7, XZR, X4

(84) 0x407d98 LDR	Q23, [X15], #16

(84) 0x407d9c ADD	X3, X3, #224

(84) 0x407da0 LDR	Q28, [X5, #48]

(84) 0x407da4 LDP	D25, D27, [X5, #32]

(84) 0x407da8 LDR	D26, [X15, #8]

(84) 0x407dac LDP	D29, D31, [X5, #64]

(84) 0x407db0 LDP	D30, D22, [X5, #80]

(84) 0x407db4 ADD	X5, X5, #96

(84) 0x407db8 LDR	W27, [X12, X6]

(84) 0x407dbc LDR	W16, [X11, X6]

(84) 0x407dc0 ADD	X6, X6, #16

(84) 0x407dc4 LDP	W14, W13, [X10, #4]

(84) 0x407dc8 LDR	W8, [X10, #12]

(84) 0x407dcc LDP	W15, W10, [X9, #4]

(84) 0x407dd0 LDR	W9, [X9, #12]

(84) 0x407dd4 STP	W27, W16, [X3, #280]

(84) 0x407dd8 STUR	Q23, [X3, #288]

(84) 0x407ddc STUR	D24, [X3, #304]

(84) 0x407de0 STP	W15, W14, [X3, #336]

(84) 0x407de4 STP	D26, D25, [X3, #856]

(84) 0x407de8 STUR	D27, [X3, #360]

(84) 0x407dec STP	W10, W13, [X3, #392]

(84) 0x407df0 STUR	Q28, [X3, #400]

(84) 0x407df4 STUR	D29, [X3, #416]

(84) 0x407df8 STP	W9, W8, [X3, #448]

(84) 0x407dfc STP	D31, D30, [X3, #968]

(84) 0x407e00 STUR	D22, [X3, #472]

(84) 0x407e04 LDR	Q0, [X7], #16

(84) 0x407e08 LDP	D1, D2, [X4, #32]

(84) 0x407e0c LDR	D7, [X4, #16]

(84) 0x407e10 LDR	D17, [X7, #8]

(84) 0x407e14 LDR	Q16, [X4, #48]

(84) 0x407e18 LDP	D3, D4, [X4, #64]

(84) 0x407e1c LDP	D5, D6, [X4, #80]

(84) 0x407e20 ADD	X4, X4, #96

(84) 0x407e24 STUR	Q0, [X3, #312]

(84) 0x407e28 STUR	D7, [X3, #328]

(84) 0x407e2c STP	D17, D1, [X3, #880]

(84) 0x407e30 STUR	D2, [X3, #384]

(84) 0x407e34 STUR	Q16, [X3, #424]

(84) 0x407e38 STUR	D3, [X3, #440]

(84) 0x407e3c STP	D4, D5, [X3, #992]

(84) 0x407e40 STUR	D6, [X3, #496]

(84) 0x407e44 CMP	X17, X6

(84) 0x407e48 B.NE	407d84

0x407e4c AND	W4, W0, #1886

0x407e50 SBFM	X27, X2, #0, #31

0x407e54 ORR	W3, WZR, W4

0x407e58 CMP	W0, W4

0x407e5c B.EQ	407f88

0x407e60 SUB	W8, W0, W4

0x407e64 ADD	W7, W2, W4

0x407e68 CMP	W8, #1

0x407e6c B.EQ	407f18

0x407e70 MOVZ	W12, #24

0x407e74 ADD	X26, X26, W3,UXTW

0x407e78 UBFM	X11, X26, #62, #61

0x407e7c ADD	X17, X30, X26,LSL #2

0x407e80 LDR	W14, [X30, X11]

0x407e84 MOVZ	W0, #56

0x407e88 ADD	X16, X18, X26,LSL #2

0x407e8c SBFM	X27, X2, #0, #31

0x407e90 UMADDL	X25, W3, W12, X25

0x407e94 UMADDL	X13, W3, W0, XZR

0x407e98 LDR	W5, [X18, X11]

0x407e9c ADD	X6, X24, X25

0x407ea0 LDR	Q18, [X24, X25]

0x407ea4 ADD	X3, X23, X25

0x407ea8 ADD	X15, X19, X13

0x407eac ADD	X12, X13, #8

0x407eb0 LDR	W9, [X16, #4]

0x407eb4 ADD	X0, X19, X12

0x407eb8 ADD	X26, X13, #32

0x407ebc LDR	W10, [X17, #4]

0x407ec0 ADD	X17, X19, X26

0x407ec4 STR	W14, [X19, X13]

0x407ec8 LDP	D19, D20, [X6, #16]

0x407ecc LDP	D21, D23, [X6, #32]

0x407ed0 STR	W5, [X15, #4]

0x407ed4 STP	W10, W9, [X15, #56]

0x407ed8 STR	Q18, [X19, X12]

0x407edc STR	D19, [X0, #16]

0x407ee0 STP	D20, D21, [X0, #56]

0x407ee4 STR	D23, [X0, #72]

0x407ee8 LDR	D25, [X23, X25]

0x407eec LDR	D31, [X3, #40]

0x407ef0 LDP	D24, D27, [X3, #8]

0x407ef4 LDP	D28, D29, [X3, #24]

0x407ef8 STR	D25, [X19, X26]

0x407efc STR	D31, [X17, #72]

0x407f00 STP	D24, D27, [X17, #8]

0x407f04 STP	D28, D29, [X17, #56]

0x407f08 TBZ	W8, #0, 407f88

0x407f0c AND	W27, W8, #1951

0x407f10 ADD	W4, W4, W27

0x407f14 ADD	W7, W7, W27

0x407f18 SBFM	X11, X7, #62, #31

0x407f1c MOVZ	W16, #56

0x407f20 LDR	W30, [X30, X11]

0x407f24 MOVZ	W8, #24

0x407f28 SBFM	X25, X4, #61, #31

0x407f2c SUB	X14, X25, W4,SXTW

0x407f30 ADD	X13, X19, X14,LSL #3

0x407f34 SMADDL	X6, W4, W16, XZR

0x407f38 SBFM	X27, X2, #0, #31

0x407f3c SMADDL	X15, W7, W8, XZR

0x407f40 ADD	X5, X19, X6

0x407f44 STR	W30, [X19, X6]

0x407f48 ADD	X10, X24, X15

0x407f4c ADD	X2, X23, X15

0x407f50 LDR	W18, [X18, X11]

0x407f54 STR	W18, [X5, #4]

0x407f58 LDR	D30, [X24, X15]

0x407f5c STR	D30, [X5, #8]

0x407f60 LDR	D22, [X10, #8]

0x407f64 STR	D22, [X13, #16]

0x407f68 LDR	D26, [X10, #16]

0x407f6c STR	D26, [X13, #24]

0x407f70 LDR	D0, [X23, X15]

0x407f74 STR	D0, [X13, #32]

0x407f78 LDR	D1, [X2, #8]

0x407f7c STR	D1, [X13, #40]

0x407f80 LDR	D2, [X2, #16]

0x407f84 STR	D2, [X13, #48]

(81) 0x407f88 ADRP	X30,

(81) 0x407f8c ORR	X0, XZR, X19

(81) 0x407f90 ADD	X3, X30, #3680

(81) 0x407f94 MOVZ	X2, #56

(81) 0x407f98 BL	402610

(81) 0x407f9c LDP	X23, X11, [X21, #8]

(81) 0x407fa0 MOVZ	W1, #1536

(81) 0x407fa4 ORN	W18, WZR, W27

(81) 0x407fa8 ADD	W26, W20, W18

(81) 0x407fac ADD	X13, X27, #1

(81) 0x407fb0 SMADDL	X3, W22, W1, XZR

(81) 0x407fb4 AND	W24, W26, #0

(81) 0x407fb8 ADD	X22, X19, #56

(81) 0x407fbc LDP	X7, X8, [X21, #24]

(81) 0x407fc0 LDR	W0, [X19]

(81) 0x407fc4 ADD	X25, X7, X3

(81) 0x407fc8 ADD	X14, X8, X3

(81) 0x407fcc LDR	D3, [X19, #8]

(81) 0x407fd0 ADD	X4, X25, #24

(81) 0x407fd4 ADD	X15, X14, #24

(81) 0x407fd8 STR	W0, [X23, X27,LSL #2]

(81) 0x407fdc LDR	W21, [X19, #4]

(81) 0x407fe0 STR	W21, [X11, X27,LSL #2]

(81) 0x407fe4 STR	D3, [X25]

(81) 0x407fe8 LDR	D4, [X19, #16]

(81) 0x407fec STR	D4, [X25, #8]

(81) 0x407ff0 LDR	D5, [X19, #24]

(81) 0x407ff4 STR	D5, [X25, #16]

(81) 0x407ff8 LDR	D6, [X19, #32]

(81) 0x407ffc STR	D6, [X14]

(81) 0x408000 LDR	D7, [X19, #40]

(81) 0x408004 STR	D7, [X14, #8]

(81) 0x408008 LDR	D16, [X19, #48]

(81) 0x40800c STR	D16, [X14, #16]

(81) 0x408010 CMP	W20, W13

(81) 0x408014 B.LE	408128

(81) 0x408018 CBZ	W24, 408080

(81) 0x40801c LDR	W17, [X22]

(81) 0x408020 LDR	D17, [X22, #8]

(81) 0x408024 STR	W17, [X23, X13,LSL #2]

(81) 0x408028 LDR	W16, [X22, #4]

(81) 0x40802c STR	W16, [X11, X13,LSL #2]

(81) 0x408030 ADD	X13, X13, #1

(81) 0x408034 STR	D17, [X4]

(81) 0x408038 LDR	D18, [X22, #16]

(81) 0x40803c STR	D18, [X4, #8]

(81) 0x408040 LDR	D19, [X22, #24]

(81) 0x408044 STR	D19, [X4, #16]

(81) 0x408048 ADD	X4, X25, #48

(81) 0x40804c LDR	D20, [X22, #32]

(81) 0x408050 STR	D20, [X15]

(81) 0x408054 LDR	D21, [X22, #40]

(81) 0x408058 STR	D21, [X15, #8]

(81) 0x40805c LDR	D23, [X22, #48]

(81) 0x408060 ADD	X22, X19, #112

(81) 0x408064 STR	D23, [X15, #16]

(81) 0x408068 ADD	X15, X14, #48

(81) 0x40806c CMP	W20, W13

(81) 0x408070 B.LE	408128

(81) 0x408074 HINT	#0

(81) 0x408078 HINT	#0

(81) 0x40807c HINT	#0

  (83) 0x408080 LDR	W10, [X22]

  (83) 0x408084 ORR	X27, XZR, X22

  (83) 0x408088 ADD	X19, X13, #1

  (83) 0x40808c ORR	X5, XZR, X4

  (83) 0x408090 ORR	X6, XZR, X15

  (83) 0x408094 LDR	D25, [X22, #8]

  (83) 0x408098 ADD	X4, X4, #48

  (83) 0x40809c ADD	X22, X22, #112

  (83) 0x4080a0 ADD	X15, X15, #48

  (83) 0x4080a4 STR	W10, [X23, X13,LSL #2]

  (83) 0x4080a8 LDUR	W2, [X22, #404]

  (83) 0x4080ac STR	W2, [X11, X13,LSL #2]

  (83) 0x4080b0 ADD	X13, X13, #2

  (83) 0x4080b4 LDUR	W9, [X22, #456]

  (83) 0x4080b8 STUR	D25, [X4, #464]

  (83) 0x4080bc LDUR	D24, [X22, #416]

  (83) 0x4080c0 STUR	D24, [X4, #472]

  (83) 0x4080c4 LDUR	D27, [X22, #424]

  (83) 0x4080c8 STUR	D27, [X4, #480]

  (83) 0x4080cc LDUR	D28, [X22, #432]

  (83) 0x4080d0 STUR	D28, [X15, #464]

  (83) 0x4080d4 LDUR	D29, [X22, #440]

  (83) 0x4080d8 STUR	D29, [X15, #472]

  (83) 0x4080dc LDUR	D31, [X22, #448]

  (83) 0x4080e0 STUR	D31, [X15, #480]

  (83) 0x4080e4 LDR	D30, [X27, #64]

  (83) 0x4080e8 STR	W9, [X23, X19,LSL #2]

  (83) 0x4080ec LDR	W12, [X27, #60]

  (83) 0x4080f0 STR	W12, [X11, X19,LSL #2]

  (83) 0x4080f4 STUR	D30, [X4, #488]

  (83) 0x4080f8 LDR	D22, [X27, #72]

  (83) 0x4080fc STUR	D22, [X4, #496]

  (83) 0x408100 LDR	D26, [X27, #80]

  (83) 0x408104 STR	D26, [X5, #40]

  (83) 0x408108 LDR	D0, [X27, #88]

  (83) 0x40810c STUR	D0, [X15, #488]

  (83) 0x408110 LDR	D1, [X27, #96]

  (83) 0x408114 STR	D1, [X6, #32]

  (83) 0x408118 LDR	D2, [X27, #104]

  (83) 0x40811c STR	D2, [X6, #40]

  (83) 0x408120 CMP	W20, W13

  (83) 0x408124 B.GT	408080

(81) 0x408128 ADD	SP, X29, #0

(81) 0x40812c LDR	X27, [SP, #80]

(81) 0x408130 LDP	X19, X20, [SP, #16]

(81) 0x408134 LDP	X21, X22, [SP, #32]

(81) 0x408138 LDP	X23, X24, [SP, #48]

(81) 0x40813c LDP	X25, X26, [SP, #64]

(81) 0x408140 LDP	X29, X30, [SP], #96

(81) 0x408144 RET

(81) 0x408148 MOVZ	W9, #1536

(81) 0x40814c SBFM	X27, X2, #0, #31

(81) 0x408150 LDR	W12, [X30, X27,LSL #2]

(81) 0x408154 ORN	W26, WZR, W2

(81) 0x408158 ADD	X25, X27, #1

(81) 0x40815c SMADDL	X3, W22, W9, XZR

(81) 0x408160 ADD	W17, W20, W26

(81) 0x408164 ADD	X0, X19, #56

(81) 0x408168 AND	W7, W17, #0

(81) 0x40816c ADD	X24, X24, X3

(81) 0x408170 ADD	X23, X23, X3

(81) 0x408174 ADD	X14, X23, #24

(81) 0x408178 ADD	X4, X24, #24

(81) 0x40817c LDR	D3, [X24]

(81) 0x408180 STR	W12, [X19]

(81) 0x408184 LDR	W11, [X18, X27,LSL #2]

(81) 0x408188 STR	D3, [X19, #8]

(81) 0x40818c LDR	D4, [X24, #8]

(81) 0x408190 STR	W11, [X19, #4]

(81) 0x408194 STR	D4, [X19, #16]

(81) 0x408198 LDR	D5, [X24, #16]

(81) 0x40819c STR	D5, [X19, #24]

(81) 0x4081a0 LDR	D6, [X23]

(81) 0x4081a4 STR	D6, [X19, #32]

(81) 0x4081a8 LDR	D7, [X23, #8]

(81) 0x4081ac STR	D7, [X19, #40]

(81) 0x4081b0 LDR	D16, [X23, #16]

(81) 0x4081b4 STR	D16, [X19, #48]

(81) 0x4081b8 CMP	W20, W25

(81) 0x4081bc B.LE	407f88

(81) 0x4081c0 CBZ	W7, 408220

(81) 0x4081c4 LDR	D17, [X4]

(81) 0x4081c8 LDR	W16, [X30, X25,LSL #2]

(81) 0x4081cc STR	W16, [X0]

(81) 0x4081d0 LDR	W8, [X18, X25,LSL #2]

(81) 0x4081d4 ADD	X25, X25, #1

(81) 0x4081d8 STR	D17, [X0, #8]

(81) 0x4081dc LDR	D18, [X4, #8]

(81) 0x4081e0 STR	W8, [X0, #4]

(81) 0x4081e4 STR	D18, [X0, #16]

(81) 0x4081e8 LDR	D19, [X4, #16]

(81) 0x4081ec ADD	X4, X24, #48

(81) 0x4081f0 STR	D19, [X0, #24]

(81) 0x4081f4 LDR	D20, [X14]

(81) 0x4081f8 STR	D20, [X0, #32]

(81) 0x4081fc LDR	D21, [X14, #8]

(81) 0x408200 STR	D21, [X0, #40]

(81) 0x408204 LDR	D23, [X14, #16]

(81) 0x408208 ADD	X14, X23, #48

(81) 0x40820c STR	D23, [X0, #48]

(81) 0x408210 ADD	X0, X19, #112

(81) 0x408214 CMP	W20, W25

(81) 0x408218 B.LE	407f88

(81) 0x40821c HINT	#0

  (82) 0x408220 LDR	D25, [X4]

  (82) 0x408224 ADD	X13, X25, #1

  (82) 0x408228 ORR	X15, XZR, X0

  (82) 0x40822c ADD	X5, X4, #24

  (82) 0x408230 ORR	X10, XZR, X14

  (82) 0x408234 LDR	W6, [X30, X25,LSL #2]

  (82) 0x408238 ADD	X0, X0, #112

  (82) 0x40823c ADD	X4, X4, #48

  (82) 0x408240 ADD	X14, X14, #48

  (82) 0x408244 STUR	W6, [X0, #400]

  (82) 0x408248 LDR	W2, [X18, X25,LSL #2]

  (82) 0x40824c ADD	X25, X25, #2

  (82) 0x408250 STUR	D25, [X0, #408]

  (82) 0x408254 LDUR	D24, [X4, #472]

  (82) 0x408258 STUR	W2, [X0, #404]

  (82) 0x40825c LDR	W9, [X30, X13,LSL #2]

  (82) 0x408260 STUR	D24, [X0, #416]

  (82) 0x408264 LDUR	D27, [X4, #480]

  (82) 0x408268 STUR	D27, [X0, #424]

  (82) 0x40826c LDUR	D28, [X14, #464]

  (82) 0x408270 STUR	D28, [X0, #432]

  (82) 0x408274 LDUR	D29, [X14, #472]

  (82) 0x408278 STUR	D29, [X0, #440]

  (82) 0x40827c LDUR	D31, [X14, #480]

  (82) 0x408280 STUR	W9, [X0, #456]

  (82) 0x408284 LDR	W12, [X18, X13,LSL #2]

  (82) 0x408288 STUR	D31, [X0, #448]

  (82) 0x40828c LDUR	D30, [X4, #488]

  (82) 0x408290 STR	W12, [X15, #60]

  (82) 0x408294 STR	D30, [X15, #64]

  (82) 0x408298 LDR	D22, [X5, #8]

  (82) 0x40829c STR	D22, [X15, #72]

  (82) 0x4082a0 LDR	D26, [X5, #16]

  (82) 0x4082a4 STR	D26, [X15, #80]

  (82) 0x4082a8 LDUR	D0, [X14, #488]

  (82) 0x4082ac STR	D0, [X15, #88]

  (82) 0x4082b0 LDR	D1, [X10, #32]

  (82) 0x4082b4 STR	D1, [X15, #96]

  (82) 0x4082b8 LDR	D2, [X10, #40]

  (82) 0x4082bc STR	D2, [X15, #104]

  (82) 0x4082c0 CMP	W20, W25

  (82) 0x4082c4 B.GT	408220

(81) 0x4082c8 B	407f88

0x4082cc ADRP	X7,

0x4082d0 ADD	X0, SP, #0

0x4082d4 ADD	X3, X7, #3680

0x4082d8 MOVZ	X2, #56

0x4082dc BL	402610

0x4082e0 ADD	SP, X29, #0

0x4082e4 LDR	X27, [SP, #80]

0x4082e8 LDP	X19, X20, [SP, #16]

0x4082ec LDP	X21, X22, [SP, #32]

0x4082f0 LDP	X23, X24, [SP, #48]

0x4082f4 LDP	X25, X26, [SP, #64]

0x4082f8 LDP	X29, X30, [SP], #96

0x4082fc RET

0x408300 MOVZ	W3, #0

0x408304 MOVZ	W4, #0

0x408308 ORR	W7, WZR, W2

0x40830c B	407e70

0x408310 HINT	#0

0x408314 HINT	#0

0x408318 HINT	#0

0x40831c HINT	#0

Coverage (%)	Name	Source Location	Module
►13.17+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►13.11+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.80+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.50+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.38+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.26+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.26+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►10.44+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.22% of application time for run gcc_0

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.00 to 9.33 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 21.00 to 16.33 cycles (1.29x speedup).

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

31% of VPU loads are used in vector version.
16% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.00 to 0.50 cycles (42.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 300 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	172
loop length	688
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.00	5.00	17.67	17.67	17.67	17.67	17.67	17.67	7.00	7.00	0.00	0.00	18.17	17.83	18.00	5.50	5.50
cycles	5.00	5.00	17.67	17.67	17.67	17.67	17.67	17.67	7.00	7.00	0.00	0.00	18.17	17.83	18.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.00
Overall L1	21.00

Vectorization ratios

all	10%
load	31%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.00 cycles. At this rate:

14% of peak load performance is reached (14.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407c64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X11, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W5, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM W2, W11, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X1, [X1, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [X1, X11,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SMADDL X3, W0, W5, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W20, W0, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X3, #15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X6, X4, #7932	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, X6,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X19, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W2, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4082cc <sortAtomsInCell+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X18, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X22, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W8, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X24, X23, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 408148 <sortAtomsInCell+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W10, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W25, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X13, W9, W10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X26, X11, #58, #57	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X14, X11, #56, #55	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SMADDL X25, W11, W25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X15, X26, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X30, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X16, W9, W5, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X18, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X30, X15,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X13, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X24, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X18, X15,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X24, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, SP, X16,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X7, X23, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CCMP X10, X5, #0, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
ADD X4, X23, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CSINC W9, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X3, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SUB X6, X16, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CCMP X10, X4, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
ADD X14, SP, X6,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
CSINC W15, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP SP, X17,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
AND W16, W9, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CCMP X14, X12, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W17, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP SP, X13,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
CCMP X14, X11, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W27, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W13, W17, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS WZR, W16, W13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B.EQ 408148 <sortAtomsInCell+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 408300 <sortAtomsInCell+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W8, W0, #2, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ X6, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X17, X8, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND W4, W0, #1886	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ORR W3, WZR, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W0, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 407f88 <sortAtomsInCell+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W8, W0, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W7, W2, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 407f18 <sortAtomsInCell+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W12, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X26, W3,UXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X11, X26, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X30, X26,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W14, [X30, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W0, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X18, X26,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
UMADDL X25, W3, W12, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UMADDL X13, W3, W0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W5, [X18, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X24, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q18, [X24, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X3, X23, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X19, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W9, [X16, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X19, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X13, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W10, [X17, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X19, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W14, [X19, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP D19, D20, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D21, D23, [X6, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR W5, [X15, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W10, W9, [X15, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR Q18, [X19, X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR D19, [X0, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D20, D21, [X0, #56]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR D23, [X0, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D25, [X23, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D31, [X3, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D24, D27, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D28, D29, [X3, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR D25, [X19, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STR D31, [X17, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D24, D27, [X17, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D28, D29, [X17, #56]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
TBZ W8, #0, 407f88 <sortAtomsInCell+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W27, W8, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W4, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W7, W7, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X11, X7, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W16, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W30, [X30, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W8, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X25, X4, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X25, W4,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X13, X19, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SMADDL X6, W4, W16, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SMADDL X15, W7, W8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X19, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W30, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X24, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X23, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W18, [X18, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W18, [X5, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D30, [X24, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D30, [X5, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D22, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D22, [X13, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D26, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D26, [X13, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X23, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D0, [X13, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D1, [X13, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D2, [X13, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADRP X7, <2004062cc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X7, #3680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402610 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD SP, X29, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W4, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W7, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 407e70 <sortAtomsInCell+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.22% of application time for run gcc_0

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.00 to 9.33 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

10% of VPU instructions are used in vector version (process two or more data elements in vector registers):

31% of VPU loads are used in vector version.
16% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.00 to 0.50 cycles (42.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 300 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	172
loop length	688
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.00	5.00	17.67	17.67	17.67	17.67	17.67	17.67	7.00	7.00	0.00	0.00	18.17	17.83	18.00	5.50	5.50
cycles	5.00	5.00	17.67	17.67	17.67	17.67	17.67	17.67	7.00	7.00	0.00	0.00	18.17	17.83	18.00	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.00
Overall L1	21.00

Vectorization ratios

all	10%
load	31%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.00 cycles. At this rate:

14% of peak load performance is reached (14.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 407c64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X11, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W5, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM W2, W11, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X1, [X1, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [X1, X11,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SMADDL X3, W0, W5, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W20, W0, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X3, #15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X6, X4, #7932	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, X6,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADD X19, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W2, W20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 4082cc <sortAtomsInCell+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X30, X18, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X22, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W8, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP X24, X23, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 408148 <sortAtomsInCell+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W9, WZR, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W10, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W25, #1536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X13, W9, W10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UBFM X26, X11, #58, #57	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X14, X11, #56, #55	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SMADDL X25, W11, W25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X15, X26, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X30, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UMADDL X16, W9, W5, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X11, X18, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X30, X15,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X13, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X24, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X18, X15,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, X24, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, SP, X16,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
CMP X4, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X7, X23, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CCMP X10, X5, #0, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
ADD X4, X23, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CSINC W9, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X3, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SUB X6, X16, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CCMP X10, X4, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
ADD X14, SP, X6,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
CSINC W15, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP SP, X17,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
AND W16, W9, W15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CCMP X14, X12, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W17, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP SP, X13,UXTX	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
CCMP X14, X11, #0, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W27, WZR, WZR, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W13, W17, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS WZR, W16, W13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B.EQ 408148 <sortAtomsInCell+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W10, W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 408300 <sortAtomsInCell+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM W8, W0, #2, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ X6, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X17, X8, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND W4, W0, #1886	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
ORR W3, WZR, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W0, W4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 407f88 <sortAtomsInCell+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W8, W0, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W7, W2, W4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 407f18 <sortAtomsInCell+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W12, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X26, W3,UXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X11, X26, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X30, X26,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W14, [X30, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W0, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X18, X26,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
UMADDL X25, W3, W12, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
UMADDL X13, W3, W0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W5, [X18, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X24, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q18, [X24, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X3, X23, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X19, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W9, [X16, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X19, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X13, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W10, [X17, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X19, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W14, [X19, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP D19, D20, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D21, D23, [X6, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR W5, [X15, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W10, W9, [X15, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR Q18, [X19, X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR D19, [X0, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D20, D21, [X0, #56]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR D23, [X0, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D25, [X23, X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D31, [X3, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D24, D27, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D28, D29, [X3, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR D25, [X19, X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STR D31, [X17, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D24, D27, [X17, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D28, D29, [X17, #56]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
TBZ W8, #0, 407f88 <sortAtomsInCell+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND W27, W8, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W4, W4, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD W7, W7, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X11, X7, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W16, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W30, [X30, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W8, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SBFM X25, X4, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X25, W4,SXTW	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ADD X13, X19, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SMADDL X6, W4, W16, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SBFM X27, X2, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SMADDL X15, W7, W8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X5, X19, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W30, [X19, X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X10, X24, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X23, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W18, [X18, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W18, [X5, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR D30, [X24, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D30, [X5, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D22, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D22, [X13, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D26, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D26, [X13, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X23, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D0, [X13, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D1, [X13, #40]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D2, [X13, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADRP X7, <2004062cc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X7, #3680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 402610 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD SP, X29, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W4, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W7, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 407e70 <sortAtomsInCell+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼sortAtomsInCell–	1.43	0.12
○Loop 84 - haloExchange.c:621-630 - exec	0.98	0.06
▼Loop 81 - haloExchange.c:621-645 - exec–	0.01	0.01
○Loop 83 - haloExchange.c:633-642 - exec	0.21	0.01
○Loop 82 - haloExchange.c:621-630 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code