OV - exec - Loop 119

0x40b48c LDRSW	X18, [X15], #4    [1]

0x40b490 LDR	D2, [X19]    [5]

0x40b494 LDUR	D3, [X17, #504]    [3]

0x40b498 SUBS	W13, W13, #1

0x40b49c ADD	X18, X14, X18,LSL #4

0x40b4a0 LDR	D1, [X18, #8]    [4]

0x40b4a4 FMUL	D2, D2, D3

0x40b4a8 LDP	D3, D4, [X16, #1016]    [2]

0x40b4ac FDIV	D1, D0, D1

0x40b4b0 FMADD	D2, D2, D1, D3

0x40b4b4 STUR	D2, [X16, #504]    [2]

0x40b4b8 LDR	D2, [X19]    [5]

0x40b4bc LDR	D3, [X17]    [3]

0x40b4c0 FMUL	D2, D2, D3

0x40b4c4 FMADD	D2, D2, D1, D4

0x40b4c8 STR	D2, [X16]    [2]

0x40b4cc LDR	D2, [X19]    [5]

0x40b4d0 LDR	D3, [X17, #8]    [3]

0x40b4d4 ADD	X17, X17, #24

0x40b4d8 FMUL	D2, D2, D3

0x40b4dc LDR	D3, [X16, #8]    [2]

0x40b4e0 FMADD	D1, D2, D1, D3

0x40b4e4 STR	D1, [X16, #8]    [2]

0x40b4e8 ADD	X16, X16, #24

0x40b4ec B.NE	40b48c

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94

--------------------------------------------------------------------------------

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.13
CQA speedup if fully vectorized	1.74
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P12,
Function	advancePosition.omp_outlined
Source	timestep.c:88-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.58
Front-end cycles	3.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.92
P3 cycles	0.92
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	4.50
P13 cycles	4.17
P14 cycles	4.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	2.22
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	3.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	24.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	5.00
Vectorization ratio load	11.11
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	51.25
Vector-efficiency ratio load	55.56
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.13
CQA speedup if fully vectorized	1.74
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P12,
Function	advancePosition.omp_outlined
Source	timestep.c:88-94
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	2.58
Front-end cycles	3.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.92
P3 cycles	0.92
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	4.50
P13 cycles	4.17
P14 cycles	4.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	2.22
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	3.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	24.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	5.00
Vectorization ratio load	11.11
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	51.25
Vector-efficiency ratio load	55.56
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advancePosition.omp_outlined
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.50 to 4.17 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.50 to 2.58 cycles (1.74x speedup).

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
6: multiply (3 inside FMA instructions)
1: divide

The binary loop is loading 84 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.92	0.92	0.83	0.83	0.75	0.75	2.50	2.50	2.50	2.50	4.50	4.17	4.33	0.00	0.00
cycles	0.50	0.50	0.92	0.92	0.83	0.83	0.75	0.75	2.50	2.50	2.50	2.50	4.50	4.17	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	1.75-3.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.13
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

INT

all	7%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	5%
load	11%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

19% of peak load performance is reached (18.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b48c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDRSW X18, [X15], #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDUR D3, [X17, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SUBS W13, W13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X18, X14, X18,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDP D3, D4, [X16, #1016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV D1, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D2, D2, D1, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STUR D2, [X16, #504]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D2, D2, D1, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D2, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X17, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X17, X17, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D3, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D1, D2, D1, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D1, [X16, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X16, X16, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.NE 40b48c <advancePosition.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advancePosition.omp_outlined
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.50 to 4.17 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.50 to 2.58 cycles (1.74x speedup).

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
6: multiply (3 inside FMA instructions)
1: divide

The binary loop is loading 84 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.92	0.92	0.83	0.83	0.75	0.75	2.50	2.50	2.50	2.50	4.50	4.17	4.33	0.00	0.00
cycles	0.50	0.50	0.92	0.92	0.83	0.83	0.75	0.75	2.50	2.50	2.50	2.50	4.50	4.17	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	1.75-3.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.13
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

INT

all	7%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	5%
load	11%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

19% of peak load performance is reached (18.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 40b48c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDRSW X18, [X15], #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDUR D3, [X17, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SUBS W13, W13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
ADD X18, X14, X18,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D1, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDP D3, D4, [X16, #1016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV D1, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
FMADD D2, D2, D1, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STUR D2, [X16, #504]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D2, D2, D1, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D2, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D3, [X17, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X17, X17, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR D3, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D1, D2, D1, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D1, [X16, #8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X16, X16, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.NE 40b48c <advancePosition.omp_outlined+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code