OV - exec - Loop 109

	Loop Id: 109	Module: exec	Source: ljForce.c:191-216 [...]	Coverage: 50.24%

0x408fa0 ADD	X24, X24, #24

0x408fa4 ADD	W7, W7, #1

0x408fa8 CMP	W1, W7

0x408fac B.LE	408f80

0x408fb0 LDR	Q16, [X6]    [1]

0x408fb4 LDUR	Q17, [X24, #496]    [7]

0x408fb8 LDR	D19, [X24]    [7]

0x408fbc FSUB	V16.2D, V16.2D, V17.2D

0x408fc0 FMADD	D18, D16, D16, D0

0x408fc4 MOV	D17, V16.D[1]

0x408fc8 FMLA	D18, D17, V16.D[1]

0x408fcc LDUR	D17, [X6, #16]    [1]

0x408fd0 FSUB	D17, D17, S19

0x408fd4 LDR	D19, [X23]    [6]

0x408fd8 FMADD	D18, D17, D17, D18

0x408fdc FCMP	D18, #0

0x408fe0 FCCMP	D18, D19, #2, #12

0x408fe4 B.HI	408fa0

0x408fe8 FDIV	D18, D1, D18

0x408fec LDR	D19, [X22]    [5]

0x408ff0 LDR	D21, [X21]    [4]

0x408ff4 LDP	X27, X26, [X2, #40]    [10]

0x408ff8 FMUL	D20, D18, D18

0x408ffc FMUL	D20, D18, D20

0x409000 FMUL	D19, D20, D19

0x409004 FADD	D20, D19, D2

0x409008 FNMSUB	D20, D19, D20, D21

0x40900c LDR	D21, [X26, X5,LSL #3]    [9]

0x409010 FMADD	D7, D20, D3, D7

0x409014 FMADD	D21, D20, D3, D21

0x409018 STR	D21, [X26, X5,LSL #3]    [9]

0x40901c MADD	X26, X5, X14, X27

0x409020 STR	D7, [SP, #16]    [2]

0x409024 LDR	D20, [X10]    [3]

0x409028 FMUL	D20, D20, D4

0x40902c FMUL	D20, D19, D20

0x409030 FMADD	D19, D19, D6, D5

0x409034 FMUL	D18, D18, D20

0x409038 FMUL	D18, D19, D18

0x40903c LDR	Q19, [X26]    [8]

0x409040 FMLS	V19.2D, V16.2D, V18.D[0]

0x409044 LDR	D16, [X26, #16]    [8]

0x409048 STR	Q19, [X26]    [8]

0x40904c FMSUB	D16, D17, D18, D16

0x409050 STR	D16, [X26, #16]    [8]

0x409054 B	408fa0

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 191 - 216

--------------------------------------------------------------------------------

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.35
CQA speedup if FP arith vectorized	1.27
CQA speedup if fully vectorized	1.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P8, P9, P10, P11,
Function	ljForce.omp_outlined.5
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	4.00
Front-end cycles	5.75
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	0.67
P3 cycles	0.58
P4 cycles	0.67
P5 cycles	0.50
P6 cycles	1.00
P7 cycles	0.58
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	6.75
P11 cycles	6.75
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	4.74
Nb FLOP add-sub	4.00
Nb FLOP mul	7.00
Nb FLOP fma	10.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.89
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	15.00
Vectorization ratio load	27.27
Vectorization ratio store	25.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	25.00
Vectorization ratio fma	11.11
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	57.50
Vector-efficiency ratio load	63.64
Vector-efficiency ratio store	62.50
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	56.25
Vector-efficiency ratio fma	61.11
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	43.75

Metric	Value
CQA speedup if no scalar integer	1.35
CQA speedup if FP arith vectorized	1.27
CQA speedup if fully vectorized	1.69
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P8, P9, P10, P11,
Function	ljForce.omp_outlined.5
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	4.00
Front-end cycles	5.75
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	0.67
P3 cycles	0.58
P4 cycles	0.67
P5 cycles	0.50
P6 cycles	1.00
P7 cycles	0.58
P8 cycles	6.75
P9 cycles	6.75
P10 cycles	6.75
P11 cycles	6.75
P12 cycles	5.33
P13 cycles	5.33
P14 cycles	5.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	4.74
Nb FLOP add-sub	4.00
Nb FLOP mul	7.00
Nb FLOP fma	10.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.89
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	15.00
Vectorization ratio load	27.27
Vectorization ratio store	25.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	25.00
Vectorization ratio fma	11.11
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	57.50
Vector-efficiency ratio load	63.64
Vector-efficiency ratio store	62.50
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	56.25
Vector-efficiency ratio fma	61.11
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	43.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:191-216
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:191,197-216.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.75 to 5.00 cycles (1.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.75 to 4.00 cycles (1.69x speedup).

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

27% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
11% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

14: addition or subtraction (10 inside FMA instructions)
17: multiply (10 inside FMA instructions)
1: divide

The binary loop is loading 128 bytes. The binary loop is storing 40 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	0.67	0.58	0.67	0.50	1.00	0.58	6.75	6.75	6.75	6.75	5.33	5.33	5.33	0.00	0.00
cycles	1.50	1.50	0.67	0.58	0.67	0.50	1.00	0.58	6.75	6.75	6.75	6.75	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	5.75
Overall L1	6.75

Vectorization ratios

INT

all	22%
load	27%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	33%
fma	11%
div/sqrt	0%
other	0%

INT+FP

all	15%
load	27%
store	25%
mul	0%
add-sub	25%
fma	11%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

19% of peak load performance is reached (18.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.93 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X24, X24, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W7, W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 408f80 <ljForce.omp_outlined.5+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q16, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q17, [X24, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D19, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB V16.2D, V16.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMADD D18, D16, D16, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
MOV D17, V16.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA D18, D17, V16.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (100.0%)
LDUR D17, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D17, D17, S19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D19, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D18, D17, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMP D18, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMP D18, D19, #2, #12	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.HI 408fa0 <ljForce.omp_outlined.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D18, D1, D18	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR D19, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D21, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP X27, X26, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
FMUL D20, D18, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D20, D18, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D19, D20, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FADD D20, D19, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNMSUB D20, D19, D20, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDR D21, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D7, D20, D3, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D21, D20, D3, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D21, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X26, X5, X14, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
STR D7, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D20, D20, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D20, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D19, D19, D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D18, D18, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D18, D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR Q19, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS V19.2D, V16.2D, V18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D16, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR Q19, [X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FMSUB D16, D17, D18, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D16, [X26, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B 408fa0 <ljForce.omp_outlined.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:191-216
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.75 to 5.00 cycles (1.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

15% of VPU instructions are used in vector version (process two or more data elements in vector registers):

27% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
11% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

14: addition or subtraction (10 inside FMA instructions)
17: multiply (10 inside FMA instructions)
1: divide

The binary loop is loading 128 bytes. The binary loop is storing 40 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	0.67	0.58	0.67	0.50	1.00	0.58	6.75	6.75	6.75	6.75	5.33	5.33	5.33	0.00	0.00
cycles	1.50	1.50	0.67	0.58	0.67	0.50	1.00	0.58	6.75	6.75	6.75	6.75	5.33	5.33	5.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	5.75
Overall L1	6.75

Vectorization ratios

INT

all	22%
load	27%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	33%
fma	11%
div/sqrt	0%
other	0%

INT+FP

all	15%
load	27%
store	25%
mul	0%
add-sub	25%
fma	11%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

19% of peak load performance is reached (18.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (5.93 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408fb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X24, X24, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD W7, W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W1, W7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 408f80 <ljForce.omp_outlined.5+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q16, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDUR Q17, [X24, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D19, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB V16.2D, V16.2D, V17.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMADD D18, D16, D16, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
MOV D17, V16.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA D18, D17, V16.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (100.0%)
LDUR D17, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FSUB D17, D17, S19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D19, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D18, D17, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FCMP D18, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMP D18, D19, #2, #12	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
B.HI 408fa0 <ljForce.omp_outlined.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D18, D1, D18	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR D19, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D21, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP X27, X26, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
FMUL D20, D18, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D20, D18, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D19, D20, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FADD D20, D19, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNMSUB D20, D19, D20, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
LDR D21, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMADD D7, D20, D3, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMADD D21, D20, D3, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D21, [X26, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MADD X26, X5, X14, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
STR D7, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR D20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL D20, D20, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D20, D19, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMADD D19, D19, D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
FMUL D18, D18, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
FMUL D18, D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (50.0%)
LDR Q19, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLS V19.2D, V16.2D, V18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D16, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
STR Q19, [X26]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FMSUB D16, D17, D18, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	scal (50.0%)
STR D16, [X26, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B 408fa0 <ljForce.omp_outlined.5+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code