OV - exec - Loop 107

0x408f40 ADD	X17, X17, #1

0x408f44 CMP	X17, X9

0x408f48 B.EQ	408f04

0x408f4c LDR	W0, [X16, X17,LSL #2]

0x408f50 TBNZ	W0, #31, 409140

0x408f54 LDR	W1, [X11, X0,LSL #2]

0x408f58 CMP	W1, #0

0x408f5c B.LE	408f40

0x408f60 LDR	X2, [X25, #32]

0x408f64 UBFM	W0, W0, #26, #25

0x408f68 ORR	X5, XZR, X15

0x408f6c ADD	W1, W1, W0

0x408f70 LDR	X3, [X2, #24]

0x408f74 UMADDL	X4, W0, W14, X3

0x408f78 ADD	X4, X4, #16

0x408f7c B	408f8c

  (108) 0x408f80 ADD	X5, X5, #1

  (108) 0x408f84 CMP	X5, X18

  (108) 0x408f88 B.GE	408f40

  (108) 0x408f8c MADD	X6, X5, X14, X3

  (108) 0x408f90 ORR	W7, WZR, W0

  (108) 0x408f94 ORR	X24, XZR, X4

  (108) 0x408f98 B	408fb0

    (109) 0x408fa0 ADD	X24, X24, #24

    (109) 0x408fa4 ADD	W7, W7, #1

    (109) 0x408fa8 CMP	W1, W7

    (109) 0x408fac B.LE	408f80

    (109) 0x408fb0 LDR	Q16, [X6]

    (109) 0x408fb4 LDUR	Q17, [X24, #496]

    (109) 0x408fb8 LDR	D19, [X24]

    (109) 0x408fbc FSUB	V16.2D, V16.2D, V17.2D

    (109) 0x408fc0 FMADD	D18, D16, D16, D0

    (109) 0x408fc4 MOV	D17, V16.D[1]

    (109) 0x408fc8 FMLA	D18, D17, V16.D[1]

    (109) 0x408fcc LDUR	D17, [X6, #16]

    (109) 0x408fd0 FSUB	D17, D17, S19

    (109) 0x408fd4 LDR	D19, [X23]

    (109) 0x408fd8 FMADD	D18, D17, D17, D18

    (109) 0x408fdc FCMP	D18, #0

    (109) 0x408fe0 FCCMP	D18, D19, #2, #12

    (109) 0x408fe4 B.HI	408fa0

    (109) 0x408fe8 FDIV	D18, D1, D18

    (109) 0x408fec LDR	D19, [X22]

    (109) 0x408ff0 LDR	D21, [X21]

    (109) 0x408ff4 LDP	X27, X26, [X2, #40]

    (109) 0x408ff8 FMUL	D20, D18, D18

    (109) 0x408ffc FMUL	D20, D18, D20

    (109) 0x409000 FMUL	D19, D20, D19

    (109) 0x409004 FADD	D20, D19, D2

    (109) 0x409008 FNMSUB	D20, D19, D20, D21

    (109) 0x40900c LDR	D21, [X26, X5,LSL #3]

    (109) 0x409010 FMADD	D7, D20, D3, D7

    (109) 0x409014 FMADD	D21, D20, D3, D21

    (109) 0x409018 STR	D21, [X26, X5,LSL #3]

    (109) 0x40901c MADD	X26, X5, X14, X27

    (109) 0x409020 STR	D7, [SP, #16]

    (109) 0x409024 LDR	D20, [X10]

    (109) 0x409028 FMUL	D20, D20, D4

    (109) 0x40902c FMUL	D20, D19, D20

    (109) 0x409030 FMADD	D19, D19, D6, D5

    (109) 0x409034 FMUL	D18, D18, D20

    (109) 0x409038 FMUL	D18, D19, D18

    (109) 0x40903c LDR	Q19, [X26]

    (109) 0x409040 FMLS	V19.2D, V16.2D, V18.D[0]

    (109) 0x409044 LDR	D16, [X26, #16]

    (109) 0x409048 STR	Q19, [X26]

    (109) 0x40904c FMSUB	D16, D17, D18, D16

    (109) 0x409050 STR	D16, [X26, #16]

    (109) 0x409054 B	408fa0

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue, P0, P1,
Function	ljForce.omp_outlined.5
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.59
Front-end cycles	2.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.42
P3 cycles	1.25
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.33
P13 cycles	1.33
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	37.50
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	41.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue, P0, P1,
Function	ljForce.omp_outlined.5
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.59
Front-end cycles	2.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.42
P3 cycles	1.25
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.33
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.33
P13 cycles	1.33
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	37.50
Vector-efficiency ratio load	37.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	41.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 37% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.59 cycles (3.37x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.42	1.25	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	2.00	2.00	1.42	1.25	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408f4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X17, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X17, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.EQ 408f04 <ljForce.omp_outlined.5+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X16, X17,LSL #2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
TBNZ W0, #31, 409140 <ljForce.omp_outlined.5+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X11, X0,LSL #2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP W1, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.LE 408f40 <ljForce.omp_outlined.5+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X25, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
UBFM W0, W0, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
ORR X5, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
LDR X3, [X2, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
UMADDL X4, W0, W14, X3	1	0	0	0	0	0	0	1	0	0	0	0	2	1	N/A
ADD X4, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
B 408f8c <ljForce.omp_outlined.5+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 37% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.59 cycles (3.37x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.42	1.25	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	2.00	2.00	1.42	1.25	1.33	1.33	1.33	1.33	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

12% of peak load performance is reached (12.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 408f4c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
ADD X17, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X17, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.EQ 408f04 <ljForce.omp_outlined.5+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X16, X17,LSL #2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
TBNZ W0, #31, 409140 <ljForce.omp_outlined.5+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X11, X0,LSL #2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (25.0%)
CMP W1, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.LE 408f40 <ljForce.omp_outlined.5+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X25, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
UBFM W0, W0, #26, #25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
ORR X5, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
ADD W1, W1, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
LDR X3, [X2, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
UMADDL X4, W0, W14, X3	1	0	0	0	0	0	0	1	0	0	0	0	2	1	N/A
ADD X4, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
B 408f8c <ljForce.omp_outlined.5+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code