OV - exec - Function advanceVelocity.omp

	Function: advanceVelocity.omp_outlined	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 1.80% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x40b150 SUB	SP, SP, #80

0x40b154 STP	X29, X30, [SP, #32]

0x40b158 STP	X22, X21, [SP, #48]

0x40b15c STP	X20, X19, [SP, #64]

0x40b160 ADD	X29, SP, #32

0x40b164 LDR	W8, [X2]

0x40b168 SUBS	W22, W8, #1

0x40b16c B.LT	40b1e0

0x40b170 LDR	W20, [X0]

0x40b174 ORR	X19, XZR, X4

0x40b178 ORR	X21, XZR, X3

0x40b17c MOVZ	W8, #1

0x40b180 ADRP	X0,

0x40b184 ADD	X0, X0, #3064

0x40b188 ADD	X3, SP, #16

0x40b18c SUB	X4, X29, #4

0x40b190 SUB	X5, X29, #8

0x40b194 STP	W22, WZR, [X29, #504]

0x40b198 STR	WZR, [SP, #16]

0x40b19c STUR	W8, [X29, #500]

0x40b1a0 SUB	X6, X29, #12

0x40b1a4 MOVZ	W2, #34

0x40b1a8 MOVZ	W7, #1

0x40b1ac STR	W8, [SP]

0x40b1b0 ORR	W1, WZR, W20

0x40b1b4 BL	4023e0

0x40b1b8 LDP	W9, W8, [X29, #504]

0x40b1bc SBFM	X8, X8, #0, #31

0x40b1c0 CMP	W9, W22

0x40b1c4 CSEL	W11, W9, W22, #11

0x40b1c8 CMP	W8, W11

0x40b1cc B.LE	40b1f4

(114) 0x40b1d0 ADRP	X0,

(114) 0x40b1d4 ADD	X0, X0, #3088

(114) 0x40b1d8 ORR	W1, WZR, W20

(114) 0x40b1dc BL	402170

(114) 0x40b1e0 LDP	X20, X19, [SP, #64]

(114) 0x40b1e4 LDP	X22, X21, [SP, #48]

(114) 0x40b1e8 LDP	X29, X30, [SP, #32]

(114) 0x40b1ec ADD	SP, SP, #80

(114) 0x40b1f0 RET

(114) 0x40b1f4 LDR	X9, [X21]

(114) 0x40b1f8 UBFM	W18, W8, #26, #25

(114) 0x40b1fc ADD	W11, W11, #1

(114) 0x40b200 ADD	X12, X19, #8

(114) 0x40b204 LDR	X10, [X9, #24]

(114) 0x40b208 LDR	X10, [X10, #120]

(114) 0x40b20c B	40b230

0x40b210 HINT	#0

0x40b214 HINT	#0

0x40b218 HINT	#0

0x40b21c HINT	#0

(114) 0x40b220 ADD	X8, X8, #1

(114) 0x40b224 ADD	W18, W13, #64

(114) 0x40b228 CMP	W11, W8

(114) 0x40b22c B.EQ	40b1d0

(114) 0x40b230 LDR	W14, [X10, X8,LSL #2]

(114) 0x40b234 SBFM	X13, X18, #0, #31

(114) 0x40b238 CMP	W14, #1

(114) 0x40b23c B.LT	40b220

(114) 0x40b240 LDR	X16, [X9, #32]

(114) 0x40b244 LDP	X16, X15, [X16, #32]

(114) 0x40b248 CMP	W14, #1

(114) 0x40b24c B.NE	40b2cc

(114) 0x40b250 ORR	W17, WZR, WZR

(114) 0x40b254 ORR	X18, XZR, X13

(114) 0x40b258 SUB	W14, W14, W17

(114) 0x40b25c ADD	X17, X18, X18,LSL #1

(114) 0x40b260 ADD	X16, X16, X17,LSL #3

(114) 0x40b264 ADD	X15, X15, X17,LSL #3

(114) 0x40b268 ADD	X16, X16, #8

(114) 0x40b26c ADD	X15, X15, #8

(114) 0x40b270 HINT	#0

(114) 0x40b274 HINT	#0

(114) 0x40b278 HINT	#0

(114) 0x40b27c HINT	#0

  (115) 0x40b280 LDR	D0, [X19]

  (115) 0x40b284 LDUR	D1, [X15, #504]

  (115) 0x40b288 LDP	D2, D3, [X16, #1016]

  (115) 0x40b28c SUBS	W14, W14, #1

  (115) 0x40b290 FMADD	D0, D0, D1, D2

  (115) 0x40b294 LDR	D2, [X16, #8]

  (115) 0x40b298 STUR	D0, [X16, #504]

  (115) 0x40b29c LDR	D0, [X19]

  (115) 0x40b2a0 LDR	D1, [X15]

  (115) 0x40b2a4 FMADD	D0, D0, D1, D3

  (115) 0x40b2a8 STR	D0, [X16]

  (115) 0x40b2ac LDR	D0, [X19]

  (115) 0x40b2b0 LDR	D1, [X15, #8]

  (115) 0x40b2b4 ADD	X15, X15, #24

  (115) 0x40b2b8 FMADD	D0, D0, D1, D2

  (115) 0x40b2bc STR	D0, [X16, #8]

  (115) 0x40b2c0 ADD	X16, X16, #24

  (115) 0x40b2c4 B.NE	40b280

(114) 0x40b2c8 B	40b220

(114) 0x40b2cc SUB	W0, W14, #1

(114) 0x40b2d0 ADD	X18, X13, W18,SXTW #1

(114) 0x40b2d4 ORR	W17, WZR, WZR

(114) 0x40b2d8 ADD	X0, X13, X0

(114) 0x40b2dc ADD	X0, X0, X0,LSL #1

(114) 0x40b2e0 UBFM	X1, X18, #61, #60

(114) 0x40b2e4 ADD	X2, X16, X0,LSL #3

(114) 0x40b2e8 ADD	X0, X15, X0,LSL #3

(114) 0x40b2ec ADD	X18, X16, X1

(114) 0x40b2f0 ADD	X0, X0, #24

(114) 0x40b2f4 ADD	X2, X2, #24

(114) 0x40b2f8 CMP	X18, X0

(114) 0x40b2fc ADD	X0, X15, X1

(114) 0x40b300 CCMP	X0, X2, #2, #3

(114) 0x40b304 CSINC	W0, WZR, WZR, #2

(114) 0x40b308 CMP	X2, X19

(114) 0x40b30c CCMP	X18, X12, #2, #8

(114) 0x40b310 B.CC	40b254

(114) 0x40b314 ORR	X18, XZR, X13

(114) 0x40b318 TBNZ	W0, #0, 40b258

(114) 0x40b31c AND	X17, X14, #6015

(114) 0x40b320 ADD	X0, X16, X1

(114) 0x40b324 ADD	X1, X15, X1

(114) 0x40b328 ADD	X18, X17, X13

(114) 0x40b32c ORR	X2, XZR, X17

(114) 0x40b330 HINT	#0

(114) 0x40b334 HINT	#0

(114) 0x40b338 HINT	#0

(114) 0x40b33c HINT	#0

  (116) 0x40b340 LDR	D0, [X19]

  (116) 0x40b344 LD3	{V1.2D, V2.2D, V3.2D}, [X1], #80

  (116) 0x40b348 SUBS	X2, X2, #2

  (116) 0x40b34c LD3	{V4.2D, V5.2D, V6.2D}, [X0]

  (116) 0x40b350 FMLA	V4.2D, V1.2D, V0.D[0]

  (116) 0x40b354 LDR	D0, [X19]

  (116) 0x40b358 FMLA	V5.2D, V2.2D, V0.D[0]

  (116) 0x40b35c FMLA	V6.2D, V3.2D, V0.D[0]

  (116) 0x40b360 ST3	{V4.2D, V5.2D, V6.2D}, [X0], #48

  (116) 0x40b364 B.NE	40b340

(114) 0x40b368 CMP	X17, X14

(114) 0x40b36c B.EQ	40b220

(114) 0x40b370 B	40b258

0x40b374 HINT	#0

0x40b378 HINT	#0

0x40b37c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 47% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.00 to 3.10 cycles (1.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40b150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40b1e0 <advanceVelocity.omp_outlined+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f180>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W22, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023e0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W9, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W11, W9, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 40b1f4 <advanceVelocity.omp_outlined+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 0.50 cycles (8.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50
cycles	1.50	1.50	3.42	3.42	3.33	3.33	3.25	3.25	0.00	0.00	0.00	0.00	3.50	3.50	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (17.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40b150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS W22, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 40b1e0 <advanceVelocity.omp_outlined+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <41f180>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3064	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W22, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4023e0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W9, W8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X8, X8, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W9, W22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W11, W9, W22, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, W11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 40b1f4 <advanceVelocity.omp_outlined+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.omp_outlined–	1.80	0.21
▼Loop 114 - timestep.c:71-78 - exec–	0.01	0.01
○Loop 116 - timestep.c:74-78 - exec	1.70	0.20
○Loop 115 - timestep.c:74-78 - exec	0.09	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code