OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:209-385 [...]	Coverage (incl. loops): 0.23% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 385

--------------------------------------------------------------------------------

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x408500 STP	X29, X30, [SP, #976]!

0x408504 STP	X22, X21, [SP, #16]

0x408508 STP	X20, X19, [SP, #32]

0x40850c ADD	X29, SP, #0

0x408510 LDR	W12, [X0, #12]

0x408514 LDR	W8, [X0, #20]

0x408518 CMP	W12, W8

0x40851c B.GE	408540

0x408520 LDR	X9, [X0, #120]

0x408524 SBFM	X8, X12, #0, #31

(99) 0x408528 STR	WZR, [X9, X8,LSL #2]

(99) 0x40852c ADD	X8, X8, #1

(99) 0x408530 LDRSW	X10, [X0, #20]

(99) 0x408534 CMP	X8, X10

(99) 0x408538 B.LT	408528

0x40853c LDR	W12, [X0, #12]

0x408540 CMP	W12, #1

0x408544 B.LT	4088a8

0x408548 LDR	X14, [X0, #120]

0x40854c MOVZ	W9, #24

0x408550 ORR	X8, XZR, XZR

0x408554 B	40856c

0x408558 HINT	#0

0x40855c HINT	#0

    (96) 0x408560 ADD	X8, X8, #1

    (96) 0x408564 CMP	X8, W12,SXTW

    (96) 0x408568 B.GE	4088a8

    (96) 0x40856c LDR	W10, [X14, X8,LSL #2]

    (96) 0x408570 CMP	W10, #1

    (96) 0x408574 B.LT	408560

  (98) 0x408578 UBFM	X11, X8, #58, #57

  (98) 0x40857c ORR	W10, WZR, WZR

  (98) 0x408580 ORR	W15, WZR, W12

  (98) 0x408584 ORR	W16, WZR, W12

  (98) 0x408588 ORR	W2, WZR, W12

  (98) 0x40858c B	4085b4

0x408590 HINT	#0

0x408594 HINT	#0

0x408598 HINT	#0

0x40859c HINT	#0

  (98) 0x4085a0 ADD	W10, W10, #1

  (98) 0x4085a4 LDR	X14, [X0, #120]

  (98) 0x4085a8 LDR	W13, [X14, X8,LSL #2]

  (98) 0x4085ac CMP	W10, W13

  (98) 0x4085b0 B.GE	408560

  (98) 0x4085b4 LDR	X17, [X1, #24]

  (98) 0x4085b8 ADD	X13, X11, W10,SXTW

  (98) 0x4085bc LDR	D1, [X0, #48]

  (98) 0x4085c0 MADD	X18, X13, X9, X17

  (98) 0x4085c4 LDR	D0, [X18]

  (98) 0x4085c8 FCMP	D0, D1

  (98) 0x4085cc B.PL	408600

  (98) 0x4085d0 LDR	D1, [X0, #24]

  (98) 0x4085d4 LDR	W4, [X0]

  (98) 0x4085d8 SUB	W5, W4, #1

  (98) 0x4085dc FSUB	D0, D0, S1

  (98) 0x4085e0 LDR	D1, [X0, #96]

  (98) 0x4085e4 FMUL	D0, D0, D1

  (98) 0x4085e8 FCVTMS	W3, D0

  (98) 0x4085ec CMP	W4, W3

  (98) 0x4085f0 CSEL	W3, W5, W3, #0

  (98) 0x4085f4 B	408608

0x4085f8 HINT	#0

0x4085fc HINT	#0

(97) 0x408600 LDR	W4, [X0]

(97) 0x408604 ORR	W3, WZR, W4

  (98) 0x408608 LDP	D0, D2, [X18, #8]

  (98) 0x40860c LDP	D1, D3, [X0, #32]

  (98) 0x408610 LDP	D4, D5, [X0, #104]

  (98) 0x408614 FSUB	D3, D2, S3

  (98) 0x408618 LDP	W5, W6, [X0, #4]

  (98) 0x40861c SUB	W20, W5, #1

  (98) 0x408620 SUB	W21, W6, #1

  (98) 0x408624 FSUB	D1, D0, S1

  (98) 0x408628 FMUL	D3, D3, D5

  (98) 0x40862c FMUL	D1, D1, D4

  (98) 0x408630 FCVTMS	W19, D3

  (98) 0x408634 FCVTMS	W7, D1

  (98) 0x408638 LDP	D1, D3, [X0, #56]

  (98) 0x40863c CMP	W5, W7

  (98) 0x408640 CSEL	W7, W20, W7, #0

  (98) 0x408644 FCMP	D0, D1

  (98) 0x408648 CSEL	W20, W5, W7, #5

  (98) 0x40864c CMP	W6, W19

  (98) 0x408650 CSEL	W19, W21, W19, #0

  (98) 0x408654 FCMP	D2, D3

  (98) 0x408658 B.MI	408680

  (98) 0x40865c UBFM	W15, W6, #31, #30

  (98) 0x408660 ADD	W2, W5, W20

  (98) 0x408664 ADD	W16, W4, #2

  (98) 0x408668 MADD	W15, W15, W5, W3

  (98) 0x40866c ADD	W2, W2, W6,LSL #1

  (98) 0x408670 ADD	W2, W2, #3

  (98) 0x408674 ADD	W15, W15, W12

  (98) 0x408678 MADD	W15, W16, W2, W15

  (98) 0x40867c B	40871c

  (98) 0x408680 CMN	W19, #1

  (98) 0x408684 B.EQ	408700

  (98) 0x408688 MADD	W20, W19, W5, W7

  (98) 0x40868c CMN	W3, #1

  (98) 0x408690 MADD	W21, W4, W20, W3

  (98) 0x408694 ADD	W20, W20, W2

  (98) 0x408698 CSEL	W20, W21, W20, #1

  (98) 0x40869c ADD	W21, W19, W6

  (98) 0x4086a0 CMP	W4, W3

  (98) 0x4086a4 ADD	W4, W4, #2

  (98) 0x4086a8 MADD	W22, W21, W5, W7

  (98) 0x4086ac CSEL	W2, W2, W16, #1

  (98) 0x4086b0 ADD	W22, W22, W16

  (98) 0x4086b4 CSEL	W20, W20, W22, #1

  (98) 0x4086b8 MADD	W22, W5, W6, WZR

  (98) 0x4086bc MADD	W5, W6, W5, WZR

  (98) 0x4086c0 CMN	W7, #1

  (98) 0x4086c4 CSEL	W16, W16, W15, #1

  (98) 0x4086c8 CSEL	W2, W2, W15, #1

  (98) 0x4086cc ADD	W22, W3, W22,LSL #1

  (98) 0x4086d0 ADD	W3, W3, W5,LSL #1

  (98) 0x4086d4 ADD	W22, W22, W15

  (98) 0x4086d8 ADD	W3, W3, W12

  (98) 0x4086dc MADD	W19, W4, W19, W22

  (98) 0x4086e0 MADD	W3, W4, W21, W3

  (98) 0x4086e4 CSINC	W7, W20, W19, #1

  (98) 0x4086e8 FCMP	D0, D1

  (98) 0x4086ec CSEL	W15, W15, W12, #4

  (98) 0x4086f0 CSEL	W16, W16, W12, #4

  (98) 0x4086f4 CSEL	W2, W2, W12, #4

  (98) 0x4086f8 CSINC	W3, W7, W3, #4

  (98) 0x4086fc B	40872c

  (98) 0x408700 UBFM	W15, W6, #31, #30

  (98) 0x408704 ADD	W16, W4, #2

  (98) 0x408708 ADD	W2, W20, W6,LSL #1

  (98) 0x40870c MADD	W15, W15, W5, W3

  (98) 0x408710 MADD	W16, W16, W2, W16

  (98) 0x408714 ADD	W15, W15, W12

  (98) 0x408718 ADD	W15, W15, W16

  (98) 0x40871c ADD	W3, W15, #1

  (98) 0x408720 ORR	W15, WZR, W12

  (98) 0x408724 ORR	W16, WZR, W12

  (98) 0x408728 ORR	W2, WZR, W12

  (98) 0x40872c TBNZ	W3, #31, 4088b8

  (98) 0x408730 LDR	W4, [X0, #20]

  (98) 0x408734 CMP	W3, W4

  (98) 0x408738 B.GE	4088d8

  (98) 0x40873c ORR	W4, WZR, W3

  (98) 0x408740 CMP	X8, X4

  (98) 0x408744 B.EQ	4085a0

  (98) 0x408748 LDR	W12, [X14, X4,LSL #2]

  (98) 0x40874c LDP	X14, X15, [X1, #8]

  (98) 0x408750 LDR	W16, [X14, X13,LSL #2]

  (98) 0x408754 ADD	W12, W12, W3,LSL #6

  (98) 0x408758 STR	W16, [X14, X12,SXTW #2]

  (98) 0x40875c SBFM	X14, X12, #0, #31

  (98) 0x408760 LDR	W16, [X15, X13,LSL #2]

  (98) 0x408764 ADD	X14, X14, W12,SXTW #1

  (98) 0x408768 STR	W16, [X15, X12,SXTW #2]

  (98) 0x40876c ADD	X15, X17, X14,LSL #3

  (98) 0x408770 ADD	X17, X13, X13,LSL #1

  (98) 0x408774 LDR	Q0, [X18]

  (98) 0x408778 LDR	X16, [X18, #16]

  (98) 0x40877c STR	X16, [X15, #16]

  (98) 0x408780 STR	Q0, [X15]

  (98) 0x408784 LDR	X15, [X1, #32]

  (98) 0x408788 ADD	X16, X15, X14,LSL #3

  (98) 0x40878c ADD	X15, X15, X17,LSL #3

  (98) 0x408790 LDR	Q0, [X15]

  (98) 0x408794 LDR	X15, [X15, #16]

  (98) 0x408798 STR	X15, [X16, #16]

  (98) 0x40879c STR	Q0, [X16]

  (98) 0x4087a0 LDR	X15, [X1, #40]

  (98) 0x4087a4 ADD	X14, X15, X14,LSL #3

  (98) 0x4087a8 ADD	X15, X15, X17,LSL #3

  (98) 0x4087ac LDR	Q0, [X15]

  (98) 0x4087b0 LDR	X15, [X15, #16]

  (98) 0x4087b4 STR	X15, [X14, #16]

  (98) 0x4087b8 STR	Q0, [X14]

  (98) 0x4087bc LDR	X14, [X1, #48]

  (98) 0x4087c0 LDR	X15, [X14, X13,LSL #3]

  (98) 0x4087c4 STR	X15, [X14, X12,SXTW #3]

  (98) 0x4087c8 LDR	X12, [X0, #120]

  (98) 0x4087cc LDR	W14, [X12, X4,LSL #2]

  (98) 0x4087d0 ADD	W15, W14, #1

  (98) 0x4087d4 STR	W15, [X12, X4,LSL #2]

  (98) 0x4087d8 CMP	W14, #63

  (98) 0x4087dc B.GE	4088f8

  (98) 0x4087e0 LDRSW	X14, [X12, X8,LSL #2]

  (98) 0x4087e4 SUB	X14, X14, #1

  (98) 0x4087e8 STR	W14, [X12, X8,LSL #2]

  (98) 0x4087ec CBZ	W14, 408870

  (98) 0x4087f0 ADD	X12, X11, X14

  (98) 0x4087f4 LDP	X14, X15, [X1, #8]

  (98) 0x4087f8 ADD	X17, X12, X12,LSL #1

  (98) 0x4087fc LDR	W16, [X14, X12,LSL #2]

  (98) 0x408800 STR	W16, [X14, X13,LSL #2]

  (98) 0x408804 LDR	W14, [X15, X12,LSL #2]

  (98) 0x408808 STR	W14, [X15, X13,LSL #2]

  (98) 0x40880c LDR	X14, [X1, #24]

  (98) 0x408810 ADD	X15, X13, X13,LSL #1

  (98) 0x408814 ADD	X16, X14, X15,LSL #3

  (98) 0x408818 ADD	X14, X14, X17,LSL #3

  (98) 0x40881c LDR	Q0, [X14]

  (98) 0x408820 LDR	X14, [X14, #16]

  (98) 0x408824 STR	X14, [X16, #16]

  (98) 0x408828 STR	Q0, [X16]

  (98) 0x40882c LDR	X14, [X1, #32]

  (98) 0x408830 ADD	X16, X14, X15,LSL #3

  (98) 0x408834 ADD	X14, X14, X17,LSL #3

  (98) 0x408838 LDR	Q0, [X14]

  (98) 0x40883c LDR	X14, [X14, #16]

  (98) 0x408840 STR	X14, [X16, #16]

  (98) 0x408844 STR	Q0, [X16]

  (98) 0x408848 LDR	X14, [X1, #40]

  (98) 0x40884c ADD	X15, X14, X15,LSL #3

  (98) 0x408850 ADD	X14, X14, X17,LSL #3

  (98) 0x408854 LDR	Q0, [X14]

  (98) 0x408858 LDR	X14, [X14, #16]

  (98) 0x40885c STR	X14, [X15, #16]

  (98) 0x408860 STR	Q0, [X15]

  (98) 0x408864 LDR	X14, [X1, #48]

  (98) 0x408868 LDR	X12, [X14, X12,LSL #3]

  (98) 0x40886c STR	X12, [X14, X13,LSL #3]

  (98) 0x408870 LDR	W12, [X0, #12]

  (98) 0x408874 CMP	W12, W3

  (98) 0x408878 B.GE	408888

  (98) 0x40887c LDR	W13, [X1]

  (98) 0x408880 SUB	W13, W13, #1

  (98) 0x408884 STR	W13, [X1]

  (98) 0x408888 ORR	W15, WZR, W12

  (98) 0x40888c ORR	W16, WZR, W12

  (98) 0x408890 ORR	W2, WZR, W12

  (98) 0x408894 LDR	X14, [X0, #120]

  (98) 0x408898 LDR	W13, [X14, X8,LSL #2]

  (98) 0x40889c CMP	W10, W13

  (98) 0x4088a0 B.LT	4085b4

  (98) 0x4088a4 B	408560

0x4088a8 LDP	X20, X19, [SP, #32]

0x4088ac LDP	X22, X21, [SP, #16]

0x4088b0 LDP	X29, X30, [SP], #48

0x4088b4 RET

0x4088b8 ADRP	X0,

0x4088bc ADD	X0, X0, #339

0x4088c0 ADRP	X1,

0x4088c4 ADD	X1, X1, #123

0x4088c8 ADRP	X3,

0x4088cc ADD	X3, X3, #349

0x4088d0 MOVZ	W2, #246

0x4088d4 BL	4021f0

0x4088d8 ADRP	X0,

0x4088dc ADD	X0, X0, #396

0x4088e0 ADRP	X1,

0x4088e4 ADD	X1, X1, #123

0x4088e8 ADRP	X3,

0x4088ec ADD	X3, X3, #349

0x4088f0 MOVZ	W2, #247

0x4088f4 BL	4021f0

0x4088f8 ADRP	X0,

0x4088fc ADD	X0, X0, #422

0x408900 ADRP	X1,

0x408904 ADD	X1, X1, #123

0x408908 ADRP	X3,

0x40890c ADD	X3, X3, #453

0x408910 MOVZ	W2, #262

0x408914 BL	4021f0

0x408918 HINT	#0

0x40891c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.20+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:209-385
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-108-7908/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:209-247,258-269,288-304,327-334,352-365,371,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.63 to 4.73 cycles (1.19x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.63 to 1.50 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	3.50	3.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	5.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.63 cycles. At this rate:

14% of peak load performance is reached (13.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 408500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W12, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 408540 <updateLinkCells+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X8, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4088a8 <updateLinkCells+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W9, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 40856c <updateLinkCells+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <40d8b8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #339	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40d8c0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X1, X1, #123	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X3, <40d8c8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #349	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #246	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4021f0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <40d8d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #396	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40d8e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X1, X1, #123	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X3, <40d8e8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #349	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #247	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4021f0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <40d8f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #422	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40d900>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X1, X1, #123	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X3, <40d908>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #453	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #262	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4021f0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:209-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.63 to 1.50 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	3.50	3.50	5.17	5.17	5.17	5.17	5.17	5.17	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	5.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.63 cycles. At this rate:

14% of peak load performance is reached (13.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.53 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 408500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W8, [X0, #20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W12, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 408540 <updateLinkCells+0x40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X8, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR W12, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4088a8 <updateLinkCells+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W9, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 40856c <updateLinkCells+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <40d8b8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #339	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40d8c0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X1, X1, #123	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X3, <40d8c8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #349	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #246	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4021f0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <40d8d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #396	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40d8e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X1, X1, #123	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X3, <40d8e8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #349	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #247	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4021f0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <40d8f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #422	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <40d900>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X1, X1, #123	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X3, <40d908>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X3, #453	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #262	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4021f0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.23	0.03
▼Loop 97 - linkCells.c:209-371 - exec–	0.00	0.00
▼Loop 98 - linkCells.c:209-371 - exec–	0.22	2.46
○Loop 96 - linkCells.c:291-295 - exec	0.00	0.02
○Loop 99 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code