	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/run/oneview_runs/multicore/aocc_2/oneview_results_1786636259 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: -> OPEN THE MAIN APPLICATION BINARY ...
[MAQAO] Info: ---> ALL LOOPS HAVE BEEN ANALYZED
[MAQAO] Info: ---> ALL FUNCTIONS HAVE BEEN ANALYZED
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/run/oneview_runs/multicore/aocc_2/oneview_results_1786636259


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/run/binaries/aocc_2/exec
  Timestamp:			2026-08-13 17:50:59
  Universal Timestamp:		1786636259
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			isix07.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		GRANITE_RAPIDS
  Model Name:			Intel(R) Xeon(R) 6972P
  Cache Size:			491520 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.31.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Sat Aug 1 05:38:01 EDT 2026
  Compilation Options:		
		exec: AMD clang version 17.0.6 (CLANG: AOCC_5.1.0-Build#1994 2025_12_23) /cluster/comp/aocc/5.1.0/bin/clang-17 -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp -I /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/aocc_2 -O3 -D DO_MPI -O3 -march=graniterapids -mprefer-vector-width=512 -ffast-math -g -fno-omit-frame-pointer -fcf-protection=none -nopie -grecord-command-line -fopenmp=libomp -MD -MT CMakeFiles/CoMD-openmp-mpi.dir/CoMD/src-openmp/ljForce.c.o -MF CMakeFiles/CoMD-openmp-mpi.dir/CoMD/src-openmp/ljForce.c.o.d -o CMakeFiles/CoMD-openmp-mpi.dir/CoMD/src-openmp/ljForce.c.o -c /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c -I /cluster/hpcx/2.23/ompi5-aocc-mt/include -I /cluster/hpcx/2.23/ompi5-aocc-mt/include/openmpi 
  Number of processes observed:	1
  Number of threads observed:	5
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				97.61 s
  Max (Thread Active Time):		97.23 s
  Average Active Time:			97.03 s
  Activity Ratio:			99.7 %
  Average number of active threads:	4.970
  Affinity Stability:			99.9 %
  Time spent in analyzed loops:		86.1 %
  Time spent in analyzed innermost loops: 84.8 %
  Time spent in user code:		86.8 %
  Compilation Options Score:		100
  Array Access Efficiency:		95.9 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		2.99
  Perfect OpenMP/MPI/Pthread/TBB:	1.05
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.14
  If No Scalar Integer:
      Potential Speedup:		1.01
      Nb Loops to get 80%:		2
  If FP Vectorized:
      Potential Speedup:		1.84
      Nb Loops to get 80%:		1
  If Fully Vectorized:
      Potential Speedup:		3.23
      Nb Loops to get 80%:		1
  If Only FP Arithmetic:
      Potential Speedup:		1.04
      Nb Loops to get 80%:		5




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 5      | 11     | 15     | 21     | 
      Cumulated Speedup | 1.0079 | 1.0119 | 1.0123 | 1.0123 | 1.0123 | 
  Top 5 loops:
    exec - 95:	1.0079
    exec - 100:	1.0108
    exec - 48:	1.0113
    exec - 65:	1.0117
    exec - 49:	1.0119

  If FP Vectorized:
      Number of loops   | 1      | 5      | 11     | 15     | 21     | 
      Cumulated Speedup | 1.8018 | 1.8358 | 1.8368 | 1.8368 | 1.8368 | 
  Top 5 loops:
    exec - 106:	1.8018
    exec - 95:	1.8324
    exec - 116:	1.8346
    exec - 111:	1.8353
    exec - 114:	1.8358

  If Fully Vectorized:
      Number of loops   | 1      | 5      | 11     | 15     | 21     | 
      Cumulated Speedup | 2.8661 | 3.1703 | 3.2252 | 3.2312 | 3.2339 | 
  Top 5 loops:
    exec - 106:	2.8661
    exec - 95:	2.9912
    exec - 105:	3.0627
    exec - 100:	3.1345
    exec - 104:	3.1703

  If Only FP Arithmetic:
      Number of loops   | 1      | 5      | 11     | 15     | 21     | 
      Cumulated Speedup | 1.0098 | 1.0322 | 1.0375 | 1.0380 | 1.0381 | 
  Top 5 loops:
    exec - 95:	1.0098
    exec - 65:	1.0184
    exec - 105:	1.0243
    exec - 113:	1.0292
    exec - 100:	1.0322



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (97.23 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9993228553754 / 3] Most of time spent in analyzed modules (99.98%) comes from functions compiled with architecture specialization option
-march=graniterapids


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.33 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (86.11%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 99.40% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.75% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (80.03%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (84.76%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.88%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [0 / 3] Too many functions do not use all threads
Functions running on a reduced number of threads (typically sequential code) cover at least 10% of application
walltime (26.56%). Check both "Max Inclusive Time Over Threads" and "Nb Threads" in Functions or Loops tabs and
consider parallelizing sequential regions or improving parallelization of regions running on a reduced number of
threads

  [3 / 3] Cumulative Outermost/In between loops coverage (1.36%) lower than cumulative innermost loop coverage (84.76%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.01%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 106 :
     analysis: Execution Time: 80 % - Vectorization Ratio: 35.68 % - Vector Length Use: 16.96 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 3
        [3] [SA] Several paths (3 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 3 issues ( = paths) costing 1 point each.
     Data Access Issues: 4
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
        [2] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 2 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 5
        [3] [SA] Several paths (3 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 3 issues ( = paths) costing 1 point each.
        [2] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 1 issues ( = data accesses) costing 2 point
            each.
     Inefficient Vectorization: 2
        [2] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM, BROADCAST) - Simplify data
            access and try to get stride 1 access. There are 2 issues (= instructions) costing 1 point each.

   + exec - 95  :
     analysis: Execution Time: 1 % - Vectorization Ratio: 17.39 % - Vector Length Use: 12.23 %
     Loop Computation Issues: 6
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Control Flow Issues: 394
        [394] [SA] Too many paths (390 paths) - Simplify control structure. There are 390 issues ( = paths) costing 1
            point each with a malus of 4 points.
     Vectorization Roadblocks: 394
        [394] [SA] Too many paths (390 paths) - Simplify control structure. There are 390 issues ( = paths) costing 1
            point each with a malus of 4 points.

   + exec - 105 :
     analysis: Execution Time: 0 % - Vectorization Ratio: 0.00 % - Vector Length Use: 12.50 %
     Control Flow Issues: 5
        [3] [SA] Several paths (3 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 3 issues ( = paths) costing 1 point each.
        [2] [SA] Non innermost loop (InBetween) - Collapse loop with innermost ones. This issue costs 2 points.
     Data Access Issues: 2
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 5
        [3] [SA] Several paths (3 paths) - Simplify control structure or force the compiler to use masked
            instructions. There are 3 issues ( = paths) costing 1 point each.
        [2] [SA] Non innermost loop (InBetween) - Collapse loop with innermost ones. This issue costs 2 points.

   + exec - 65  :
     analysis: Execution Time: 0 % - Vectorization Ratio: 100.00 % - Vector Length Use: 94.59 %
     Data Access Issues: 52
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [12] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM) - Simplify data access and
            try to get stride 1 access. There are 12 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 8
        [8] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 2 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 44
        [32] [SA] Presence of expensive instructions (GATHER/SCATTER) - Use array restructuring. There are 8 issues (=
            instructions) costing 4 points each.
        [12] [SA] Presence of special instructions executing on a single port (SHUFFLE/PERM) - Simplify data access and
            try to get stride 1 access. There are 12 issues (= instructions) costing 1 point each.

   + exec - 100 :
     analysis: Execution Time: 0 % - Vectorization Ratio: 33.33 % - Vector Length Use: 12.50 %
     Loop Computation Issues: 2
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 86.78  | 0.66    | 0.33    | 0.00   | 0.14   | 0.01  | 0.00  | 12.07 | 0.00    | 0.01  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 90.21                     | 90.21                     |
   4% to 8%                   | 0                         | 0.00                      | 90.21                     |
   2% to 4%                   | 1                         | 2.26                      | 92.47                     |
   1% to 2%                   | 2                         | 2.68                      | 95.15                     |
   0.5% to 1%                 | 4                         | 2.95                      | 98.10                     |
   0.25% to 0.5%              | 3                         | 1.08                      | 99.18                     |
   0.125% to 0.25%            | 2                         | 0.32                      | 99.50                     |
   < 0.125%                   | 21                        | 0.46                      | 99.96                     |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 1                         | 80.03                     | 80.03                     |
   4% to 8%                   | 0                         | 0.00                      | 80.03                     |
   2% to 4%                   | 0                         | 0.00                      | 80.03                     |
   1% to 2%                   | 1                         | 1.59                      | 81.62                     |
   0.5% to 1%                 | 3                         | 2.23                      | 83.84                     |
   0.25% to 0.5%              | 1                         | 0.41                      | 84.26                     |
   0.125% to 0.25%            | 1                         | 0.17                      | 84.43                     |
   < 0.125%                   | 12                        | 0.33                      | 84.76                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   ljForce.omp_outlined.5                                 | exec                | 81.33          | 78.91          |
   __kmp_hyper_barrier_release(barrier_type, kmp_info*... | libomp.so           | 8.89           | 10.78          |
   __kmp_hardware_timestamp                               | libomp.so           | 2.26           | 2.19           |
   updateLinkCells                                        | exec                | 1.60           | 7.78           |
   sortAtomsInCell                                        | exec                | 1.08           | 1.04           |
   __kmp_hyper_barrier_gather(barrier_type, kmp_info*,... | libomp.so           | 0.91           | 1.47           |
   ljForce.omp_outlined                                   | exec                | 0.85           | 0.83           |
   advanceVelocity.omp_outlined                           | exec                | 0.59           | 0.58           |
   unknown_kernel_region                                  | kernel              | 0.59           | 0.57           |
   advancePosition.omp_outlined                           | exec                | 0.42           | 0.41           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   106            | exec                | ljForce.c:191-191,ljForce.c:197-216                    | 80.03          |
   95             | exec                | linkCells.c:211-247,linkCells.c:258-269,linkCells.c... | 1.59           |
   105            | exec                | ljForce.c:187-187                                      | 0.89           |
   65             | exec                | haloExchange.c:621-630                                 | 0.87           |
   100            | exec                | mytype.h:23-23,ljForce.c:158-161                       | 0.85           |
   113            | exec                | timestep.c:76-78                                       | 0.51           |
   116            | exec                | timestep.c:88-94                                       | 0.41           |
   104            | exec                | ljForce.c:178-184,ljForce.c:187-187                    | 0.39           |
   48             | exec                | haloExchange.c:380-389                                 | 0.17           |
   64             | exec                | haloExchange.c:633-642                                 | 0.08           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 106 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:191,197-216.

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (2.67 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 18% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.48 cycles (6.22x speedup).

Details
44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 50% of SSE/AVX loads are used in vector version.
 - 33% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.1.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.1.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 5: addition or subtraction (1 inside FMA instructions)
 - 3: multiply (1 inside FMA instructions)
The binary loop is loading 48 bytes (6 double precision FP elements).


      6.1.1.1.6  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.


      6.1.1.1.7  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)




      6.1.1.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

9% of peak computational performance is used (3.00 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.2.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 15% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 10.00 to 2.00 cycles (5.00x speedup).

Details
22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 27% of SSE/AVX loads are used in vector version.
 - 33% of SSE/AVX stores are used in vector version.
 - 16% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 11% of SSE/AVX multiply instructions are used in vector version.
 - 20% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 0% of SSE/AVX divide and square root instructions are used in vector version.
 - 40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.2.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 9.50 cycles (1.05x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.1.2.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 6 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.11x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.2.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VUCOMISD: 1 occurrences<<list_path_2_complex_1>>



      6.1.1.2.5  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.1.2.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

20 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.1.2.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 30 FP arithmetical operations:
 - 13: addition or subtraction (6 inside FMA instructions)
 - 16: multiply (6 inside FMA instructions)
 - 1: divide
The binary loop is loading 128 bytes (16 double precision FP elements).
The binary loop is storing 32 bytes (4 double precision FP elements).


      6.1.1.2.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.




      6.1.1.3  -  Path 3
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (2.67 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.3.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 17% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.50 cycles (6.00x speedup).

Details
40% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 40% of SSE/AVX loads are used in vector version.
 - 33% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.3.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.83 cycles (1.06x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.1.3.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.3.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VUCOMISD: 1 occurrences<<list_path_3_complex_1>>



      6.1.1.3.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.1.3.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 5: addition or subtraction (1 inside FMA instructions)
 - 3: multiply (1 inside FMA instructions)
The binary loop is loading 56 bytes (7 double precision FP elements).


      6.1.1.3.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.


      6.1.1.3.8  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.2  -  Loop 95 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,258-269,295-301,327-334,352,359-365,371-373.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:
 - Ignoring paths for analysis
 - Too many paths. If you really need to analyze all of the 390 paths individually, rerun with max-paths=390
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 390 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.17 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 34.67 to 17.50 cycles (1.98x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 12% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 34.67 to 2.89 cycles (11.98x speedup).

Details
17% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 27% of SSE/AVX loads are used in vector version.
 - 27% of SSE/AVX stores are used in vector version.
 - 0% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 0% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.2.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).





      6.1.2.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - DEC: 1 occurrences<<list_path_1_complex_1>>
 - VCVTTSD2SI: 3 occurrences<<list_path_1_complex_2>>
 - VROUNDSD: 3 occurrences<<list_path_1_complex_3>>
 - VUCOMISD: 2 occurrences<<list_path_1_complex_4>>



      6.1.2.1.6  -  Conversion instructions
  ----------------------------------------------------------------------------------------------------------

Detected expensive conversion instructions.

Details
 - VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences<<list_path_1_cvt_1>>


Workaround
Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.


      6.1.2.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.2.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 6 FP arithmetical operations:
 - 3: addition or subtraction
 - 3: multiply
The binary loop is loading 472 bytes (59 double precision FP elements).
The binary loop is storing 196 bytes (24 double precision FP elements).


      6.1.2.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.


      6.1.2.1.10  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.3  -  Loop 105 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

Warnings:
This path is accessible from 3 CFG paths (including child blocks)

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
By vectorizing your loop, you can lower the cost of an iteration from 1.33 to 0.17 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.3.1.3  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.3.1.4  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 16 bytes.







      6.1.4  -  Loop 65 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-630.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 94% register length (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 33.33 to 31.97 cycles (1.04x speedup).

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.4.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.4.1.3  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VPSCATTERQD: 2 occurrences<<list_path_1_complex_1>>
 - VSCATTERQPD: 6 occurrences<<list_path_1_complex_2>>



      6.1.4.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.4.1.5  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 33.33 to 12.50 cycles (2.67x speedup).

Details
 - VPSCATTERQD: 2 occurrences<<list_path_1_gather_scatter_1>>
 - VSCATTERQPD: 6 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.4.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------




      6.1.4.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 448 bytes.
The binary loop is storing 512 bytes.







      6.1.5  -  Loop 100 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:158-161


The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 12% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.19 cycles (8.00x speedup).

Details
33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 33% of SSE/AVX stores are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).


Workaround
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop
  * use the 'restrict' C99 keyword




No data for this section



      6.1.5.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.5.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is storing 32 bytes.


      6.1.5.1.6  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop body is too small to efficiently use resources.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.6  -  Loop 113 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76-78.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (2.67 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
97% of vector register length is used (average across all SSE/AVX instructions).


Details
97% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 85% of SSE/AVX loads are used in vector version.
 - 96% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 18.00 to 6.50 cycles (2.77x speedup).


Workaround
Reduce the number of FP multiply/FMA instructions




      6.1.6.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.




      6.1.6.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.6.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 48 FP arithmetical operations:
 - 24: addition or subtraction (all inside FMA instructions)
 - 24: multiply (all inside FMA instructions)
The binary loop is loading 392 bytes (49 double precision FP elements).
The binary loop is storing 192 bytes (24 double precision FP elements).


      6.1.6.1.6  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.7  -  Loop 116 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

7% of peak computational performance is used (2.50 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 2.00 cycles (2.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.7.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.67 cycles (1.09x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.7.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 3.50 cycles (1.14x speedup).


      6.1.7.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 3 FMA (fused multiply-add) operations.




      6.1.7.1.5  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.7.1.6  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 10 FP arithmetical operations:
 - 3: addition or subtraction (all inside FMA instructions)
 - 6: multiply (3 inside FMA instructions)
 - 1: divide
The binary loop is loading 84 bytes (10 double precision FP elements).
The binary loop is storing 24 bytes (3 double precision FP elements).


      6.1.7.1.7  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.


      6.1.7.1.8  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.8  -  Loop 104 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 10% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.15 cycles (13.71x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.8.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.8.1.3  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.8.1.4  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 40 bytes.
The binary loop is storing 8 bytes.




      6.1.8.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

Warnings:
This path is accessible from 3 CFG paths (including child blocks)

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.2.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 10% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.30 cycles (13.79x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.8.2.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.8.2.3  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.8.2.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.


      6.1.8.2.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 72 bytes.
The binary loop is storing 16 bytes.







      6.1.9  -  Loop 48 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:380-389.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (0.69 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 4.33 to 3.17 cycles (1.37x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 11% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 4.33 to 0.44 cycles (9.90x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.9.1.4  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.1.5  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 3 FP arithmetical operations:
 - 3: addition or subtraction
The binary loop is loading 60 bytes (7 double precision FP elements).
The binary loop is storing 56 bytes (7 double precision FP elements).


      6.1.9.1.6  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.


      6.1.9.1.7  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)







      6.1.10  -  Loop 64 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:633-642.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

0% of peak computational performance is used (0.00 out of 64.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is vectorized, but using 82% register length (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 28.00 to 26.00 cycles (1.08x speedup).

Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Pass to your compiler a micro-architecture specialization option:
  * use march=native
 - Use vector aligned instructions:
  1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
  2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.



      6.1.10.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.



No data for this section



      6.1.10.1.3  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VGATHERQPD: 6 occurrences<<list_path_1_complex_1>>
 - VPGATHERQD: 2 occurrences<<list_path_1_complex_2>>



      6.1.10.1.4  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 2 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.10.1.5  -  Gather/scatter instructions
  ----------------------------------------------------------------------------------------------------------

Detected gather/scatter instructions (typically caused by indirect accesses). By removing them, you can lower the cost of an iteration from 28.00 to 12.50 cycles (2.24x speedup).

Details
 - VGATHERQPD: 6 occurrences<<list_path_1_gather_scatter_1>>
 - VPGATHERQD: 2 occurrences<<list_path_1_gather_scatter_2>>


Workaround
Try to simplify your code and/or replace indirect accesses with unit-stride ones.


      6.1.10.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------




      6.1.10.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop does not contain any FP arithmetical operations.
The binary loop is loading 448 bytes.
The binary loop is storing 448 bytes.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-663-3083/intel/CoMD/run/oneview_runs/multicore/aocc_2/oneview_run_1786636259"
[MAQAO] Info: 
