OV - exec - Loop 85

0x40b1f0 INC	%R10

0x40b1f3 CMP	$0x1b,%R10

0x40b1f7 JE	40b1a0

0x40b1f9 MOVSXD	(%R8,%R10,4),%RAX

0x40b1fd TEST	%RAX,%RAX

0x40b200 JS	40b404

0x40b206 MOV	-0x60(%RBP),%RCX

0x40b20a MOV	(%RCX,%RAX,4),%ECX

0x40b20d TEST	%ECX,%ECX

0x40b20f JLE	40b1f0

0x40b211 SAL	$0x6,%EAX

0x40b214 MOV	-0x58(%RBP),%RDX

0x40b218 MOV	0x20(%RDX),%R11

0x40b21c MOV	0x18(%R11),%R14

0x40b220 DEC	%ECX

0x40b222 LEA	(%RCX,%RCX,2),%RCX

0x40b226 LEA	0x18(,%RCX,8),%R12

0x40b22e LEA	(%RAX,%RAX,2),%RAX

0x40b232 LEA	0x10(%R14,%RAX,8),%R13

0x40b237 XOR	%EBX,%EBX

0x40b239 JMP	40b24c

  (86) 0x40b240 LEA	0x1(%RBX),%RAX

  (86) 0x40b244 CMP	%R9,%RBX

  (86) 0x40b247 MOV	%RAX,%RBX

  (86) 0x40b24a JE	40b1f0

  (86) 0x40b24c LEA	(%RBX,%RDI,1),%RSI

  (86) 0x40b250 LEA	(%RSI,%RSI,2),%RCX

  (86) 0x40b254 LEA	(%R14,%RCX,8),%RAX

  (86) 0x40b258 XOR	%R15D,%R15D

  (86) 0x40b25b JMP	40b269

    (87) 0x40b260 ADD	$0x18,%R15

    (87) 0x40b264 CMP	%R15,%R12

    (87) 0x40b267 JE	40b240

    (87) 0x40b269 VMOVUPD	(%RAX),%XMM11

    (87) 0x40b26d VSUBPD	-0x10(%R13,%R15,1),%XMM11,%XMM11

    (87) 0x40b274 VMULPD	%XMM11,%XMM11,%XMM12

    (87) 0x40b279 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

    (87) 0x40b27f VADDSD	%XMM12,%XMM13,%XMM13

    (87) 0x40b284 VMOVSD	0x10(%RAX),%XMM12

    (87) 0x40b289 VSUBSD	(%R13,%R15,1),%XMM12,%XMM12

    (87) 0x40b290 VFMADD231SD	%XMM12,%XMM12,%XMM13

    (87) 0x40b295 VUCOMISD	%XMM13,%XMM2

    (87) 0x40b29a JB	40b260

    (87) 0x40b29c VUCOMISD	%XMM4,%XMM13

    (87) 0x40b2a0 JBE	40b260

    (87) 0x40b2a2 VDIVSD	%XMM13,%XMM6,%XMM13

    (87) 0x40b2a7 VMULSD	%XMM13,%XMM13,%XMM14

    (87) 0x40b2ac VMULSD	%XMM1,%XMM13,%XMM15

    (87) 0x40b2b0 VMULSD	%XMM15,%XMM14,%XMM14

    (87) 0x40b2b5 VADDSD	%XMM7,%XMM14,%XMM15

    (87) 0x40b2b9 VFNMADD213SD	%XMM0,%XMM14,%XMM15

    (87) 0x40b2be VMULSD	%XMM8,%XMM15,%XMM15

    (87) 0x40b2c3 MOV	0x30(%R11),%RDX

    (87) 0x40b2c7 VADDSD	(%RDX,%RSI,8),%XMM15,%XMM16

    (87) 0x40b2ce VMOVSD	%XMM16,(%RDX,%RSI,8)

    (87) 0x40b2d5 VMOVAPD	%XMM9,%XMM16

    (87) 0x40b2db VFMADD213SD	%XMM10,%XMM14,%XMM16

    (87) 0x40b2e1 VMULSD	%XMM3,%XMM13,%XMM13

    (87) 0x40b2e5 VMULSD	%XMM14,%XMM13,%XMM13

    (87) 0x40b2ea VMULSD	%XMM16,%XMM13,%XMM13

    (87) 0x40b2f0 MOV	0x28(%R11),%RDX

    (87) 0x40b2f4 VMOVDDUP	%XMM13,%XMM14

    (87) 0x40b2f9 VFMADD213PD	(%RDX,%RCX,8),%XMM14,%XMM11

    (87) 0x40b2ff VMOVUPD	%XMM11,(%RDX,%RCX,8)

    (87) 0x40b304 VFMADD213SD	0x10(%RDX,%RCX,8),%XMM13,%XMM12

    (87) 0x40b30b VMOVSD	%XMM12,0x10(%RDX,%RCX,8)

    (87) 0x40b311 VADDSD	%XMM5,%XMM15,%XMM5

    (87) 0x40b315 JMP	40b260

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.24
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks
Function	ljForce.extracted
Source	ljForce.c:178-184,ljForce.c:191-191,ljForce.c:197-197
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.23
Front-end cycles	3.00
P0 cycles	1.88
P1 cycles	1.55
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	0.00
P5 cycles	1.35
P6 cycles	1.88
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.35
P11 cycles	1.75
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.25
Nb uops	18.00
Nb loads	5.25
Nb stores	0.00
Nb stack references	1.75
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.24
Bytes prefetched	0.00
Bytes loaded	34.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.16
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.16

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue, P0, P6,
Function	ljForce.extracted
Source	ljForce.c:178-184,ljForce.c:191-191,ljForce.c:197-197
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.19
Front-end cycles	1.50
P0 cycles	1.50
P1 cycles	0.80
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.00
P5 cycles	0.60
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.60
P11 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	9.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:178-184,ljForce.c:191-191,ljForce.c:197-197
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.24
Front-end cycles	3.50
P0 cycles	2.00
P1 cycles	1.80
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	1.60
P6 cycles	2.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.60
P11 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	6.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.43
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.extracted
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,191,197.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.23 cycles (13.24x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 34 bytes.

General properties

nb instructions	18.25
nb uops	18
loop length	64.50
used x86 registers	9.50
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1.75

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.88	1.55	1.75	1.75	0.00	1.35	1.88	0.00	0.00	0.00	1.35	1.75
cycles	1.88	1.55	1.75	1.75	0.00	1.35	1.88	0.00	0.00	0.00	1.35	1.75

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.00
Dispatch	1.88
Data deps.	0.00
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

5% of peak load performance is reached (11.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	ljForce.extracted
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,191,197.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.19 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	10
nb uops	9
loop length	33
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	0.80	1.00	1.00	0.00	0.60	1.50	0.00	0.00	0.00	0.60	1.00
cycles	1.50	0.80	1.00	1.00	0.00	0.60	1.50	0.00	0.00	0.00	0.60	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.50
Dispatch	1.50
Data deps.	0.00
Overall L1	1.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

5% of peak load performance is reached (10.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.50 to 1.00 cycles (1.50x speedup).

ASM code

In the binary file, the address of the loop is: 40b1f9

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
INC %R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1b,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JE 40b1a0 <ljForce.extracted+0x170>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOVSXD (%R8,%R10,4),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (12.5%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,4),%ECX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	N/A
JLE 40b1f0 <ljForce.extracted+0x1c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	ljForce.extracted
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,191,197.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.24 cycles (14.61x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	21
nb uops	21
loop length	75
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.80	2.00	2.00	0.00	1.60	2.00	0.00	0.00	0.00	1.60	2.00
cycles	2.00	1.80	2.00	2.00	0.00	1.60	2.00	0.00	0.00	0.00	1.60	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.50
Dispatch	2.00
Data deps.	0.00
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

5% of peak load performance is reached (11.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.00 cycles (1.75x speedup).

ASM code

In the binary file, the address of the loop is: 40b1f9

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
INC %R10	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1b,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JE 40b1a0 <ljForce.extracted+0x170>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOVSXD (%R8,%R10,4),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (12.5%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RCX,%RAX,4),%ECX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (6.3%)
JLE 40b1f0 <ljForce.extracted+0x1c0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
SAL $0x6,%EAX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDX),%R11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%R11),%R14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
DEC %ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA (%RCX,%RCX,2),%RCX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(,%RCX,8),%R12	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(%R14,%RAX,8),%R13	1	0	1	0	0	0	0	0	0	3	1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 40b24c <ljForce.extracted+0x21c>	1	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code