OV - exec - Loop 84

	Loop Id: 84	Module: exec	Source: ljForce.c:172-222 [...]	Coverage: 0.01%

0x40b1a0 MOV	-0x78(%RBP),%RCX

0x40b1a4 INC	%RCX

0x40b1a7 ADD	$0x40,%EDI

0x40b1aa CMP	-0x50(%RBP),%RCX

0x40b1ae JE	40b0b0

0x40b1b4 MOV	%EDI,%EDI

0x40b1b6 MOV	-0x60(%RBP),%RAX

0x40b1ba MOV	(%RAX,%RCX,4),%EAX

0x40b1bd MOV	-0x70(%RBP),%RDX

0x40b1c1 MOV	(%RDX,%RCX,8),%R8

0x40b1c5 TEST	%EAX,%EAX

0x40b1c7 MOV	%RCX,-0x78(%RBP)

0x40b1cb JLE	40b320

0x40b1d1 SAL	$0x6,%ECX

0x40b1d4 ADD	%ECX,%EAX

0x40b1d6 LEA	0x1(%RDI),%ECX

0x40b1d9 CMP	%ECX,%EAX

0x40b1db CMOVLE	%ECX,%EAX

0x40b1de MOV	%EDI,%R9D

0x40b1e1 NOT	%R9D

0x40b1e4 ADD	%EAX,%R9D

0x40b1e7 XOR	%R10D,%R10D

0x40b1ea JMP	40b1f9

  (85) 0x40b1f0 INC	%R10

  (85) 0x40b1f3 CMP	$0x1b,%R10

  (85) 0x40b1f7 JE	40b1a0

  (85) 0x40b1f9 MOVSXD	(%R8,%R10,4),%RAX

  (85) 0x40b1fd TEST	%RAX,%RAX

  (85) 0x40b200 JS	40b404

  (85) 0x40b206 MOV	-0x60(%RBP),%RCX

  (85) 0x40b20a MOV	(%RCX,%RAX,4),%ECX

  (85) 0x40b20d TEST	%ECX,%ECX

  (85) 0x40b20f JLE	40b1f0

  (85) 0x40b211 SAL	$0x6,%EAX

  (85) 0x40b214 MOV	-0x58(%RBP),%RDX

  (85) 0x40b218 MOV	0x20(%RDX),%R11

  (85) 0x40b21c MOV	0x18(%R11),%R14

  (85) 0x40b220 DEC	%ECX

  (85) 0x40b222 LEA	(%RCX,%RCX,2),%RCX

  (85) 0x40b226 LEA	0x18(,%RCX,8),%R12

  (85) 0x40b22e LEA	(%RAX,%RAX,2),%RAX

  (85) 0x40b232 LEA	0x10(%R14,%RAX,8),%R13

  (85) 0x40b237 XOR	%EBX,%EBX

  (85) 0x40b239 JMP	40b24c

    (86) 0x40b240 LEA	0x1(%RBX),%RAX

    (86) 0x40b244 CMP	%R9,%RBX

    (86) 0x40b247 MOV	%RAX,%RBX

    (86) 0x40b24a JE	40b1f0

    (86) 0x40b24c LEA	(%RBX,%RDI,1),%RSI

    (86) 0x40b250 LEA	(%RSI,%RSI,2),%RCX

    (86) 0x40b254 LEA	(%R14,%RCX,8),%RAX

    (86) 0x40b258 XOR	%R15D,%R15D

    (86) 0x40b25b JMP	40b269

      (87) 0x40b260 ADD	$0x18,%R15

      (87) 0x40b264 CMP	%R15,%R12

      (87) 0x40b267 JE	40b240

      (87) 0x40b269 VMOVUPD	(%RAX),%XMM11

      (87) 0x40b26d VSUBPD	-0x10(%R13,%R15,1),%XMM11,%XMM11

      (87) 0x40b274 VMULPD	%XMM11,%XMM11,%XMM12

      (87) 0x40b279 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

      (87) 0x40b27f VADDSD	%XMM12,%XMM13,%XMM13

      (87) 0x40b284 VMOVSD	0x10(%RAX),%XMM12

      (87) 0x40b289 VSUBSD	(%R13,%R15,1),%XMM12,%XMM12

      (87) 0x40b290 VFMADD231SD	%XMM12,%XMM12,%XMM13

      (87) 0x40b295 VUCOMISD	%XMM13,%XMM2

      (87) 0x40b29a JB	40b260

      (87) 0x40b29c VUCOMISD	%XMM4,%XMM13

      (87) 0x40b2a0 JBE	40b260

      (87) 0x40b2a2 VDIVSD	%XMM13,%XMM6,%XMM13

      (87) 0x40b2a7 VMULSD	%XMM13,%XMM13,%XMM14

      (87) 0x40b2ac VMULSD	%XMM1,%XMM13,%XMM15

      (87) 0x40b2b0 VMULSD	%XMM15,%XMM14,%XMM14

      (87) 0x40b2b5 VADDSD	%XMM7,%XMM14,%XMM15

      (87) 0x40b2b9 VFNMADD213SD	%XMM0,%XMM14,%XMM15

      (87) 0x40b2be VMULSD	%XMM8,%XMM15,%XMM15

      (87) 0x40b2c3 MOV	0x30(%R11),%RDX

      (87) 0x40b2c7 VADDSD	(%RDX,%RSI,8),%XMM15,%XMM16

      (87) 0x40b2ce VMOVSD	%XMM16,(%RDX,%RSI,8)

      (87) 0x40b2d5 VMOVAPD	%XMM9,%XMM16

      (87) 0x40b2db VFMADD213SD	%XMM10,%XMM14,%XMM16

      (87) 0x40b2e1 VMULSD	%XMM3,%XMM13,%XMM13

      (87) 0x40b2e5 VMULSD	%XMM14,%XMM13,%XMM13

      (87) 0x40b2ea VMULSD	%XMM16,%XMM13,%XMM13

      (87) 0x40b2f0 MOV	0x28(%R11),%RDX

      (87) 0x40b2f4 VMOVDDUP	%XMM13,%XMM14

      (87) 0x40b2f9 VFMADD213PD	(%RDX,%RCX,8),%XMM14,%XMM11

      (87) 0x40b2ff VMOVUPD	%XMM11,(%RDX,%RCX,8)

      (87) 0x40b304 VFMADD213SD	0x10(%RDX,%RCX,8),%XMM13,%XMM12

      (87) 0x40b30b VMOVSD	%XMM12,0x10(%RDX,%RCX,8)

      (87) 0x40b311 VADDSD	%XMM5,%XMM15,%XMM5

      (87) 0x40b315 JMP	40b260

0x40b320 CMPL	$0,(%R8)

0x40b324 JS	40b404

0x40b32a CMPL	$0,0x4(%R8)

0x40b32f JS	40b404

0x40b335 CMPL	$0,0x8(%R8)

0x40b33a JS	40b404

0x40b340 CMPL	$0,0xc(%R8)

0x40b345 JS	40b404

0x40b34b CMPL	$0,0x10(%R8)

0x40b350 JS	40b404

0x40b356 CMPL	$0,0x14(%R8)

0x40b35b JS	40b404

0x40b361 CMPL	$0,0x18(%R8)

0x40b366 JS	40b404

0x40b36c CMPL	$0,0x1c(%R8)

0x40b371 JS	40b404

0x40b377 CMPL	$0,0x20(%R8)

0x40b37c JS	40b404

0x40b382 CMPL	$0,0x24(%R8)

0x40b387 JS	40b404

0x40b389 CMPL	$0,0x28(%R8)

0x40b38e JS	40b404

0x40b390 CMPL	$0,0x2c(%R8)

0x40b395 JS	40b404

0x40b397 CMPL	$0,0x30(%R8)

0x40b39c JS	40b404

0x40b39e CMPL	$0,0x34(%R8)

0x40b3a3 JS	40b404

0x40b3a5 CMPL	$0,0x38(%R8)

0x40b3aa JS	40b404

0x40b3ac CMPL	$0,0x3c(%R8)

0x40b3b1 JS	40b404

0x40b3b3 CMPL	$0,0x40(%R8)

0x40b3b8 JS	40b404

0x40b3ba CMPL	$0,0x44(%R8)

0x40b3bf JS	40b404

0x40b3c1 CMPL	$0,0x48(%R8)

0x40b3c6 JS	40b404

0x40b3c8 CMPL	$0,0x4c(%R8)

0x40b3cd JS	40b404

0x40b3cf CMPL	$0,0x50(%R8)

0x40b3d4 JS	40b404

0x40b3d6 CMPL	$0,0x54(%R8)

0x40b3db JS	40b404

0x40b3dd CMPL	$0,0x58(%R8)

0x40b3e2 JS	40b404

0x40b3e4 CMPL	$0,0x5c(%R8)

0x40b3e9 JS	40b404

0x40b3eb CMPL	$0,0x60(%R8)

0x40b3f0 JS	40b404

0x40b3f2 CMPL	$0,0x64(%R8)

0x40b3f7 JS	40b404

0x40b3f9 CMPL	$0,0x68(%R8)

0x40b3fe JNS	40b1a0

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 222

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

[...]

222:    } // loop over local boxes in system

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.34
Bottlenecks
Function	ljForce.extracted
Source	ljForce.c:172-175,ljForce.c:180-182,ljForce.c:187-187,ljForce.c:222-222
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	8.75
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	0.56
Front-end cycles	7.08
P0 cycles	8.20
P1 cycles	5.90
P2 cycles	6.17
P3 cycles	6.17
P4 cycles	0.50
P5 cycles	5.90
P6 cycles	8.10
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	5.90
P11 cycles	6.17
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.50
Nb uops	42.50
Nb loads	18.50
Nb stores	1.00
Nb stack references	3.50
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.52
Bytes prefetched	0.00
Bytes loaded	90.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.70
Vector-efficiency ratio load	9.49
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.36

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:172-175,ljForce.c:180-182,ljForce.c:187-187,ljForce.c:222-222
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.21
Front-end cycles	3.00
P0 cycles	1.90
P1 cycles	1.80
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	0.50
P5 cycles	1.80
P6 cycles	1.70
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.80
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.75
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P0, P6,
Function	ljForce.extracted
Source	ljForce.c:172-175,ljForce.c:180-182,ljForce.c:187-187,ljForce.c:222-222
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	0.91
Front-end cycles	11.17
P0 cycles	14.50
P1 cycles	10.00
P2 cycles	11.00
P3 cycles	11.00
P4 cycles	0.50
P5 cycles	10.00
P6 cycles	14.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	10.00
P11 cycles	11.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	67.00
Nb uops	67.00
Nb loads	33.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.03
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.65
Vector-efficiency ratio load	6.48
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.47

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.extracted
Source file and lines	ljForce.c:172-222
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216,222.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-175,180-182,187,222.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.75 to 0.56 cycles (15.70x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 90 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	42.50
nb uops	42.50
loop length	166.50
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	7.08 cycles
front end	7.08 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.20	5.90	6.17	6.17	0.50	5.90	8.10	0.50	0.50	0.50	5.90	6.17
cycles	8.20	5.90	6.17	6.17	0.50	5.90	8.10	0.50	0.50	0.50	5.90	6.17

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.08
Dispatch	8.20
Data deps.	2.00
Overall L1	8.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

5% of peak load performance is reached (9.91 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.61 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	ljForce.extracted
Source file and lines	ljForce.c:172-222
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.21 cycles (14.40x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	18
nb uops	18
loop length	56
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.90	1.80	1.33	1.33	0.50	1.80	1.70	0.50	0.50	0.50	1.80	1.33
cycles	1.90	1.80	1.33	1.33	0.50	1.80	1.70	0.50	0.50	0.50	1.80	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.00
Dispatch	1.90
Data deps.	2.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

4% of peak load performance is reached (9.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 1.90 cycles (1.58x speedup).

ASM code

In the binary file, the address of the loop is: 40b1b4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,4),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 40b320 <ljForce.extracted+0x2f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x6,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RDI),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVLE %ECX,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %EDI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EAX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 40b1f9 <ljForce.extracted+0x1c9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	ljForce.extracted
Source file and lines	ljForce.c:172-222
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.50 to 0.91 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	67
nb uops	67
loop length	277
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.50	10.00	11.00	11.00	0.50	10.00	14.50	0.50	0.50	0.50	10.00	11.00
cycles	14.50	10.00	11.00	11.00	0.50	10.00	14.50	0.50	0.50	0.50	10.00	11.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	11.17
Dispatch	14.50
Data deps.	2.00
Overall L1	14.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

5% of peak load performance is reached (10.48 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b1b4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x78(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP -0x50(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 40b0b0 <ljForce.extracted+0x80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%RCX,4),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%RCX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 40b320 <ljForce.extracted+0x2f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x4(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x8(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0xc(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x10(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x14(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x18(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x1c(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x20(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x24(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x28(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x2c(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x30(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x34(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x38(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x3c(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x40(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x44(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x48(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x4c(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x50(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x54(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x58(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x5c(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x60(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x64(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JS 40b404 <ljForce.extracted+0x3d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPL $0,0x68(%R8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNS 40b1a0 <ljForce.extracted+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code