OV - exec - Function advancePosition.extracted

	Function: advancePosition.extracted	Module: exec	Source: timestep.c:85-96	Coverage (incl. loops): 0.71% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 96

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

95:       }

96:    }

0x40ebb0 PUSH	%RBP

0x40ebb1 MOV	%RSP,%RBP

0x40ebb4 PUSH	%R15

0x40ebb6 PUSH	%R14

0x40ebb8 PUSH	%R13

0x40ebba PUSH	%R12

0x40ebbc PUSH	%RBX

0x40ebbd SUB	$0x18,%RSP

0x40ebc1 MOV	%RCX,%R15

0x40ebc4 MOV	%RDX,%RBX

0x40ebc7 MOVL	$0,-0x3c(%RBP)

0x40ebce MOV	(%RDI),%ESI

0x40ebd0 MOVL	$0,-0x30(%RBP)

0x40ebd7 MOV	%R9D,-0x2c(%RBP)

0x40ebdb MOVL	$0x1,-0x38(%RBP)

0x40ebe2 SUB	$0x8,%RSP

0x40ebe6 LEA	-0x38(%RBP),%RAX

0x40ebea LEA	-0x3c(%RBP),%RCX

0x40ebee LEA	-0x30(%RBP),%R8

0x40ebf2 LEA	-0x2c(%RBP),%R9

0x40ebf6 MOV	$0x429950,%EDI

0x40ebfb MOV	%ESI,-0x34(%RBP)

0x40ebfe MOV	$0x22,%EDX

0x40ec03 PUSH	$0x1

0x40ec05 PUSH	$0x1

0x40ec07 PUSH	%RAX

0x40ec08 CALL	403240 <__kmpc_for_static_init_4@plt>

0x40ec0d ADD	$0x20,%RSP

0x40ec11 MOV	-0x30(%RBP),%EAX

0x40ec14 MOV	-0x2c(%RBP),%ECX

0x40ec17 CMP	%ECX,%EAX

0x40ec19 JBE	40ec36

0x40ec1b MOV	$0x429970,%EDI

0x40ec20 MOV	-0x34(%RBP),%ESI

0x40ec23 ADD	$0x18,%RSP

0x40ec27 POP	%RBX

0x40ec28 POP	%R12

0x40ec2a POP	%R13

0x40ec2c POP	%R14

0x40ec2e POP	%R15

0x40ec30 POP	%RBP

0x40ec31 JMP	4030f0

0x40ec36 VMOVQ	%R15,%XMM0

0x40ec3b MOV	0x18(%RBX),%RDX

0x40ec3f MOV	0x78(%RDX),%RDX

0x40ec43 MOV	%EAX,%ESI

0x40ec45 SAL	$0x6,%ESI

0x40ec48 INC	%RCX

0x40ec4b JMP	40ec5b

0x40ec4d NOPL	(%RAX)

(94) 0x40ec50 INC	%RAX

(94) 0x40ec53 ADD	$0x40,%ESI

(94) 0x40ec56 CMP	%RCX,%RAX

(94) 0x40ec59 JE	40ec1b

(94) 0x40ec5b MOV	(%RDX,%RAX,4),%R11D

(94) 0x40ec5f TEST	%R11D,%R11D

(94) 0x40ec62 JLE	40ec50

(94) 0x40ec64 MOV	%ESI,%R9D

(94) 0x40ec67 MOV	0x20(%RBX),%R8

(94) 0x40ec6b MOV	0x28(%RBX),%R10

(94) 0x40ec6f MOV	0x10(%R8),%R15

(94) 0x40ec73 MOV	0x18(%R8),%RDI

(94) 0x40ec77 MOV	0x20(%R8),%R8

(94) 0x40ec7b CMP	$0x1,%R11D

(94) 0x40ec7f JE	40ed4c

(94) 0x40ec85 LEA	(%R9,%R9,2),%R12

(94) 0x40ec89 LEA	0x28(,%R12,8),%R12

(94) 0x40ec91 MOV	%R11D,%R13D

(94) 0x40ec94 AND	$0x7ffffffe,%R13D

(94) 0x40ec9b NOPL	(%RAX,%RAX,1)

  (95) 0x40eca0 MOVSXD	(%R15,%R9,4),%R14

  (95) 0x40eca4 SAL	$0x4,%R14

  (95) 0x40eca8 VMOVSD	-0x28(%R8,%R12,1),%XMM1

  (95) 0x40ecaf VDIVSD	0x8(%R10,%R14,1),%XMM0,%XMM2

  (95) 0x40ecb6 VFMADD213SD	-0x28(%RDI,%R12,1),%XMM2,%XMM1

  (95) 0x40ecbd VMOVSD	%XMM1,-0x28(%RDI,%R12,1)

  (95) 0x40ecc4 VMOVSD	-0x20(%R8,%R12,1),%XMM1

  (95) 0x40eccb VFMADD213SD	-0x20(%RDI,%R12,1),%XMM2,%XMM1

  (95) 0x40ecd2 VMOVSD	%XMM1,-0x20(%RDI,%R12,1)

  (95) 0x40ecd9 VMOVSD	-0x18(%R8,%R12,1),%XMM1

  (95) 0x40ece0 VFMADD213SD	-0x18(%RDI,%R12,1),%XMM2,%XMM1

  (95) 0x40ece7 VMOVSD	%XMM1,-0x18(%RDI,%R12,1)

  (95) 0x40ecee MOVSXD	0x4(%R15,%R9,4),%R14

  (95) 0x40ecf3 SAL	$0x4,%R14

  (95) 0x40ecf7 VMOVSD	-0x10(%R8,%R12,1),%XMM1

  (95) 0x40ecfe VDIVSD	0x8(%R10,%R14,1),%XMM0,%XMM2

  (95) 0x40ed05 VFMADD213SD	-0x10(%RDI,%R12,1),%XMM2,%XMM1

  (95) 0x40ed0c VMOVSD	%XMM1,-0x10(%RDI,%R12,1)

  (95) 0x40ed13 VMOVSD	-0x8(%R8,%R12,1),%XMM1

  (95) 0x40ed1a VFMADD213SD	-0x8(%RDI,%R12,1),%XMM2,%XMM1

  (95) 0x40ed21 VMOVSD	%XMM1,-0x8(%RDI,%R12,1)

  (95) 0x40ed28 VMOVSD	(%R8,%R12,1),%XMM1

  (95) 0x40ed2e VFMADD213SD	(%RDI,%R12,1),%XMM2,%XMM1

  (95) 0x40ed34 VMOVSD	%XMM1,(%RDI,%R12,1)

  (95) 0x40ed3a ADD	$0x2,%R9

  (95) 0x40ed3e ADD	$0x30,%R12

  (95) 0x40ed42 ADD	$-0x2,%R13D

  (95) 0x40ed46 JNE	40eca0

(94) 0x40ed4c TEST	$0x1,%R11B

(94) 0x40ed50 JE	40ec50

(94) 0x40ed56 MOVSXD	(%R15,%R9,4),%R11

(94) 0x40ed5a SAL	$0x4,%R11

(94) 0x40ed5e SAL	$0x3,%R9

(94) 0x40ed62 LEA	(%R9,%R9,2),%R9

(94) 0x40ed66 VMOVSD	(%R8,%R9,1),%XMM1

(94) 0x40ed6c VDIVSD	0x8(%R10,%R11,1),%XMM0,%XMM2

(94) 0x40ed73 VFMADD213SD	(%RDI,%R9,1),%XMM2,%XMM1

(94) 0x40ed79 VMOVSD	%XMM1,(%RDI,%R9,1)

(94) 0x40ed7f VMOVSD	0x8(%R8,%R9,1),%XMM1

(94) 0x40ed86 VFMADD213SD	0x8(%RDI,%R9,1),%XMM2,%XMM1

(94) 0x40ed8d VMOVSD	%XMM1,0x8(%RDI,%R9,1)

(94) 0x40ed94 VMOVSD	0x10(%R8,%R9,1),%XMM1

(94) 0x40ed9b VFMADD213SD	0x10(%RDI,%R9,1),%XMM2,%XMM1

(94) 0x40eda2 VMOVSD	%XMM1,0x10(%RDI,%R9,1)

(94) 0x40eda9 JMP	40ec50

0x40edae XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	timestep.c:85-96
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-96.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 1.00 cycles (8.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.67 to 0.58 cycles (14.84x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	51
nb uops	52
loop length	162
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.40	1.40	4.00	4.00	7.50	1.40	1.40	7.50	7.50	7.50	1.40	4.00
cycles	1.40	1.40	4.00	4.00	7.50	1.40	1.40	7.50	7.50	7.50	1.40	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	7.50
Overall L1	8.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

1% of peak load performance is reached (3.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.67 to 7.50 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 40ebb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x429950,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403240 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40ec36 <advancePosition.extracted+0x86>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x429970,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4030f0 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVQ %R15,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 40ec5b <advancePosition.extracted+0xab>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	timestep.c:85-96
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-96.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 1.00 cycles (8.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	51
nb uops	52
loop length	162
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.40	1.40	4.00	4.00	7.50	1.40	1.40	7.50	7.50	7.50	1.40	4.00
cycles	1.40	1.40	4.00	4.00	7.50	1.40	1.40	7.50	7.50	7.50	1.40	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	7.50
Overall L1	8.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

1% of peak load performance is reached (3.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40ebb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x3c(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x429950,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403240 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40ec36 <advancePosition.extracted+0x86>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV $0x429970,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 4030f0 <__kmpc_for_static_fini@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVQ %R15,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOV 0x18(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 40ec5b <advancePosition.extracted+0xab>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advancePosition.extracted–	0.71	0.03
▼Loop 94 - timestep.c:86-96 - exec–	0.04	0.01
○Loop 95 - timestep.c:88-94 - exec	0.68	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code