OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:209-385 [...]	Coverage (incl. loops): 0.44% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 385

--------------------------------------------------------------------------------

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

[...]

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

[...]

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40a830 PUSH	%RBP

0x40a831 MOV	%RSP,%RBP

0x40a834 PUSH	%R15

0x40a836 PUSH	%R14

0x40a838 PUSH	%R13

0x40a83a PUSH	%R12

0x40a83c PUSH	%RBX

0x40a83d SUB	$0x78,%RSP

0x40a841 MOV	%RSI,-0x48(%RBP)

0x40a845 MOV	0xc(%RDI),%R14D

0x40a849 MOV	%RDI,-0x40(%RBP)

0x40a84d MOV	0x14(%RDI),%R15D

0x40a851 CMP	%R15D,%R14D

0x40a854 MOV	%R15D,-0x38(%RBP)

0x40a858 JGE	40a884

0x40a85a MOVSXD	%R14D,%RDI

0x40a85d SAL	$0x2,%RDI

0x40a861 MOV	-0x40(%RBP),%RAX

0x40a865 ADD	0x78(%RAX),%RDI

0x40a869 MOV	%R14D,%EAX

0x40a86c NOT	%EAX

0x40a86e ADD	%R15D,%EAX

0x40a871 LEA	0x4(,%RAX,4),%RDX

0x40a879 XOR	%ESI,%ESI

0x40a87b CALL	410aa0 <_intel_fast_memset>

0x40a880 MOV	-0x38(%RBP),%R15D

0x40a884 TEST	%R14D,%R14D

0x40a887 JLE	40ac44

0x40a88d MOV	-0x40(%RBP),%RAX

0x40a891 MOV	0x78(%RAX),%RAX

0x40a895 LEA	0x1(%R14),%ECX

0x40a899 MOV	%ECX,-0x2c(%RBP)

0x40a89c XOR	%R9D,%R9D

0x40a89f VPCMPEQD	%XMM0,%XMM0,%XMM0

0x40a8a3 MOV	%RAX,-0x58(%RBP)

0x40a8a7 MOV	%R14,-0xa0(%RBP)

0x40a8ae JMP	40a8bc

(80) 0x40a8b0 INC	%R9

(80) 0x40a8b3 CMP	%R14,%R9

(80) 0x40a8b6 JE	40ac44

(80) 0x40a8bc CMPL	$0,(%RAX,%R9,4)

(80) 0x40a8c1 JLE	40a8b0

(80) 0x40a8c3 MOVSXD	%R9D,%RCX

(80) 0x40a8c6 SAL	$0x6,%RCX

(80) 0x40a8ca MOV	%RCX,-0x88(%RBP)

(80) 0x40a8d1 MOV	-0x48(%RBP),%RCX

(80) 0x40a8d5 MOV	0x18(%RCX),%R10

(80) 0x40a8d9 MOV	-0x40(%RBP),%RAX

(80) 0x40a8dd VMOVSD	0x30(%RAX),%XMM1

(80) 0x40a8e2 MOV	(%RAX),%R11D

(80) 0x40a8e5 LEA	-0x1(%R11),%ECX

(80) 0x40a8e9 MOV	%ECX,-0x64(%RBP)

(80) 0x40a8ec VMOVUPD	0x38(%RAX),%XMM2

(80) 0x40a8f1 VMOVUPD	0x20(%RAX),%XMM3

(80) 0x40a8f6 VMOVUPD	0x68(%RAX),%XMM4

(80) 0x40a8fb MOV	0x4(%RAX),%R13

(80) 0x40a8ff MOV	-0x58(%RBP),%RAX

(80) 0x40a903 VMOVQ	%R13,%XMM5

(80) 0x40a908 MOV	%R13,%RCX

(80) 0x40a90b SHR	$0x20,%RCX

(80) 0x40a90f VPADDD	%XMM0,%XMM5,%XMM6

(80) 0x40a913 MOV	%RCX,-0x98(%RBP)

(80) 0x40a91a LEA	(%RCX,%RCX,1),%EDX

(80) 0x40a91d MOV	%RDX,%RCX

(80) 0x40a920 MOV	%RDX,-0x80(%RBP)

(80) 0x40a924 IMUL	%R13D,%ECX

(80) 0x40a928 MOV	%ECX,-0x34(%RBP)

(80) 0x40a92b LEA	0x2(%R11),%ECX

(80) 0x40a92f MOV	%ECX,-0x30(%RBP)

(80) 0x40a932 VPINSRD	$0,%R14D,%XMM5,%XMM7

(80) 0x40a938 XOR	%EBX,%EBX

(80) 0x40a93a MOV	%R11,-0x78(%RBP)

(80) 0x40a93e MOV	%R13,-0x70(%RBP)

(80) 0x40a942 MOV	%R9,-0x50(%RBP)

(80) 0x40a946 JMP	40a960

0x40a948 NOPL	(%RAX,%RAX,1)

  (81) 0x40a950 MOV	-0x60(%RBP),%RBX

  (81) 0x40a954 INC	%EBX

  (81) 0x40a956 CMP	(%RAX,%R9,4),%EBX

  (81) 0x40a95a JGE	40a8b0

  (81) 0x40a960 MOV	-0x88(%RBP),%RCX

  (81) 0x40a967 ADD	%EBX,%ECX

  (81) 0x40a969 MOVSXD	%ECX,%RCX

  (81) 0x40a96c MOV	%RCX,-0x90(%RBP)

  (81) 0x40a973 LEA	(%RCX,%RCX,2),%R12

  (81) 0x40a977 VMOVSD	(%R10,%R12,8),%XMM8

  (81) 0x40a97d VUCOMISD	%XMM8,%XMM1

  (81) 0x40a982 MOV	%R11D,%ECX

  (81) 0x40a985 JBE	40a9ab

  (81) 0x40a987 MOV	-0x40(%RBP),%RAX

  (81) 0x40a98b VSUBSD	0x18(%RAX),%XMM8,%XMM8

  (81) 0x40a990 VMULSD	0x60(%RAX),%XMM8,%XMM8

  (81) 0x40a995 MOV	-0x58(%RBP),%RAX

  (81) 0x40a999 VROUNDSD	$0x9,%XMM8,%XMM8,%XMM8

  (81) 0x40a99f VCVTTSD2SI	%XMM8,%ECX

  (81) 0x40a9a4 CMP	%ECX,%R11D

  (81) 0x40a9a7 CMOVE	-0x64(%RBP),%ECX

  (81) 0x40a9ab VMOVUPD	0x8(%R10,%R12,8),%XMM9

  (81) 0x40a9b2 VSUBPD	%XMM3,%XMM9,%XMM8

  (81) 0x40a9b6 VMULPD	%XMM4,%XMM8,%XMM8

  (81) 0x40a9ba VROUNDPD	$0x9,%XMM8,%XMM8

  (81) 0x40a9c0 VCVTTPD2DQ	%XMM8,%XMM8

  (81) 0x40a9c5 VPCMPEQD	%XMM8,%XMM5,%K1

  (81) 0x40a9cb VCMPPD	$0x5,%XMM2,%XMM9,%K0

  (81) 0x40a9d2 KMOVD	%K0,%EDX

  (81) 0x40a9d6 VMOVDQA32	%XMM6,%XMM8{%K1}

  (81) 0x40a9dc VMOVD	%XMM8,%ESI

  (81) 0x40a9e0 TEST	$0x1,%DL

  (81) 0x40a9e3 MOV	%ESI,%R8D

  (81) 0x40a9e6 CMOVNE	%R13D,%R8D

  (81) 0x40a9ea TEST	$0x2,%DL

  (81) 0x40a9ed JE	40aa10

  (81) 0x40a9ef ADD	%R13D,%R8D

  (81) 0x40a9f2 MOV	-0x80(%RBP),%RDX

  (81) 0x40a9f6 LEA	0x3(%RDX,%R8,1),%EDX

  (81) 0x40a9fb IMUL	-0x30(%RBP),%EDX

  (81) 0x40a9ff ADD	-0x2c(%RBP),%ECX

  (81) 0x40aa02 ADD	-0x34(%RBP),%ECX

  (81) 0x40aa05 ADD	%EDX,%ECX

  (81) 0x40aa07 JMP	40aa81

0x40aa09 NOPL	(%RAX)

  (81) 0x40aa10 MOV	%R15D,%EDI

  (81) 0x40aa13 VPEXTRD	$0x1,%XMM8,%R15D

  (81) 0x40aa19 CMP	$-0x1,%R15D

  (81) 0x40aa1d JE	40aa2d

  (81) 0x40aa1f TEST	$0x1,%DL

  (81) 0x40aa22 JE	40aa44

  (81) 0x40aa24 ADD	-0x98(%RBP),%R15D

  (81) 0x40aa2b JMP	40aa70

  (81) 0x40aa2d MOV	-0x80(%RBP),%RDX

  (81) 0x40aa31 LEA	0x1(%R8,%RDX,1),%EDX

  (81) 0x40aa36 IMUL	-0x30(%RBP),%EDX

  (81) 0x40aa3a ADD	-0x2c(%RBP),%ECX

  (81) 0x40aa3d ADD	-0x34(%RBP),%ECX

  (81) 0x40aa40 ADD	%EDX,%ECX

  (81) 0x40aa42 JMP	40aa7e

  (81) 0x40aa44 CMP	$-0x1,%ESI

  (81) 0x40aa47 JE	40aa70

  (81) 0x40aa49 CMP	%ECX,%R11D

  (81) 0x40aa4c JNE	40ac22

  (81) 0x40aa52 VPADDD	%XMM7,%XMM8,%XMM8

  (81) 0x40aa56 VPEXTRD	$0x1,%XMM8,%EDX

  (81) 0x40aa5c IMUL	%R13D,%EDX

  (81) 0x40aa60 VMOVD	%XMM8,%ECX

  (81) 0x40aa64 ADD	%EDX,%ECX

  (81) 0x40aa66 JMP	40aa7e

0x40aa68 NOPL	(%RAX,%RAX,1)

  (81) 0x40aa70 IMUL	-0x30(%RBP),%R15D

  (81) 0x40aa75 ADD	-0x2c(%RBP),%ECX

  (81) 0x40aa78 ADD	-0x34(%RBP),%ECX

  (81) 0x40aa7b ADD	%R15D,%ECX

  (81) 0x40aa7e MOV	%EDI,%R15D

  (81) 0x40aa81 TEST	%ECX,%ECX

  (81) 0x40aa83 JS	40ac53

  (81) 0x40aa89 CMP	%R15D,%ECX

  (81) 0x40aa8c JGE	40ac6c

  (81) 0x40aa92 MOV	%RBX,-0x60(%RBP)

  (81) 0x40aa96 MOV	%ECX,%EBX

  (81) 0x40aa98 CMP	%RBX,%R9

  (81) 0x40aa9b JE	40a950

  (81) 0x40aaa1 MOVSXD	(%RAX,%RBX,4),%RSI

  (81) 0x40aaa5 MOVSXD	%ECX,%RDX

  (81) 0x40aaa8 SAL	$0x6,%RDX

  (81) 0x40aaac ADD	%RSI,%RDX

  (81) 0x40aaaf MOV	-0x48(%RBP),%RAX

  (81) 0x40aab3 MOV	0x8(%RAX),%R14

  (81) 0x40aab7 MOV	-0x90(%RBP),%R13

  (81) 0x40aabe MOV	(%R14,%R13,4),%ESI

  (81) 0x40aac2 MOV	%ESI,(%R14,%RDX,4)

  (81) 0x40aac6 MOV	0x10(%RAX),%R11

  (81) 0x40aaca MOV	(%R11,%R13,4),%ESI

  (81) 0x40aace MOV	%ESI,(%R11,%RDX,4)

  (81) 0x40aad2 LEA	(%R10,%R12,8),%R12

  (81) 0x40aad6 LEA	(,%RDX,8),%RSI

  (81) 0x40aade MOV	%R10,%R8

  (81) 0x40aae1 LEA	(%RSI,%RSI,2),%R10

  (81) 0x40aae5 MOV	0x10(%R12),%RSI

  (81) 0x40aaea MOV	%RSI,0x10(%R8,%R10,1)

  (81) 0x40aaef VMOVUPS	(%R12),%XMM8

  (81) 0x40aaf5 MOV	%R8,%RDI

  (81) 0x40aaf8 VMOVUPS	%XMM8,(%R8,%R10,1)

  (81) 0x40aafe MOV	0x20(%RAX),%RSI

  (81) 0x40ab02 LEA	(,%R13,8),%R8

  (81) 0x40ab0a LEA	(%R8,%R8,2),%R15

  (81) 0x40ab0e MOV	0x10(%RSI,%R15,1),%R8

  (81) 0x40ab13 MOV	%R8,0x10(%RSI,%R10,1)

  (81) 0x40ab18 VMOVUPS	(%RSI,%R15,1),%XMM8

  (81) 0x40ab1e VMOVUPS	%XMM8,(%RSI,%R10,1)

  (81) 0x40ab24 MOV	0x28(%RAX),%R8

  (81) 0x40ab28 MOV	0x10(%R8,%R15,1),%R9

  (81) 0x40ab2d MOV	%R9,0x10(%R8,%R10,1)

  (81) 0x40ab32 VMOVDQU	(%R8,%R15,1),%XMM8

  (81) 0x40ab38 VMOVDQU	%XMM8,(%R8,%R10,1)

  (81) 0x40ab3e MOV	0x30(%RAX),%R10

  (81) 0x40ab42 MOV	-0x58(%RBP),%RAX

  (81) 0x40ab46 MOV	(%R10,%R13,8),%R9

  (81) 0x40ab4a MOV	%R9,(%R10,%RDX,8)

  (81) 0x40ab4e MOV	(%RAX,%RBX,4),%EDX

  (81) 0x40ab51 LEA	0x1(%RDX),%R9D

  (81) 0x40ab55 MOV	%R9D,(%RAX,%RBX,4)

  (81) 0x40ab59 CMP	$0x3f,%EDX

  (81) 0x40ab5c JGE	40ac85

  (81) 0x40ab62 MOV	-0x50(%RBP),%RDX

  (81) 0x40ab66 MOVSXD	(%RAX,%RDX,4),%RBX

  (81) 0x40ab6a DEC	%RBX

  (81) 0x40ab6d MOV	%EBX,(%RAX,%RDX,4)

  (81) 0x40ab70 TEST	%EBX,%EBX

  (81) 0x40ab72 JE	40abea

  (81) 0x40ab74 LEA	(%RSI,%R15,1),%RDX

  (81) 0x40ab78 ADD	-0x88(%RBP),%RBX

  (81) 0x40ab7f MOV	(%R14,%RBX,4),%R9D

  (81) 0x40ab83 MOV	-0x90(%RBP),%R13

  (81) 0x40ab8a MOV	%R9D,(%R14,%R13,4)

  (81) 0x40ab8e MOV	(%R11,%RBX,4),%R9D

  (81) 0x40ab92 MOV	%R9D,(%R11,%R13,4)

  (81) 0x40ab96 ADD	%R8,%R15

  (81) 0x40ab99 LEA	(,%RBX,8),%R9

  (81) 0x40aba1 LEA	(%R9,%R9,2),%R9

  (81) 0x40aba5 MOV	0x10(%RDI,%R9,1),%R11

  (81) 0x40abaa MOV	%R11,0x10(%R12)

  (81) 0x40abaf VMOVUPS	(%RDI,%R9,1),%XMM8

  (81) 0x40abb5 VMOVUPS	%XMM8,(%R12)

  (81) 0x40abbb MOV	0x10(%RSI,%R9,1),%R11

  (81) 0x40abc0 MOV	%R11,0x10(%RDX)

  (81) 0x40abc4 VMOVUPS	(%RSI,%R9,1),%XMM8

  (81) 0x40abca VMOVUPS	%XMM8,(%RDX)

  (81) 0x40abce MOV	0x10(%R8,%R9,1),%RDX

  (81) 0x40abd3 MOV	%RDX,0x10(%R15)

  (81) 0x40abd7 VMOVDQU	(%R8,%R9,1),%XMM8

  (81) 0x40abdd VMOVDQU	%XMM8,(%R15)

  (81) 0x40abe2 MOV	(%R10,%RBX,8),%RDX

  (81) 0x40abe6 MOV	%RDX,(%R10,%R13,8)

  (81) 0x40abea MOV	-0xa0(%RBP),%R14

  (81) 0x40abf1 CMP	%ECX,%R14D

  (81) 0x40abf4 JGE	40abfc

  (81) 0x40abf6 MOV	-0x48(%RBP),%RCX

  (81) 0x40abfa DECL	(%RCX)

  (81) 0x40abfc MOV	-0x38(%RBP),%R15D

  (81) 0x40ac00 MOV	-0x50(%RBP),%R9

  (81) 0x40ac04 MOV	%RDI,%R10

  (81) 0x40ac07 MOV	-0x78(%RBP),%R11

  (81) 0x40ac0b MOV	-0x70(%RBP),%R13

  (81) 0x40ac0f MOV	-0x60(%RBP),%RBX

  (81) 0x40ac13 CMP	(%RAX,%R9,4),%EBX

  (81) 0x40ac17 JL	40a960

(80) 0x40ac1d JMP	40a8b0

  (81) 0x40ac22 IMUL	%R13D,%R15D

  (81) 0x40ac26 CMP	$-0x1,%ECX

  (81) 0x40ac29 JE	40ac37

  (81) 0x40ac2b ADD	%ESI,%R15D

  (81) 0x40ac2e IMUL	%R11D,%R15D

  (81) 0x40ac32 JMP	40aa7b

  (81) 0x40ac37 ADD	%R14D,%ESI

  (81) 0x40ac3a ADD	%R15D,%ESI

  (81) 0x40ac3d MOV	%ESI,%ECX

  (81) 0x40ac3f JMP	40aa7e

0x40ac44 ADD	$0x78,%RSP

0x40ac48 POP	%RBX

0x40ac49 POP	%R12

0x40ac4b POP	%R13

0x40ac4d POP	%R14

0x40ac4f POP	%R15

0x40ac51 POP	%RBP

0x40ac52 RET

0x40ac53 MOV	$0x41f914,%EDI

0x40ac58 MOV	$0x41f83e,%ESI

0x40ac5d MOV	$0x41f91e,%ECX

0x40ac62 MOV	$0xf6,%EDX

0x40ac67 CALL	4030b0 <__assert_fail@plt>

0x40ac6c MOV	$0x41f94d,%EDI

0x40ac71 MOV	$0x41f83e,%ESI

0x40ac76 MOV	$0x41f91e,%ECX

0x40ac7b MOV	$0xf7,%EDX

0x40ac80 CALL	4030b0 <__assert_fail@plt>

0x40ac85 MOV	$0x41f967,%EDI

0x40ac8a MOV	$0x41f83e,%ESI

0x40ac8f MOV	$0x41f986,%ECX

0x40ac94 MOV	$0x106,%EDX

0x40ac99 CALL	4030b0 <__assert_fail@plt>

0x40ac9e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►59.96+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►38.06+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►1.97+	redistributeAtoms	timestep.c:148	exec
○	main	CoMD.c:207	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:209-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:209-221,227-247,258-269,288-304,327-334,352-353,359-365,371,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 1.00 cycles (11.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 11.33 to 0.79 cycles (14.42x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262
_intel_fast_memset: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:385

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	64
nb uops	68
loop length	243
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67
cycles	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	8.00
Overall L1	11.33

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.33 cycles. At this rate:

2% of peak load performance is reached (3.88 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.33 to 8.00 cycles (1.42x speedup).

ASM code

In the binary file, the address of the function is: 40a830

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x14(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP %R15D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JGE 40a884 <updateLinkCells+0x54>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %R14D,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
SAL $0x2,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x78(%RAX),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 410aa0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40ac44 <updateLinkCells+0x414>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPCMPEQD %XMM0,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 40a8bc <updateLinkCells+0x8c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV $0x41f914,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41f83e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41f91e,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x41f94d,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41f83e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41f91e,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x41f967,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41f83e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41f986,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x106,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:209-385
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262
_intel_fast_memset: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:385

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	64
nb uops	68
loop length	243
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67
cycles	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	8.00
Overall L1	11.33

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.33 cycles. At this rate:

2% of peak load performance is reached (3.88 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40a830

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x14(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP %R15D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JGE 40a884 <updateLinkCells+0x54>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %R14D,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
SAL $0x2,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x78(%RAX),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 410aa0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40ac44 <updateLinkCells+0x414>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPCMPEQD %XMM0,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 40a8bc <updateLinkCells+0x8c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV $0x41f914,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41f83e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41f91e,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x41f94d,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41f83e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41f91e,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x41f967,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41f83e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41f986,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x106,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.44	0.02
▼Loop 80 - linkCells.c:209-371 - exec–	0.00	0.01
○Loop 81 - linkCells.c:209-371 - exec	0.43	0.88

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Matching between your function (in the source code) and the binary function

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