OV - exec - Function putAtomInBox

	Function: putAtomInBox	Module: exec	Source: linkCells.c:173-378 [...]	Coverage (incl. loops): 0.17% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 173 - 378

--------------------------------------------------------------------------------

173: {

174:    real_t xyz[3] = {x,y,z};

175:

176:    // Find correct box.

177:    int iBox = getBoxFromCoord(boxes, xyz);

178:    int iOff = iBox*MAXATOMS;

179:    iOff += boxes->nAtoms[iBox];

180:

181:    // assign values to array elements

182:    if (iBox < boxes->nLocalBoxes)

183:       atoms->nLocal++;

184:    boxes->nAtoms[iBox]++;

185:    atoms->gid[iOff] = gid;

186:    atoms->iSpecies[iOff] = iType;

187:

188:    atoms->r[iOff][0] = x;

189:    atoms->r[iOff][1] = y;

190:    atoms->r[iOff][2] = z;

191:

192:    atoms->p[iOff][0] = px;

193:    atoms->p[iOff][1] = py;

194:    atoms->p[iOff][2] = pz;

195: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

378:    return getBoxFromTuple(boxes, ix, iy, iz);

0x40a520 PUSH	%RBP

0x40a521 MOV	%RSP,%RBP

0x40a524 PUSH	%R15

0x40a526 PUSH	%R14

0x40a528 PUSH	%R12

0x40a52a PUSH	%RBX

0x40a52b SUB	$0x40,%RSP

0x40a52f MOV	%RDI,%R12

0x40a532 VPUNPCKLQDQ	%XMM2,%XMM1,%XMM6

0x40a536 VSUBPD	0x20(%RDI),%XMM6,%XMM6

0x40a53b VMULPD	0x68(%RDI),%XMM6,%XMM6

0x40a540 VROUNDPD	$0x9,%XMM6,%XMM6

0x40a546 VMOVSD	%XMM5,-0x40(%RBP)

0x40a54b VMOVSD	%XMM4,-0x38(%RBP)

0x40a550 VMOVSD	%XMM3,-0x30(%RBP)

0x40a555 MOV	%ECX,%R14D

0x40a558 MOV	%EDX,%R15D

0x40a55b MOV	%RSI,%RBX

0x40a55e VCVTTPD2DQ	%XMM6,%XMM5

0x40a562 VMOVSD	0x30(%RDI),%XMM3

0x40a567 VUCOMISD	%XMM0,%XMM3

0x40a56b MOV	(%RDI),%ESI

0x40a56d VMOVSD	%XMM0,-0x28(%RBP)

0x40a572 JBE	40a596

0x40a574 VSUBSD	0x18(%R12),%XMM0,%XMM3

0x40a57b VMULSD	0x60(%R12),%XMM3,%XMM3

0x40a582 VROUNDSD	$0x9,%XMM3,%XMM3,%XMM3

0x40a588 VCVTTSD2SI	%XMM3,%EAX

0x40a58c CMP	%EAX,%ESI

0x40a58e LEA	-0x1(%RSI),%ECX

0x40a591 CMOVNE	%EAX,%ECX

0x40a594 MOV	%ECX,%ESI

0x40a596 VMOVSD	0x38(%R12),%XMM4

0x40a59d MOV	0x4(%R12),%RAX

0x40a5a2 VMOVQ	%RAX,%XMM3

0x40a5a7 LEA	-0x1(%RAX),%ECX

0x40a5aa VPCMPEQD	%XMM5,%XMM3,%K0

0x40a5b0 KMOVD	%K0,%EDI

0x40a5b4 VMOVD	%XMM5,%EDX

0x40a5b8 TEST	$0x1,%DIL

0x40a5bc CMOVNE	%ECX,%EDX

0x40a5bf VMOVUPD	%XMM1,-0x50(%RBP)

0x40a5c4 VUCOMISD	%XMM1,%XMM4

0x40a5c8 VMOVSD	0x40(%R12),%XMM1

0x40a5cf CMOVBE	%EAX,%EDX

0x40a5d2 SHR	$0x20,%RAX

0x40a5d6 LEA	-0x1(%RAX),%R8D

0x40a5da VPEXTRD	$0x1,%XMM5,%ECX

0x40a5e0 TEST	$0x2,%DIL

0x40a5e4 CMOVNE	%R8D,%ECX

0x40a5e8 VMOVUPD	%XMM2,-0x60(%RBP)

0x40a5ed VUCOMISD	%XMM2,%XMM1

0x40a5f1 CMOVBE	%EAX,%ECX

0x40a5f4 MOV	%R12,%RDI

0x40a5f7 CALL	40a410 <getBoxFromTuple>

0x40a5fc MOV	0x78(%R12),%RCX

0x40a601 MOV	%EAX,%EDX

0x40a603 MOV	(%RCX,%RDX,4),%ESI

0x40a606 CMP	0xc(%R12),%EAX

0x40a60b JGE	40a60f

0x40a60d INCL	(%RBX)

0x40a60f MOV	%EDX,%EAX

0x40a611 SAL	$0x6,%EAX

0x40a614 ADD	%ESI,%EAX

0x40a616 INC	%ESI

0x40a618 MOV	%ESI,(%RCX,%RDX,4)

0x40a61b MOV	0x8(%RBX),%RCX

0x40a61f CLTQ

0x40a621 MOV	%R15D,(%RCX,%RAX,4)

0x40a625 MOV	0x10(%RBX),%RCX

0x40a629 MOV	%R14D,(%RCX,%RAX,4)

0x40a62d MOV	0x18(%RBX),%RCX

0x40a631 SAL	$0x3,%RAX

0x40a635 LEA	(%RAX,%RAX,2),%RAX

0x40a639 VMOVSD	-0x28(%RBP),%XMM0

0x40a63e VMOVSD	%XMM0,(%RCX,%RAX,1)

0x40a643 VMOVUPS	-0x50(%RBP),%XMM0

0x40a648 VMOVSD	%XMM0,0x8(%RCX,%RAX,1)

0x40a64e VMOVUPS	-0x60(%RBP),%XMM0

0x40a653 VMOVSD	%XMM0,0x10(%RCX,%RAX,1)

0x40a659 MOV	0x20(%RBX),%RCX

0x40a65d VMOVSD	-0x30(%RBP),%XMM0

0x40a662 VMOVSD	%XMM0,(%RCX,%RAX,1)

0x40a667 VMOVSD	-0x38(%RBP),%XMM0

0x40a66c VMOVSD	%XMM0,0x8(%RCX,%RAX,1)

0x40a672 VMOVSD	-0x40(%RBP),%XMM0

0x40a677 VMOVSD	%XMM0,0x10(%RCX,%RAX,1)

0x40a67d ADD	$0x40,%RSP

0x40a681 POP	%RBX

0x40a682 POP	%R12

0x40a684 POP	%R14

0x40a686 POP	%R15

0x40a688 POP	%RBP

0x40a689 RET

0x40a68a NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►6.70+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►6.46+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►6.22+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►5.74+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►5.26+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►4.55+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►4.31+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►4.31+	createFccLattice	initAtoms.c:100	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6
►4.07+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►4.07+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►3.83+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►3.83+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►3.83+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►3.35+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►2.87+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►2.63+	createFccLattice	initAtoms.c:100	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6
►2.63+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►2.63+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►2.39+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►2.15+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►2.15+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►2.15+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►1.68+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►1.67+	unloadAtomsBuffer	haloExchange.c:416	exec
○	haloExchange	haloExchange.c:302	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►1.44+	createFccLattice	initAtoms.c:100	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6
►1.44+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►1.44+	unloadAtomsBuffer	haloExchange.c:414	exec
○	haloExchange	memUtils.h:28	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►1.20+	createFccLattice	initAtoms.c:100	exec
○	main	CoMD.c:199	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:173-378
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:173-195,352-365,371,378.

This function has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.25 to 1.59 cycles (10.19x speedup).

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

27% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
75% of SSE/AVX multiply instructions are used in vector version.
19% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

getBoxFromTuple: 0 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 0 occurrences
INC: 0 occurrences
VCVTTPD2DQ: 0 occurrences
VCVTTSD2SI: 0 occurrences
VPEXTRD: 0 occurrences
VROUNDPD: 0 occurrences
VROUNDSD: 0 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 0 occurrences
VCVTTPD2DQ (FP64 to INT32, SIMD): 0 occurrences
VCVTTSD2SI (FP64 to INT32/64, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

2.50: addition or subtraction
2.50: multiply

The binary function is loading 190 bytes (23 double precision FP elements). The binary function is storing 126 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	89.50
nb uops	97.50
loop length	344
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	16.25 cycles
front end	16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	7.35	9.17	9.17	10.75	7.00	9.75	10.75	10.75	10.75	6.90	9.17
cycles	10.00	7.35	9.17	9.17	10.75	7.00	9.75	10.75	10.75	10.75	6.90	9.17

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.25
Dispatch	10.88
Overall L1	16.25

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	26%
load	33%
store	16%
mul	75%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

INT+FP

all	20%
load	27%
store	12%
mul	75%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	16%
store	14%
mul	21%
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	13%
load	14%
store	12%
mul	21%
add-sub	17%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.25 cycles. At this rate:

6% of peak load performance is reached (11.70 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.77 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.33 to 8.00 cycles (2.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.33 to 1.69 cycles (10.23x speedup).

Details

19% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
17% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:378

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:183
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VCVTTSD2SI: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
VPEXTRD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VROUNDSD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:185
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 200 bytes (25 double precision FP elements). The binary function is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	104
loop length	362
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.33 cycles
front end	17.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	8.50	9.67	9.67	11.00	8.00	10.50	11.00	11.00	11.00	8.00	9.67
cycles	11.00	8.50	9.67	9.67	11.00	8.00	10.50	11.00	11.00	11.00	8.00	9.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.33
Dispatch	11.00
Overall L1	17.33

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	30%
store	16%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	19%
load	26%
store	12%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	16%
store	14%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	13%
load	15%
store	12%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.33 cycles. At this rate:

6% of peak load performance is reached (11.54 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.33 to 11.00 cycles (1.58x speedup).

ASM code

In the binary file, the address of the function is: 40a520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPUNPCKLQDQ %XMM2,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD 0x20(%RDI),%XMM6,%XMM6	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VMULPD 0x68(%RDI),%XMM6,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VROUNDPD $0x9,%XMM6,%XMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTTPD2DQ %XMM6,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (25.0%)
VMOVSD 0x30(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JBE 40a596 <putAtomInBox+0x76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x18(%R12),%XMM0,%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMULSD 0x60(%R12),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM3,%XMM3,%XMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM3,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %EAX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x1(%RSI),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMOVNE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x38(%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x4(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ %RAX,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
LEA -0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPCMPEQD %XMM5,%XMM3,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVD %K0,%EDI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %XMM5,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x1,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %ECX,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM1,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD 0x40(%R12),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVBE %EAX,%EDX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x1(%RAX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPEXTRD $0x1,%XMM5,%ECX	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
TEST $0x2,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %R8D,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMOVBE %EAX,%ECX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 40a410 <getBoxFromTuple>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x78(%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX,%RDX,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0xc(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40a60f <putAtomInBox+0xef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INCL (%RBX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,(%RCX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x18(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.83 to 8.00 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
17% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:378

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VCVTTSD2SI: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
VPEXTRD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VROUNDSD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:185
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary function is loading 196 bytes (24 double precision FP elements). The binary function is storing 124 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	101
loop length	360
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.83 cycles
front end	16.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.00	8.50	9.33	9.33	10.50	7.60	10.50	10.50	10.50	10.50	7.40	9.33
cycles	11.00	8.50	9.33	9.33	10.50	7.60	10.50	10.50	10.50	10.50	7.40	9.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.83
Dispatch	11.00
Overall L1	16.83

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	30%
store	16%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	20%
load	28%
store	13%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

INT

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	15%
load	16%
store	14%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

INT+FP

all	13%
load	15%
store	12%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.83 cycles. At this rate:

6% of peak load performance is reached (11.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40a520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPUNPCKLQDQ %XMM2,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD 0x20(%RDI),%XMM6,%XMM6	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VMULPD 0x68(%RDI),%XMM6,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VROUNDPD $0x9,%XMM6,%XMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTTPD2DQ %XMM6,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (25.0%)
VMOVSD 0x30(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JBE 40a596 <putAtomInBox+0x76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VSUBSD 0x18(%R12),%XMM0,%XMM3	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMULSD 0x60(%R12),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VROUNDSD $0x9,%XMM3,%XMM3,%XMM3	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM3,%EAX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %EAX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA -0x1(%RSI),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMOVNE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x38(%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x4(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ %RAX,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
LEA -0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPCMPEQD %XMM5,%XMM3,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVD %K0,%EDI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %XMM5,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x1,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %ECX,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM1,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD 0x40(%R12),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVBE %EAX,%EDX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x1(%RAX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPEXTRD $0x1,%XMM5,%ECX	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
TEST $0x2,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %R8D,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMOVBE %EAX,%ECX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 40a410 <getBoxFromTuple>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x78(%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX,%RDX,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0xc(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40a60f <putAtomInBox+0xef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,(%RCX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x18(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.67 to 6.67 cycles (2.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
21% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:378

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:183
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VPEXTRD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:185
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: addition or subtraction
2: multiply

The binary function is loading 184 bytes (23 double precision FP elements). The binary function is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	86
nb uops	94
loop length	328
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.67 cycles
front end	15.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.00	6.40	9.00	9.00	11.00	6.40	9.00	11.00	11.00	11.00	6.20	9.00
cycles	9.00	6.40	9.00	9.00	11.00	6.40	9.00	11.00	11.00	11.00	6.20	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.67
Dispatch	11.00
Overall L1	15.67

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	28%
load	36%
store	16%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	20%
load	26%
store	12%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	17%
store	14%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	13%
load	14%
store	12%
mul	25%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.67 cycles. At this rate:

6% of peak load performance is reached (11.74 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.17 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40a520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPUNPCKLQDQ %XMM2,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD 0x20(%RDI),%XMM6,%XMM6	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VMULPD 0x68(%RDI),%XMM6,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VROUNDPD $0x9,%XMM6,%XMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTTPD2DQ %XMM6,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (25.0%)
VMOVSD 0x30(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JBE 40a596 <putAtomInBox+0x76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x38(%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x4(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ %RAX,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
LEA -0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPCMPEQD %XMM5,%XMM3,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVD %K0,%EDI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %XMM5,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x1,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %ECX,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM1,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD 0x40(%R12),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVBE %EAX,%EDX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x1(%RAX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPEXTRD $0x1,%XMM5,%ECX	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
TEST $0x2,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %R8D,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMOVBE %EAX,%ECX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 40a410 <getBoxFromTuple>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x78(%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX,%RDX,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP 0xc(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40a60f <putAtomInBox+0xef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INCL (%RBX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,(%RCX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x18(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:173-378
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.17 to 6.67 cycles (2.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
21% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

getBoxFromTuple: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:378

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVBE: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VPEXTRD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:185
VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: addition or subtraction
2: multiply

The binary function is loading 180 bytes (22 double precision FP elements). The binary function is storing 124 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	85
nb uops	91
loop length	326
used x86 registers	12
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.17 cycles
front end	15.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.00	6.00	8.67	8.67	10.50	6.00	9.00	10.50	10.50	10.50	6.00	8.67
cycles	9.00	6.00	8.67	8.67	10.50	6.00	9.00	10.50	10.50	10.50	6.00	8.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.17
Dispatch	10.50
Overall L1	15.17

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	28%
load	36%
store	16%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	20%
load	28%
store	13%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	8%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	16%
load	17%
store	14%
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	13%
load	14%
store	12%
mul	25%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.17 cycles. At this rate:

6% of peak load performance is reached (11.87 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40a520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPUNPCKLQDQ %XMM2,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBPD 0x20(%RDI),%XMM6,%XMM6	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (25.0%)
VMULPD 0x68(%RDI),%XMM6,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VROUNDPD $0x9,%XMM6,%XMM6	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VMOVSD %XMM5,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTTPD2DQ %XMM6,%XMM5	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (25.0%)
VMOVSD 0x30(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM0,%XMM3	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSD %XMM0,-0x28(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JBE 40a596 <putAtomInBox+0x76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x38(%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x4(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ %RAX,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
LEA -0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPCMPEQD %XMM5,%XMM3,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVD %K0,%EDI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %XMM5,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x1,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %ECX,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM1,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM1,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVSD 0x40(%R12),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVBE %EAX,%EDX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
SHR $0x20,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA -0x1(%RAX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPEXTRD $0x1,%XMM5,%ECX	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
TEST $0x2,%DIL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
CMOVNE %R8D,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
VMOVUPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VUCOMISD %XMM2,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
CMOVBE %EAX,%ECX	2	1	0	0	0	0	0	1	0	0	0	0	0	1-2	1	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 40a410 <getBoxFromTuple>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x78(%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX,%RDX,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP 0xc(%R12),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40a60f <putAtomInBox+0xef>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
INC %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,(%RCX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14D,(%RCX,%RAX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x18(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x28(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS -0x60(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x8(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM0,0x10(%RCX,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
○putAtomInBox	0.17	0.01

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CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

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Vectorization