OV - exec - Function loadAtomsBuffer

	Function: loadAtomsBuffer	Module: exec	Source: haloExchange.c:362-393	Coverage (incl. loops): 0.06% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 362 - 393

--------------------------------------------------------------------------------

362: {

363:    AtomExchangeParms* parms = (AtomExchangeParms*) vparms;

364:    SimFlat* s = (SimFlat*) data;

365:    AtomMsg* buf = (AtomMsg*) charBuf;

366:

367:    real_t* pbcFactor = parms->pbcFactor[face];

368:    real3 shift;

369:    shift[0] = pbcFactor[0] * s->domain->globalExtent[0];

370:    shift[1] = pbcFactor[1] * s->domain->globalExtent[1];

371:    shift[2] = pbcFactor[2] * s->domain->globalExtent[2];

372:

373:    int nCells = parms->nCells[face];

374:    int* cellList = parms->cellList[face];

375:    int nBuf = 0;

376:    for (int iCell=0; iCell<nCells; ++iCell)

377:    {

378:       int iBox = cellList[iCell];

379:       int iOff = iBox*MAXATOMS;

380:       for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii)

381:       {

382:          buf[nBuf].gid  = s->atoms->gid[ii];

383:          buf[nBuf].type = s->atoms->iSpecies[ii];

384:          buf[nBuf].rx = s->atoms->r[ii][0] + shift[0];

385:          buf[nBuf].ry = s->atoms->r[ii][1] + shift[1];

386:          buf[nBuf].rz = s->atoms->r[ii][2] + shift[2];

387:          buf[nBuf].px = s->atoms->p[ii][0];

388:          buf[nBuf].py = s->atoms->p[ii][1];

389:          buf[nBuf].pz = s->atoms->p[ii][2];

390:          ++nBuf;

391:       }

392:    }

393:    return nBuf*sizeof(AtomMsg);

0x406d90 PUSH	%RBP

0x406d91 MOV	%RSP,%RBP

0x406d94 PUSH	%R15

0x406d96 PUSH	%R14

0x406d98 PUSH	%R13

0x406d9a PUSH	%R12

0x406d9c PUSH	%RBX

0x406d9d MOV	%RCX,-0x30(%RBP)

0x406da1 MOVSXD	%EDX,%RDX

0x406da4 MOVSXD	(%RDI,%RDX,4),%RAX

0x406da8 TEST	%RAX,%RAX

0x406dab JLE	406eae

0x406db1 MOV	0x18(%RDI,%RDX,8),%RCX

0x406db6 MOV	%RCX,-0x38(%RBP)

0x406dba MOV	0x48(%RDI,%RDX,8),%RDX

0x406dbf MOV	0x10(%RSI),%RDI

0x406dc3 VMOVUPD	0x48(%RDI),%XMM0

0x406dc8 VMULPD	(%RDX),%XMM0,%XMM0

0x406dcc VMOVSD	0x58(%RDI),%XMM1

0x406dd1 VMULSD	0x10(%RDX),%XMM1,%XMM1

0x406dd6 MOV	0x18(%RSI),%RDX

0x406dda MOV	0x78(%RDX),%RDI

0x406dde XOR	%R8D,%R8D

0x406de1 XOR	%R9D,%R9D

0x406de4 JMP	406dfc

0x406de6 NOPW	%CS:(%RAX,%RAX,1)

(45) 0x406df0 INC	%R8

(45) 0x406df3 CMP	%RAX,%R8

(45) 0x406df6 JE	406ea8

(45) 0x406dfc MOV	-0x38(%RBP),%RCX

(45) 0x406e00 MOVSXD	(%RCX,%R8,4),%RDX

(45) 0x406e04 MOV	(%RDI,%RDX,4),%R12D

(45) 0x406e08 TEST	%R12D,%R12D

(45) 0x406e0b JLE	406df0

(45) 0x406e0d SAL	$0x6,%EDX

(45) 0x406e10 ADD	%EDX,%R12D

(45) 0x406e13 MOV	0x20(%RSI),%R14

(45) 0x406e17 MOV	0x8(%R14),%R10

(45) 0x406e1b MOV	0x10(%R14),%R11

(45) 0x406e1f MOV	0x18(%R14),%RBX

(45) 0x406e23 MOV	0x20(%R14),%R14

(45) 0x406e27 MOVSXD	%EDX,%R15

(45) 0x406e2a MOVSXD	%R12D,%R12

(45) 0x406e2d MOVSXD	%R9D,%RDX

(45) 0x406e30 IMUL	$0x38,%RDX,%R13

(45) 0x406e34 ADD	-0x30(%RBP),%R13

(45) 0x406e38 LEA	(%R15,%R15,1),%RDX

(45) 0x406e3c LEA	0x4(%RDX,%RDX,2),%RDX

(45) 0x406e41 NOPW	%CS:(%RAX,%RAX,1)

  (46) 0x406e50 MOV	(%R10,%R15,4),%ECX

  (46) 0x406e54 MOV	%ECX,(%R13)

  (46) 0x406e58 MOV	(%R11,%R15,4),%ECX

  (46) 0x406e5c MOV	%ECX,0x4(%R13)

  (46) 0x406e60 VADDPD	-0x10(%RBX,%RDX,4),%XMM0,%XMM2

  (46) 0x406e66 VMOVUPD	%XMM2,0x8(%R13)

  (46) 0x406e6c VADDSD	(%RBX,%RDX,4),%XMM1,%XMM2

  (46) 0x406e71 VMOVSD	%XMM2,0x18(%R13)

  (46) 0x406e77 VMOVUPS	-0x10(%R14,%RDX,4),%XMM2

  (46) 0x406e7e VMOVUPS	%XMM2,0x20(%R13)

  (46) 0x406e84 VMOVSD	(%R14,%RDX,4),%XMM2

  (46) 0x406e8a VMOVSD	%XMM2,0x30(%R13)

  (46) 0x406e90 INC	%R15

  (46) 0x406e93 ADD	$0x38,%R13

  (46) 0x406e97 INC	%R9D

  (46) 0x406e9a ADD	$0x6,%RDX

  (46) 0x406e9e CMP	%R12,%R15

  (46) 0x406ea1 JL	406e50

(45) 0x406ea3 JMP	406df0

0x406ea8 IMUL	$0x38,%R9D,%EAX

0x406eac JMP	406eb0

0x406eae XOR	%EAX,%EAX

0x406eb0 POP	%RBX

0x406eb1 POP	%R12

0x406eb3 POP	%R13

0x406eb5 POP	%R14

0x406eb7 POP	%R15

0x406eb9 POP	%RBP

0x406eba RET

0x406ebb NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►18.42+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►13.82+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►11.18+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►10.53+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►9.21+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►8.56+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►8.55+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►4.61+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►4.60+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►3.95+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►2.63+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►2.63+	haloExchange	haloExchange.c:288	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	haloExchange.c:362-393
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:362-393.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.67 cycles (3.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 6.17 to 0.54 cycles (11.38x speedup).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	37
nb uops	37
loop length	120
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.50	5.67	5.67	4.00	1.07	1.50	4.00	4.00	4.00	0.93	5.67
cycles	2.00	1.53	5.67	5.67	4.00	1.07	1.50	4.00	4.00	4.00	0.93	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	5.67
Overall L1	6.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	22%
load	40%
store	0%
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	18%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	17%
store	12%
mul	18%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

7% of peak load performance is reached (14.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.17 to 5.67 cycles (1.09x speedup).

ASM code

In the binary file, the address of the function is: 406d90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD (%RDI,%RDX,4),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 406eae <loadAtomsBuffer+0x11e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RDI,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RDI,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD 0x48(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULPD (%RDX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVSD 0x58(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD 0x10(%RDX),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x18(%RSI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 406dfc <loadAtomsBuffer+0x6c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL $0x38,%R9D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
JMP 406eb0 <loadAtomsBuffer+0x120>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	haloExchange.c:362-393
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:362-393.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.17 to 1.67 cycles (3.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	37
nb uops	37
loop length	120
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.50	5.67	5.67	4.00	1.07	1.50	4.00	4.00	4.00	0.93	5.67
cycles	2.00	1.53	5.67	5.67	4.00	1.07	1.50	4.00	4.00	4.00	0.93	5.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.17
Dispatch	5.67
Overall L1	6.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	22%
load	40%
store	0%
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	18%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	17%
store	12%
mul	18%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

7% of peak load performance is reached (14.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 406d90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %EDX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD (%RDI,%RDX,4),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 406eae <loadAtomsBuffer+0x11e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RDI,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RDI,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPD 0x48(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMULPD (%RDX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVSD 0x58(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD 0x10(%RDX),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV 0x18(%RSI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 406dfc <loadAtomsBuffer+0x6c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL $0x38,%R9D,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
JMP 406eb0 <loadAtomsBuffer+0x120>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼loadAtomsBuffer–	0.06	0.00
▼Loop 45 - haloExchange.c:376-389 - exec–	0.00	0.01
○Loop 46 - haloExchange.c:380-389 - exec	0.06	0.12

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code