OV - exec - Function __libm_log

	Function: __libm_log_z0	Module: exec	Source: :0-0	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x410770 ENDBR64

0x410774 VMOVQ	%XMM0,%RAX

0x410779 MOV	%RAX,%RCX

0x41077c SHR	$0x20,%RCX

0x410780 ADD	$-0x7ff00000,%ECX

0x410786 CMP	$-0x7fe00000,%ECX

0x41078c JB	410870

0x410792 VMOVQ	%XMM0,%XMM2

0x410796 VPBROADCASTQ	0x12cb1(%RIP),%XMM1

0x41079f VPTERNLOGQ	$-0x8,0x12cae(%RIP){1to2},%XMM0,%XMM1

0x4107aa VGETEXPSD	%XMM2,%XMM2,%XMM0

0x4107b0 VMOVQ	%XMM1,%XMM2

0x4107b4 VPSRLQ	$0x1d,%XMM2,%XMM2

0x4107b9 VRCPSS	%XMM2,%XMM2,%XMM2

0x4107bd VPADDD	0x12469(%RIP){1to4},%XMM2,%XMM2

0x4107c7 VPSRLD	$0x10,%XMM2,%XMM2

0x4107cc VPSLLQ	$0x2d,%XMM2,%XMM3

0x4107d1 VPORQ	0x12c85(%RIP){1to2},%XMM1,%XMM1

0x4107db VFMADD213SD	0xea84(%RIP),%XMM3,%XMM1

0x4107e4 VMOVSD	0x12404(%RIP),%XMM3

0x4107ec VFMADD213SD	0x12403(%RIP),%XMM1,%XMM3

0x4107f5 VMOVSD	0x12403(%RIP),%XMM4

0x4107fd VFMADD213SD	0x12402(%RIP),%XMM1,%XMM4

0x410806 VMOVSD	0x12402(%RIP),%XMM5

0x41080e VFMADD213SD	0x12401(%RIP),%XMM1,%XMM5

0x410817 VPADDQ	%XMM2,%XMM2,%XMM2

0x41081b VMOVD	%XMM2,%EAX

0x41081f AND	$0x1fe,%EAX

0x410824 LEA	0x12c45(%RIP),%RCX

0x41082b VMOVSD	0x123ed(%RIP),%XMM2

0x410833 VFMADD213SD	0x8(%RCX,%RAX,8),%XMM0,%XMM2

0x41083a VMOVSD	0x123e6(%RIP),%XMM6

0x410842 VFMADD213SD	(%RCX,%RAX,8),%XMM0,%XMM6

0x410848 VADDSD	%XMM1,%XMM6,%XMM0

0x41084c VSUBSD	%XMM6,%XMM0,%XMM6

0x410850 VSUBSD	%XMM6,%XMM1,%XMM6

0x410854 VADDSD	%XMM6,%XMM2,%XMM2

0x410858 VMULSD	%XMM1,%XMM1,%XMM1

0x41085c VFMADD231SD	%XMM3,%XMM1,%XMM4

0x410861 VFMADD213SD	%XMM5,%XMM1,%XMM4

0x410866 VFMADD213SD	%XMM2,%XMM1,%XMM4

0x41086b VADDSD	%XMM4,%XMM0,%XMM0

0x41086f RET

0x410870 VXORPD	%XMM2,%XMM2,%XMM2

0x410874 VADDSD	%XMM2,%XMM0,%XMM1

0x410878 VUCOMISD	%XMM2,%XMM0

0x41087c JNE	410880

0x41087e JNP	4108b9

0x410880 SHR	$0x34,%RAX

0x410884 JNE	4108b9

0x410886 VMULSD	0x12352(%RIP),%XMM1,%XMM0

0x41088e VMOVQ	%XMM0,%XMM2

0x410892 VPBROADCASTQ	0x12bb5(%RIP),%XMM1

0x41089b VPTERNLOGQ	$-0x8,0x12bb2(%RIP){1to2},%XMM0,%XMM1

0x4108a6 VGETEXPSD	%XMM2,%XMM2,%XMM0

0x4108ac VADDSD	0x12334(%RIP),%XMM0,%XMM0

0x4108b4 JMP	4107b0

0x4108b9 VMOVAPD	%XMM1,%XMM0

0x4108bd JMP	40f940

0x4108c2 NOPW	%CS:(%RAX,%RAX,1)

0x4108cc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►67.28+	setTemperature.extracted.30	initAtoms.c:160	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►18.18+	setTemperature.extracted.30	initAtoms.c:162	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►14.54+	setTemperature.extracted.30	initAtoms.c:161	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines
Module	exec

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 11.67 to 1.67 cycles (7.00x speedup).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

21% of SSE/AVX loads are used in vector version.
22% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.67 to 10.67 cycles (1.09x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPTERNLOGQ: 2 occurrences►

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 28 FP arithmetical operations:

16: addition or subtraction (9 inside FMA instructions)
11: multiply (9 inside FMA instructions)
1: fast reciprocal

The binary function is loading 148 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	61
nb uops	62
loop length	352
used x86 registers	2
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.67 cycles
front end	10.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.67	11.67	6.67	6.67	0.00	11.67	7.00	0.00	0.00	0.00	3.00	6.67
cycles	11.67	11.67	6.67	6.67	0.00	11.67	7.00	0.00	0.00	0.00	3.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.67
Dispatch	11.67
Overall L1	11.67

Vectorization ratios

INT

all	53%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	46%

all	6%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	40%

INT+FP

all	22%
load	21%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	22%
fma	0%
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	18%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	6%
other	17%

INT+FP

all	15%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	15%
fma	12%
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.67 cycles. At this rate:

6% of peak load performance is reached (12.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $-0x7ff00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $-0x7fe00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 410870 <__libm_log_z0+0x100>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPBROADCASTQ 0x12cb1(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPTERNLOGQ $-0x8,0x12cae(%RIP){1to2},%XMM0,%XMM1	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VGETEXPSD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPSRLQ $0x1d,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VRCPSS %XMM2,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	4	1	scal (6.3%)
VPADDD 0x12469(%RIP){1to4},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLD $0x10,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPSLLQ $0x2d,%XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPORQ 0x12c85(%RIP){1to2},%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VFMADD213SD 0xea84(%RIP),%XMM3,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x12404(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x12403(%RIP),%XMM1,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x12403(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x12402(%RIP),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x12402(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x12401(%RIP),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VPADDQ %XMM2,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVD %XMM2,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
AND $0x1fe,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x12c45(%RIP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x123ed(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%RCX,%RAX,8),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x123e6(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD (%RCX,%RAX,8),%XMM0,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM6,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM3,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM5,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM2,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 410880 <__libm_log_z0+0x110>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JNP 4108b9 <__libm_log_z0+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SHR $0x34,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 4108b9 <__libm_log_z0+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD 0x12352(%RIP),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVQ %XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPBROADCASTQ 0x12bb5(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPTERNLOGQ $-0x8,0x12bb2(%RIP){1to2},%XMM0,%XMM1	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VGETEXPSD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD 0x12334(%RIP),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
JMP 4107b0 <__libm_log_z0+0x40>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 40f940 <__libm_log_e7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run orig_0

Source file and lines
Module	exec

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

21% of SSE/AVX loads are used in vector version.
22% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPTERNLOGQ: 2 occurrences►

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 28 FP arithmetical operations:

16: addition or subtraction (9 inside FMA instructions)
11: multiply (9 inside FMA instructions)
1: fast reciprocal

The binary function is loading 148 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	61
nb uops	62
loop length	352
used x86 registers	2
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.67 cycles
front end	10.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.67	11.67	6.67	6.67	0.00	11.67	7.00	0.00	0.00	0.00	3.00	6.67
cycles	11.67	11.67	6.67	6.67	0.00	11.67	7.00	0.00	0.00	0.00	3.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.67
Dispatch	11.67
Overall L1	11.67

Vectorization ratios

INT

all	53%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	46%

all	6%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	40%

INT+FP

all	22%
load	21%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	22%
fma	0%
div/sqrt	0%
other	44%

Vector efficiency ratios

INT

all	18%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	6%
other	17%

INT+FP

all	15%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	15%
fma	12%
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.67 cycles. At this rate:

6% of peak load performance is reached (12.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $-0x7ff00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $-0x7fe00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 410870 <__libm_log_z0+0x100>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPBROADCASTQ 0x12cb1(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPTERNLOGQ $-0x8,0x12cae(%RIP){1to2},%XMM0,%XMM1	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VGETEXPSD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPSRLQ $0x1d,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VRCPSS %XMM2,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	4	1	scal (6.3%)
VPADDD 0x12469(%RIP){1to4},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLD $0x10,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPSLLQ $0x2d,%XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPORQ 0x12c85(%RIP){1to2},%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VFMADD213SD 0xea84(%RIP),%XMM3,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x12404(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x12403(%RIP),%XMM1,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x12403(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x12402(%RIP),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x12402(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x12401(%RIP),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VPADDQ %XMM2,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVD %XMM2,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
AND $0x1fe,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x12c45(%RIP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x123ed(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%RCX,%RAX,8),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x123e6(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD (%RCX,%RAX,8),%XMM0,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM6,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM3,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM5,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM2,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 410880 <__libm_log_z0+0x110>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JNP 4108b9 <__libm_log_z0+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SHR $0x34,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 4108b9 <__libm_log_z0+0x149>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD 0x12352(%RIP),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVQ %XMM0,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPBROADCASTQ 0x12bb5(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPTERNLOGQ $-0x8,0x12bb2(%RIP){1to2},%XMM0,%XMM1	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VGETEXPSD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD 0x12334(%RIP),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
JMP 4107b0 <__libm_log_z0+0x40>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 40f940 <__libm_log_e7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
○__libm_log_z0	0.02	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code