OV - exec - Loop 91

	Loop Id: 91	Module: exec	Source: random.c:26-48 [...]	Coverage: 0.04%

0x40fe80 IMUL	%RCX,%RDX

0x40fe84 MULX	%RSI,%R8,%R8

0x40fe89 MOV	%RDX,%RAX

0x40fe8c SUB	%R8,%RAX

0x40fe8f SHR	$0x1,%RAX

0x40fe92 ADD	%R8,%RAX

0x40fe95 SHR	$0x3c,%RAX

0x40fe99 MOV	%RAX,%R8

0x40fe9c SAL	$0x3d,%R8

0x40fea0 SUB	%R8,%RAX

0x40fea3 ADD	%RDX,%RAX

0x40fea6 VCVTSI2SD	%RAX,%XMM5,%XMM4

0x40feab VFMADD213SD	%XMM0,%XMM1,%XMM4

0x40feb0 IMUL	%RCX,%RAX

0x40feb4 MOV	%RAX,%RDX

0x40feb7 MULX	%RSI,%R8,%R8

0x40febc SUB	%R8,%RDX

0x40febf SHR	$0x1,%RDX

0x40fec2 ADD	%R8,%RDX

0x40fec5 SHR	$0x3c,%RDX

0x40fec9 MOV	%RDX,%R8

0x40fecc SAL	$0x3d,%R8

0x40fed0 SUB	%R8,%RDX

0x40fed3 ADD	%RAX,%RDX

0x40fed6 VCVTSI2SD	%RDX,%XMM5,%XMM17

0x40fedc VFMADD213SD	%XMM0,%XMM1,%XMM17

0x40fee2 VMULSD	%XMM4,%XMM4,%XMM16

0x40fee8 VFMADD231SD	%XMM17,%XMM17,%XMM16

0x40feee VUCOMISD	%XMM2,%XMM16

0x40fef4 JAE	40fe80

0x40fef6 VUCOMISD	%XMM3,%XMM16

0x40fefc JNE	40ff00

0x40fefe JNP	40fe80

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 26 - 48

--------------------------------------------------------------------------------

26:       v1 = 2.0*lcg61(seed)-1.0;

27:       v2 = 2.0*lcg61(seed)-1.0;

28:       rsq = v1*v1+v2*v2;

29:    } while (rsq >= 1.0 || rsq == 0.0);

[...]

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

47:

48:    return *seed*convertToDouble;

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.97
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40 - 4.00
Bottlenecks
Function	gasdev
Source	random.c:26-29,random.c:45-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00 - 30.00
CQA cycles if no scalar integer	18.00 - 30.00
CQA cycles if FP arith vectorized	6.07 - 10.11
CQA cycles if fully vectorized	2.25 - 3.75
Front-end cycles	6.17
P0 cycles	7.50
P1 cycles	6.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	6.00
P6 cycles	7.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	6.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	18 - 30
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	37.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.39 - 0.23
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.97
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40 - 4.00
Bottlenecks
Function	gasdev
Source	random.c:26-29,random.c:45-48
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00 - 30.00
CQA cycles if no scalar integer	18.00 - 30.00
CQA cycles if FP arith vectorized	6.07 - 10.11
CQA cycles if fully vectorized	2.25 - 3.75
Front-end cycles	6.17
P0 cycles	7.50
P1 cycles	6.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	6.00
P6 cycles	7.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	6.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	18 - 30
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	37.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.39 - 0.23
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	gasdev
Source file and lines	random.c:26-48
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:26-29,45-48.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 30.00 to 3.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 3 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MULX: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
VCVTSI2SD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
4: multiply (3 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	33
nb uops	37
loop length	128
used x86 registers	5
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	6.50	0.00	0.00	0.00	6.00	7.00	0.00	0.00	0.00	6.00	0.00
cycles	7.50	6.50	0.00	0.00	0.00	6.00	7.00	0.00	0.00	0.00	6.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	18.00-30.00

Cycles summary

Front-end	6.17
Dispatch	7.50
Data deps.	18.00-30.00
Overall L1	18.00-30.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40fe80

Instruction	Nb FU	P0	P1	P5	P6	P10	Latency	Recip. throughput	Vectorization
IMUL %RCX,%RDX	1	0	1	0	0	0	3	1	N/A
MULX %RSI,%R8,%R8	2	0	1	1	0	0	3-4	1	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
ADD %R8,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x3c,%RAX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
MOV %RAX,%R8	1	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R8	1	0.50	0	0	0.50	0	0-2	0.50	scal (12.5%)
SUB %R8,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
VCVTSI2SD %RAX,%XMM5,%XMM4	2	0.50	0.50	1	0	0	7	1	scal (12.5%)
VFMADD213SD %XMM0,%XMM1,%XMM4	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
IMUL %RCX,%RAX	1	0	1	0	0	0	3	1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	1	0.17	N/A
MULX %RSI,%R8,%R8	2	0	1	1	0	0	3-4	1	scal (12.5%)
SUB %R8,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x1,%RDX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
ADD %R8,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x3c,%RDX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
MOV %RDX,%R8	1	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R8	1	0.50	0	0	0.50	0	0-2	0.50	scal (12.5%)
SUB %R8,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
VCVTSI2SD %RDX,%XMM5,%XMM17	2	0.50	0.50	1	0	0	7	1	scal (12.5%)
VFMADD213SD %XMM0,%XMM1,%XMM17	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM4,%XMM4,%XMM16	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM17,%XMM17,%XMM16	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM16	1	1	0	0	0	0	3	1	scal (12.5%)
JAE 40fe80 <gasdev+0x30>	1	0.50	0	0	0.50	0	0	0.50	N/A
VUCOMISD %XMM3,%XMM16	1	1	0	0	0	0	3	1	scal (12.5%)
JNE 40ff00 <gasdev+0xb0>	1	0.50	0	0	0.50	0	0	0.50	N/A
JNP 40fe80 <gasdev+0x30>	1	0.50	0	0	0.50	0	0	0.50	N/A

Function	gasdev
Source file and lines	random.c:26-48
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 30.00 to 3.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 3 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MULX: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
VCVTSI2SD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7 FP arithmetical operations:

3: addition or subtraction (all inside FMA instructions)
4: multiply (3 inside FMA instructions)

The binary loop does not load or store any data.

General properties

nb instructions	33
nb uops	37
loop length	128
used x86 registers	5
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.17 cycles
front end	6.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.50	6.50	0.00	0.00	0.00	6.00	7.00	0.00	0.00	0.00	6.00	0.00
cycles	7.50	6.50	0.00	0.00	0.00	6.00	7.00	0.00	0.00	0.00	6.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	18.00-30.00

Cycles summary

Front-end	6.17
Dispatch	7.50
Data deps.	18.00-30.00
Overall L1	18.00-30.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40fe80

Instruction	Nb FU	P0	P1	P5	P6	P10	Latency	Recip. throughput	Vectorization
IMUL %RCX,%RDX	1	0	1	0	0	0	3	1	N/A
MULX %RSI,%R8,%R8	2	0	1	1	0	0	3-4	1	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	1	0.17	N/A
SUB %R8,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
ADD %R8,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x3c,%RAX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
MOV %RAX,%R8	1	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R8	1	0.50	0	0	0.50	0	0-2	0.50	scal (12.5%)
SUB %R8,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
VCVTSI2SD %RAX,%XMM5,%XMM4	2	0.50	0.50	1	0	0	7	1	scal (12.5%)
VFMADD213SD %XMM0,%XMM1,%XMM4	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
IMUL %RCX,%RAX	1	0	1	0	0	0	3	1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	1	0.17	N/A
MULX %RSI,%R8,%R8	2	0	1	1	0	0	3-4	1	scal (12.5%)
SUB %R8,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x1,%RDX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
ADD %R8,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
SHR $0x3c,%RDX	1	0.50	0	0	0.50	0	0-2	0.50	N/A
MOV %RDX,%R8	1	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R8	1	0.50	0	0	0.50	0	0-2	0.50	scal (12.5%)
SUB %R8,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
ADD %RAX,%RDX	1	0.20	0.20	0.20	0.20	0.20	1	0.20	N/A
VCVTSI2SD %RDX,%XMM5,%XMM17	2	0.50	0.50	1	0	0	7	1	scal (12.5%)
VFMADD213SD %XMM0,%XMM1,%XMM17	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM4,%XMM4,%XMM16	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM17,%XMM17,%XMM16	1	0.50	0.50	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM16	1	1	0	0	0	0	3	1	scal (12.5%)
JAE 40fe80 <gasdev+0x30>	1	0.50	0	0	0.50	0	0	0.50	N/A
VUCOMISD %XMM3,%XMM16	1	1	0	0	0	0	3	1	scal (12.5%)
JNE 40ff00 <gasdev+0xb0>	1	0.50	0	0	0.50	0	0	0.50	N/A
JNP 40fe80 <gasdev+0x30>	1	0.50	0	0	0.50	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code