OV - exec - Loop 90

	Loop Id: 90	Module: exec	Source: ljForce.c:158-162 [...]	Coverage: 0.60%

0x40cda0 VMOVUPS	%XMM0,(%R9)    [1]

0x40cda5 MOVQ	$0,0x10(%R9)    [1]

0x40cdad MOVQ	$0,-0x38(%R10)    [2]

0x40cdb5 VMOVUPS	%XMM0,0x18(%R9)    [1]

0x40cdbb MOVQ	$0,0x28(%R9)    [1]

0x40cdc3 MOVQ	$0,-0x30(%R10)    [2]

0x40cdcb VMOVUPS	%XMM0,0x30(%R9)    [1]

0x40cdd1 MOVQ	$0,0x40(%R9)    [1]

0x40cdd9 MOVQ	$0,-0x28(%R10)    [2]

0x40cde1 VMOVUPS	%XMM0,0x48(%R9)    [1]

0x40cde7 MOVQ	$0,0x58(%R9)    [1]

0x40cdef MOVQ	$0,-0x20(%R10)    [2]

0x40cdf7 VMOVUPS	%XMM0,0x60(%R9)    [1]

0x40cdfd MOVQ	$0,0x70(%R9)    [1]

0x40ce05 MOVQ	$0,-0x18(%R10)    [2]

0x40ce0d VMOVUPS	%XMM0,0x78(%R9)    [1]

0x40ce13 MOVQ	$0,0x88(%R9)    [1]

0x40ce1e MOVQ	$0,-0x10(%R10)    [2]

0x40ce26 VMOVUPS	%XMM0,0x90(%R9)    [1]

0x40ce2f MOVQ	$0,0xa0(%R9)    [1]

0x40ce3a MOVQ	$0,-0x8(%R10)    [2]

0x40ce42 VMOVUPS	%XMM0,0xa8(%R9)    [1]

0x40ce4b MOVQ	$0,0xb8(%R9)    [1]

0x40ce56 MOVQ	$0,(%R10)    [2]

0x40ce5d ADD	$0xc0,%R9

0x40ce64 ADD	$0x40,%R10

0x40ce68 DEC	%R8

0x40ce6b JNE	40cda0

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 23 - 23

--------------------------------------------------------------------------------

23:    a[1] = 0.0;

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 158 - 162

--------------------------------------------------------------------------------

158:    for (int ii=0; ii<fSize; ++ii)

159:    {

160:       zeroReal3(s->atoms->f[ii]);

161:       s->atoms->U[ii] = 0.;

162:    }

Coverage (%)	Name	Source Location	Module
►100.00+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P4, P7, P8, P9,
Function	ljForce.extracted.27
Source	mytype.h:23-23,ljForce.c:158-162
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	12.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	1.50
Front-end cycles	4.50
P0 cycles	0.50
P1 cycles	0.40
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	12.00
P5 cycles	0.40
P6 cycles	0.50
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	0.20
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	27.00
Nb loads	0.00
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	NA
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.67
Bottlenecks	P4, P7, P8, P9,
Function	ljForce.extracted.27
Source	mytype.h:23-23,ljForce.c:158-162
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	12.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	1.50
Front-end cycles	4.50
P0 cycles	0.50
P1 cycles	0.40
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	12.00
P5 cycles	0.40
P6 cycles	0.50
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	12.00
P10 cycles	0.20
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	27.00
Nb loads	0.00
Nb stores	24.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	NA
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.extracted.27
Source file and lines	ljForce.c:158-162
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:158-162

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 4.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	28
nb uops	27
loop length	209
used x86 registers	3
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.50 cycles
front end	4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.40	0.00	0.00	12.00	0.40	0.50	12.00	12.00	12.00	0.20	0.00
cycles	0.50	0.40	0.00	0.00	12.00	0.40	0.50	12.00	12.00	12.00	0.20	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.50
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40cda0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVUPS %XMM0,(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x10(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x38(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x18(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x28(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x30(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x30(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x40(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x28(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x48(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x58(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x20(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x60(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x70(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x18(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x78(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x88(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x10(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x90(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0xa0(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x8(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0xa8(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0xb8(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
ADD $0xc0,%R9	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
ADD $0x40,%R10	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R8	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40cda0 <ljForce.extracted.27+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	ljForce.extracted.27
Source file and lines	ljForce.c:158-162
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:158-162

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 4.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

General properties

nb instructions	28
nb uops	27
loop length	209
used x86 registers	3
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.50 cycles
front end	4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.40	0.00	0.00	12.00	0.40	0.50	12.00	12.00	12.00	0.20	0.00
cycles	0.50	0.40	0.00	0.00	12.00	0.40	0.50	12.00	12.00	12.00	0.20	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.50
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40cda0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
VMOVUPS %XMM0,(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x10(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x38(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x18(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x28(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x30(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x30(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x40(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x28(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x48(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x58(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x20(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x60(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x70(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x18(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x78(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0x88(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x10(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0x90(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0xa0(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,-0x8(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
VMOVUPS %XMM0,0xa8(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	0-1	0.50	vect (25.0%)
MOVQ $0,0xb8(%R9)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
MOVQ $0,(%R10)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
ADD $0xc0,%R9	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
ADD $0x40,%R10	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R8	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40cda0 <ljForce.extracted.27+0xa0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code