OV - exec - Loop 82

	Loop Id: 82	Module: exec	Source: linkCells.c:209-371 [...]	Coverage: 0.43%

0x40bf40 MOV	-0x60(%RBP),%RBX    [13]

0x40bf44 INC	%EBX

0x40bf46 CMP	(%RAX,%R9,4),%EBX    [9]

0x40bf4a JGE	40be80

0x40bf50 MOV	-0x88(%RBP),%RCX    [13]

0x40bf57 ADD	%EBX,%ECX

0x40bf59 MOVSXD	%ECX,%RCX

0x40bf5c MOV	%RCX,-0x90(%RBP)    [13]

0x40bf63 LEA	(%RCX,%RCX,2),%R12

0x40bf67 VMOVSD	(%R10,%R12,8),%XMM8    [6]

0x40bf6d VUCOMISD	%XMM8,%XMM1

0x40bf72 MOV	%R11D,%ECX

0x40bf75 JBE	40bf9b

0x40bf77 MOV	-0x40(%RBP),%RAX    [13]

0x40bf7b VSUBSD	0x18(%RAX),%XMM8,%XMM8    [10]

0x40bf80 VMULSD	0x60(%RAX),%XMM8,%XMM8    [10]

0x40bf85 MOV	-0x58(%RBP),%RAX    [13]

0x40bf89 VROUNDSD	$0x9,%XMM8,%XMM8,%XMM8

0x40bf8f VCVTTSD2SI	%XMM8,%ECX

0x40bf94 CMP	%ECX,%R11D

0x40bf97 CMOVE	-0x64(%RBP),%ECX    [13]

0x40bf9b VMOVUPD	0x8(%R10,%R12,8),%XMM9    [6]

0x40bfa2 VSUBPD	%XMM3,%XMM9,%XMM8

0x40bfa6 VMULPD	%XMM4,%XMM8,%XMM8

0x40bfaa VROUNDPD	$0x9,%XMM8,%XMM8

0x40bfb0 VCVTTPD2DQ	%XMM8,%XMM8

0x40bfb5 VPCMPEQD	%XMM8,%XMM5,%K1

0x40bfbb VCMPPD	$0x5,%XMM2,%XMM9,%K0

0x40bfc2 KMOVD	%K0,%EDX

0x40bfc6 VMOVDQA32	%XMM6,%XMM8{%K1}

0x40bfcc VMOVD	%XMM8,%ESI

0x40bfd0 TEST	$0x1,%DL

0x40bfd3 MOV	%ESI,%R8D

0x40bfd6 CMOVNE	%R13D,%R8D

0x40bfda TEST	$0x2,%DL

0x40bfdd JE	40c000

0x40bfdf ADD	%R13D,%R8D

0x40bfe2 MOV	-0x80(%RBP),%RDX    [13]

0x40bfe6 LEA	0x3(%RDX,%R8,1),%EDX

0x40bfeb IMUL	-0x30(%RBP),%EDX    [13]

0x40bfef ADD	-0x2c(%RBP),%ECX    [13]

0x40bff2 ADD	-0x34(%RBP),%ECX    [13]

0x40bff5 ADD	%EDX,%ECX

0x40bff7 JMP	40c0d1

0x40c000 MOV	%R15D,%EDI

0x40c003 VPEXTRD	$0x1,%XMM8,%R15D

0x40c009 CMP	$-0x1,%R15D

0x40c00d JE	40c040

0x40c00f TEST	$0x1,%DL

0x40c012 JE	40c080

0x40c014 ADD	-0x98(%RBP),%R15D    [13]

0x40c01b JMP	40c0c0

0x40c040 MOV	-0x80(%RBP),%RDX    [13]

0x40c044 LEA	0x1(%R8,%RDX,1),%EDX

0x40c049 IMUL	-0x30(%RBP),%EDX    [13]

0x40c04d ADD	-0x2c(%RBP),%ECX    [13]

0x40c050 ADD	-0x34(%RBP),%ECX    [13]

0x40c053 ADD	%EDX,%ECX

0x40c055 JMP	40c0ce

0x40c080 CMP	$-0x1,%ESI

0x40c083 JE	40c0c0

0x40c085 CMP	%ECX,%R11D

0x40c088 JNE	40c280

0x40c08e VPADDD	%XMM7,%XMM8,%XMM8

0x40c092 VPEXTRD	$0x1,%XMM8,%EDX

0x40c098 IMUL	%R13D,%EDX

0x40c09c VMOVD	%XMM8,%ECX

0x40c0a0 ADD	%EDX,%ECX

0x40c0a2 JMP	40c0ce

0x40c0c0 IMUL	-0x30(%RBP),%R15D    [13]

0x40c0c5 ADD	-0x2c(%RBP),%ECX    [13]

0x40c0c8 ADD	-0x34(%RBP),%ECX    [13]

0x40c0cb ADD	%R15D,%ECX

0x40c0ce MOV	%EDI,%R15D

0x40c0d1 TEST	%ECX,%ECX

0x40c0d3 JS	40c340

0x40c0d9 CMP	%R15D,%ECX

0x40c0dc JGE	40c380

0x40c0e2 MOV	%RBX,-0x60(%RBP)    [13]

0x40c0e6 MOV	%ECX,%EBX

0x40c0e8 CMP	%RBX,%R9

0x40c0eb JE	40bf40

0x40c0f1 MOVSXD	(%RAX,%RBX,4),%RSI    [9]

0x40c0f5 MOVSXD	%ECX,%RDX

0x40c0f8 SAL	$0x6,%RDX

0x40c0fc ADD	%RSI,%RDX

0x40c0ff MOV	-0x48(%RBP),%RAX    [13]

0x40c103 MOV	0x8(%RAX),%R14    [8]

0x40c107 MOV	-0x90(%RBP),%R13    [13]

0x40c10e MOV	(%R14,%R13,4),%ESI    [15]

0x40c112 MOV	%ESI,(%R14,%RDX,4)    [15]

0x40c116 MOV	0x10(%RAX),%R11    [8]

0x40c11a MOV	(%R11,%R13,4),%ESI    [11]

0x40c11e MOV	%ESI,(%R11,%RDX,4)    [11]

0x40c122 LEA	(%R10,%R12,8),%R12

0x40c126 LEA	(,%RDX,8),%RSI

0x40c12e MOV	%R10,%R8

0x40c131 LEA	(%RSI,%RSI,2),%R10

0x40c135 MOV	0x10(%R12),%RSI    [14]

0x40c13a MOV	%RSI,0x10(%R8,%R10,1)    [2]

0x40c13f VMOVUPS	(%R12),%XMM8    [14]

0x40c145 MOV	%R8,%RDI

0x40c148 VMOVUPS	%XMM8,(%R8,%R10,1)    [2]

0x40c14e MOV	0x20(%RAX),%RSI    [8]

0x40c152 LEA	(,%R13,8),%R8

0x40c15a LEA	(%R8,%R8,2),%R15

0x40c15e MOV	0x10(%RSI,%R15,1),%R8    [12]

0x40c163 MOV	%R8,0x10(%RSI,%R10,1)    [12]

0x40c168 VMOVUPS	(%RSI,%R15,1),%XMM8    [12]

0x40c16e VMOVUPS	%XMM8,(%RSI,%R10,1)    [12]

0x40c174 MOV	0x28(%RAX),%R8    [8]

0x40c178 MOV	0x10(%R8,%R15,1),%R9    [1]

0x40c17d MOV	%R9,0x10(%R8,%R10,1)    [1]

0x40c182 VMOVDQU	(%R8,%R15,1),%XMM8    [1]

0x40c188 VMOVDQU	%XMM8,(%R8,%R10,1)    [1]

0x40c18e MOV	0x30(%RAX),%R10    [8]

0x40c192 MOV	-0x58(%RBP),%RAX    [13]

0x40c196 MOV	(%R10,%R13,8),%R9    [5]

0x40c19a MOV	%R9,(%R10,%RDX,8)    [5]

0x40c19e MOV	(%RAX,%RBX,4),%EDX    [7]

0x40c1a1 LEA	0x1(%RDX),%R9D

0x40c1a5 MOV	%R9D,(%RAX,%RBX,4)    [7]

0x40c1a9 CMP	$0x3f,%EDX

0x40c1ac JGE	40c3c0

0x40c1b2 MOV	-0x50(%RBP),%RDX    [13]

0x40c1b6 MOVSXD	(%RAX,%RDX,4),%RBX    [7]

0x40c1ba DEC	%RBX

0x40c1bd MOV	%EBX,(%RAX,%RDX,4)    [7]

0x40c1c0 TEST	%EBX,%EBX

0x40c1c2 JE	40c23a

0x40c1c4 LEA	(%RSI,%R15,1),%RDX

0x40c1c8 ADD	-0x88(%RBP),%RBX    [13]

0x40c1cf MOV	(%R14,%RBX,4),%R9D    [15]

0x40c1d3 MOV	-0x90(%RBP),%R13    [13]

0x40c1da MOV	%R9D,(%R14,%R13,4)    [15]

0x40c1de MOV	(%R11,%RBX,4),%R9D    [11]

0x40c1e2 MOV	%R9D,(%R11,%R13,4)    [11]

0x40c1e6 ADD	%R8,%R15

0x40c1e9 LEA	(,%RBX,8),%R9

0x40c1f1 LEA	(%R9,%R9,2),%R9

0x40c1f5 MOV	0x10(%RDI,%R9,1),%R11    [4]

0x40c1fa MOV	%R11,0x10(%R12)    [14]

0x40c1ff VMOVUPS	(%RDI,%R9,1),%XMM8    [4]

0x40c205 VMOVUPS	%XMM8,(%R12)    [14]

0x40c20b MOV	0x10(%RSI,%R9,1),%R11    [12]

0x40c210 MOV	%R11,0x10(%RDX)    [17]

0x40c214 VMOVUPS	(%RSI,%R9,1),%XMM8    [12]

0x40c21a VMOVUPS	%XMM8,(%RDX)    [17]

0x40c21e MOV	0x10(%R8,%R9,1),%RDX    [1]

0x40c223 MOV	%RDX,0x10(%R15)    [16]

0x40c227 VMOVDQU	(%R8,%R9,1),%XMM8    [1]

0x40c22d VMOVDQU	%XMM8,(%R15)    [16]

0x40c232 MOV	(%R10,%RBX,8),%RDX    [5]

0x40c236 MOV	%RDX,(%R10,%R13,8)    [5]

0x40c23a MOV	-0xa0(%RBP),%R14    [13]

0x40c241 CMP	%ECX,%R14D

0x40c244 JGE	40c24c

0x40c246 MOV	-0x48(%RBP),%RCX    [13]

0x40c24a DECL	(%RCX)    [3]

0x40c24c MOV	-0x38(%RBP),%R15D    [13]

0x40c250 MOV	-0x50(%RBP),%R9    [13]

0x40c254 MOV	%RDI,%R10

0x40c257 MOV	-0x78(%RBP),%R11    [13]

0x40c25b MOV	-0x70(%RBP),%R13    [13]

0x40c25f MOV	-0x60(%RBP),%RBX    [13]

0x40c263 CMP	(%RAX,%R9,4),%EBX    [7]

0x40c267 JL	40bf50

0x40c280 IMUL	%R13D,%R15D

0x40c284 CMP	$-0x1,%ECX

0x40c287 JE	40c2c0

0x40c289 ADD	%ESI,%R15D

0x40c28c IMUL	%R11D,%R15D

0x40c290 JMP	40c0cb

0x40c2c0 ADD	%R14D,%ESI

0x40c2c3 ADD	%R15D,%ESI

0x40c2c6 MOV	%ESI,%ECX

0x40c2c8 JMP	40c0ce

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 371

--------------------------------------------------------------------------------

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

[...]

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

[...]

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

Coverage (%)	Name	Source Location	Module
►60.38+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►37.60+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►2.02+	redistributeAtoms	timestep.c:148	exec
○	main	CoMD.c:207	exec
○	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	2.60
CQA speedup if FP arith vectorized	2.51
CQA speedup if fully vectorized	11.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	micro-operation queue,
Function	updateLinkCells
Source	linkCells.c:209-221,linkCells.c:227-247,linkCells.c:258-269,linkCells.c:295-301,linkCells.c:327-334,linkCells.c:352-353,linkCells.c:359-365,linkCells.c:371-371
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.17
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.41
CQA cycles if fully vectorized	2.80
Front-end cycles	31.17
P0 cycles	17.80
P1 cycles	17.90
P2 cycles	21.00
P3 cycles	21.00
P4 cycles	11.50
P5 cycles	17.80
P6 cycles	17.70
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	17.80
P11 cycles	21.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	177.00
Nb uops	185.00
Nb loads	63.00
Nb stores	23.00
Nb stack references	17.00
FLOP/cycle	0.19
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.69
Bytes prefetched	0.00
Bytes loaded	472.00
Bytes stored	204.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	34.43
Vectorization ratio load	53.85
Vectorization ratio store	26.09
Vectorization ratio mul	50.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	14.45
Vector-efficiency ratio load	17.79
Vector-efficiency ratio store	13.86
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.00

Metric	Value
CQA speedup if no scalar integer	2.60
CQA speedup if FP arith vectorized	2.51
CQA speedup if fully vectorized	11.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	micro-operation queue,
Function	updateLinkCells
Source	linkCells.c:209-221,linkCells.c:227-247,linkCells.c:258-269,linkCells.c:295-301,linkCells.c:327-334,linkCells.c:352-353,linkCells.c:359-365,linkCells.c:371-371
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.17
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.41
CQA cycles if fully vectorized	2.80
Front-end cycles	31.17
P0 cycles	17.80
P1 cycles	17.90
P2 cycles	21.00
P3 cycles	21.00
P4 cycles	11.50
P5 cycles	17.80
P6 cycles	17.70
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	11.50
P10 cycles	17.80
P11 cycles	21.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	177.00
Nb uops	185.00
Nb loads	63.00
Nb stores	23.00
Nb stack references	17.00
FLOP/cycle	0.19
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.69
Bytes prefetched	0.00
Bytes loaded	472.00
Bytes stored	204.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	34.43
Vectorization ratio load	53.85
Vectorization ratio store	26.09
Vectorization ratio mul	50.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	14.45
Vector-efficiency ratio load	17.79
Vector-efficiency ratio store	13.86
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	updateLinkCells
Source file and lines	linkCells.c:209-371
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:209-221,227-247,258-269,295-301,327-334,352-353,359-365,371.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 70 paths individually, rerun with max-paths=70
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 70 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.17 to 12.00 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 31.17 to 2.80 cycles (11.15x speedup).

Details

34% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:269
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
VCVTTSD2SI: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
VPEXTRD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:215
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:234
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
VROUNDSD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 472 bytes (59 double precision FP elements). The binary loop is storing 204 bytes (25 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	177
nb uops	185
loop length	742
used x86 registers	15
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	17
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.17 cycles
front end	31.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	17.80	17.90	21.00	21.00	11.50	17.80	17.70	11.50	11.50	11.50	17.80	21.00
cycles	17.80	17.90	21.00	21.00	11.50	17.80	17.70	11.50	11.50	11.50	17.80	21.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.17
Dispatch	21.00
Overall L1	31.17

Vectorization ratios

INT

all	17%
load	40%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	70%
load	62%
store	100%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	34%
load	53%
store	26%
mul	50%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	11%
load	13%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	21%
load	20%
store	25%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	14%
load	17%
store	13%
mul	18%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.17 cycles. At this rate:

7% of peak load performance is reached (15.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 31.17 to 21.00 cycles (1.48x speedup).

ASM code

In the binary file, the address of the loop is: 40bf50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP (%RAX,%R9,4),%EBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40be80 <updateLinkCells+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EBX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %ECX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%RCX,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R10,%R12,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM8,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R11D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 40bf9b <updateLinkCells+0x1bb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBSD 0x18(%RAX),%XMM8,%XMM8	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMULSD 0x60(%RAX),%XMM8,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VROUNDSD $0x9,%XMM8,%XMM8,%XMM8	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM8,%ECX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ECX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE -0x64(%RBP),%ECX	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	1	0.50	N/A
VMOVUPD 0x8(%R10,%R12,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBPD %XMM3,%XMM9,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM4,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VROUNDPD $0x9,%XMM8,%XMM8	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VCVTTPD2DQ %XMM8,%XMM8	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (25.0%)
VPCMPEQD %XMM8,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VCMPPD $0x5,%XMM2,%XMM9,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVD %K0,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVDQA32 %XMM6,%XMM8{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVD %XMM8,%ESI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV %ESI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNE %R13D,%R8D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40c000 <updateLinkCells+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R13D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x3(%RDX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL -0x30(%RBP),%EDX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x2c(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x34(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40c0d1 <updateLinkCells+0x2f1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPEXTRD $0x1,%XMM8,%R15D	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
CMP $-0x1,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40c040 <updateLinkCells+0x260>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40c080 <updateLinkCells+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD -0x98(%RBP),%R15D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JMP 40c0c0 <updateLinkCells+0x2e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R8,%RDX,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL -0x30(%RBP),%EDX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x2c(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x34(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40c0ce <updateLinkCells+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
CMP $-0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40c0c0 <updateLinkCells+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %ECX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40c280 <updateLinkCells+0x4a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPADDD %XMM7,%XMM8,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPEXTRD $0x1,%XMM8,%EDX	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
IMUL %R13D,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %XMM8,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40c0ce <updateLinkCells+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
IMUL -0x30(%RBP),%R15D	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x2c(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x34(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 40c340 <updateLinkCells+0x560>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40c380 <updateLinkCells+0x5a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40bf40 <updateLinkCells+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD (%RAX,%RBX,4),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ECX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
SAL $0x6,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R13,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,(%R14,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11,%R13,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,(%R11,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%R10,%R12,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RSI,2),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x10(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%R12),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPS %XMM8,(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x20(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R13,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R8,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RSI,%R15,1),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,0x10(%RSI,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%RSI,%R15,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS %XMM8,(%RSI,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x28(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R8,%R15,1),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,0x10(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQU (%R8,%R15,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM8,(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x30(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R10,%R13,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,(%R10,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX,%RBX,4),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,(%RAX,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x3f,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40c3c0 <updateLinkCells+0x5e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX,%RDX,4),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EBX,(%RAX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40c23a <updateLinkCells+0x45a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RSI,%R15,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD -0x88(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV (%R14,%RBX,4),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9D,(%R14,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R11,%RBX,4),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9D,(%R11,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%RBX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RDI,%R9,1),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x10(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%RDI,%R9,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS %XMM8,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RSI,%R9,1),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x10(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%RSI,%R9,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS %XMM8,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%R8,%R9,1),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x10(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQU (%R8,%R9,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM8,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV (%R10,%RBX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,(%R10,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40c24c <updateLinkCells+0x46c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DECL (%RCX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x78(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RAX,%R9,4),%EBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JL 40bf50 <updateLinkCells+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R15D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
CMP $-0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40c2c0 <updateLinkCells+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %ESI,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R11D,%R15D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
JMP 40c0cb <updateLinkCells+0x2eb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R14D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 40c0ce <updateLinkCells+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	updateLinkCells
Source file and lines	linkCells.c:209-371
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 70 paths individually, rerun with max-paths=70
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

34% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:269
VCVTTPD2DQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
VCVTTSD2SI: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
VPEXTRD: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:215
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:234
VROUNDPD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
VROUNDSD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
VCVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 472 bytes (59 double precision FP elements). The binary loop is storing 204 bytes (25 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	177
nb uops	185
loop length	742
used x86 registers	15
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	17
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.17 cycles
front end	31.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	17.80	17.90	21.00	21.00	11.50	17.80	17.70	11.50	11.50	11.50	17.80	21.00
cycles	17.80	17.90	21.00	21.00	11.50	17.80	17.70	11.50	11.50	11.50	17.80	21.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.17
Dispatch	21.00
Overall L1	31.17

Vectorization ratios

INT

all	17%
load	40%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	70%
load	62%
store	100%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	34%
load	53%
store	26%
mul	50%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	11%
load	13%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	21%
load	20%
store	25%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	14%
load	17%
store	13%
mul	18%
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.17 cycles. At this rate:

7% of peak load performance is reached (15.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40bf50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP (%RAX,%R9,4),%EBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JGE 40be80 <updateLinkCells+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EBX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %ECX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RCX,%RCX,2),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R10,%R12,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUCOMISD %XMM8,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R11D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JBE 40bf9b <updateLinkCells+0x1bb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VSUBSD 0x18(%RAX),%XMM8,%XMM8	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMULSD 0x60(%RAX),%XMM8,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VROUNDSD $0x9,%XMM8,%XMM8,%XMM8	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM8,%ECX	2	1.50	0.50	0	0	0	0	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ECX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMOVE -0x64(%RBP),%ECX	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	1	0.50	N/A
VMOVUPD 0x8(%R10,%R12,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VSUBPD %XMM3,%XMM9,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMULPD %XMM4,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VROUNDPD $0x9,%XMM8,%XMM8	2	1	1	0	0	0	0	0	0	0	0	0	0	8	1	vect (25.0%)
VCVTTPD2DQ %XMM8,%XMM8	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	vect (25.0%)
VPCMPEQD %XMM8,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VCMPPD $0x5,%XMM2,%XMM9,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
KMOVD %K0,%EDX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVDQA32 %XMM6,%XMM8{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVD %XMM8,%ESI	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV %ESI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVNE %R13D,%R8D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40c000 <updateLinkCells+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R13D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x3(%RDX,%R8,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL -0x30(%RBP),%EDX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x2c(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x34(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40c0d1 <updateLinkCells+0x2f1>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPEXTRD $0x1,%XMM8,%R15D	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
CMP $-0x1,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40c040 <updateLinkCells+0x260>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40c080 <updateLinkCells+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD -0x98(%RBP),%R15D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JMP 40c0c0 <updateLinkCells+0x2e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x80(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R8,%RDX,1),%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL -0x30(%RBP),%EDX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x2c(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x34(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40c0ce <updateLinkCells+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
CMP $-0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40c0c0 <updateLinkCells+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %ECX,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40c280 <updateLinkCells+0x4a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPADDD %XMM7,%XMM8,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPEXTRD $0x1,%XMM8,%EDX	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (6.3%)
IMUL %R13D,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVD %XMM8,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40c0ce <updateLinkCells+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
IMUL -0x30(%RBP),%R15D	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD -0x2c(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD -0x34(%RBP),%ECX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 40c340 <updateLinkCells+0x560>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R15D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40c380 <updateLinkCells+0x5a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40bf40 <updateLinkCells+0x160>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD (%RAX,%RBX,4),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ECX,%RDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
SAL $0x6,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R13,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,(%R14,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R11,%R13,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,(%R11,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%R10,%R12,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RSI,2),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x10(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%R12),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPS %XMM8,(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x20(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R13,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R8,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RSI,%R15,1),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,0x10(%RSI,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%RSI,%R15,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS %XMM8,(%RSI,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x28(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%R8,%R15,1),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,0x10(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQU (%R8,%R15,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM8,(%R8,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x30(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R10,%R13,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,(%R10,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX,%RBX,4),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RDX),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,(%RAX,%RBX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x3f,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40c3c0 <updateLinkCells+0x5e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%RAX,%RDX,4),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EBX,(%RAX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %EBX,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40c23a <updateLinkCells+0x45a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RSI,%R15,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD -0x88(%RBP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV (%R14,%RBX,4),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9D,(%R14,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R11,%RBX,4),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9D,(%R11,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %R8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%RBX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R9,2),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RDI,%R9,1),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x10(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%RDI,%R9,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS %XMM8,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%RSI,%R9,1),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,0x10(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPS (%RSI,%R9,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS %XMM8,(%RDX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0x10(%R8,%R9,1),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x10(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQU (%R8,%R9,1),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM8,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV (%R10,%RBX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,(%R10,%R13,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %ECX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40c24c <updateLinkCells+0x46c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DECL (%RCX)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x78(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP (%RAX,%R9,4),%EBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JL 40bf50 <updateLinkCells+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %R13D,%R15D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
CMP $-0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40c2c0 <updateLinkCells+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %ESI,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R11D,%R15D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
JMP 40c0cb <updateLinkCells+0x2eb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
ADD %R14D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 40c0ce <updateLinkCells+0x2ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code