OV - exec - Function ljForce.extracted

	Function: ljForce.extracted	Module: exec	Source: ljForce.c:172-222 [...]	Coverage (incl. loops): 45.46% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 222

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

[...]

222:    } // loop over local boxes in system

0x40c820 PUSH	%RBP

0x40c821 MOV	%RSP,%RBP

0x40c824 PUSH	%R15

0x40c826 PUSH	%R14

0x40c828 PUSH	%R13

0x40c82a PUSH	%R12

0x40c82c PUSH	%RBX

0x40c82d SUB	$0x58,%RSP

0x40c831 MOV	%R9,%R14

0x40c834 MOV	%R8,%R13

0x40c837 MOV	%RCX,%R12

0x40c83a MOV	%RDX,-0x58(%RBP)

0x40c83e MOV	0x28(%RBP),%EAX

0x40c841 MOVL	$0,-0x44(%RBP)

0x40c848 MOV	%RDI,-0x68(%RBP)

0x40c84c MOV	(%RDI),%ESI

0x40c84e MOVL	$0,-0x30(%RBP)

0x40c855 MOV	%EAX,-0x2c(%RBP)

0x40c858 MOVL	$0x1,-0x40(%RBP)

0x40c85f SUB	$0x8,%RSP

0x40c863 LEA	-0x40(%RBP),%RAX

0x40c867 LEA	-0x44(%RBP),%RCX

0x40c86b LEA	-0x30(%RBP),%R8

0x40c86f LEA	-0x2c(%RBP),%R9

0x40c873 MOV	$0x422740,%EDI

0x40c878 MOV	%ESI,-0x3c(%RBP)

0x40c87b MOV	$0x22,%EDX

0x40c880 PUSH	$0x1

0x40c882 PUSH	$0x1

0x40c884 PUSH	%RAX

0x40c885 CALL	403250 <__kmpc_for_static_init_4@plt>

0x40c88a ADD	$0x20,%RSP

0x40c88e MOV	-0x30(%RBP),%ECX

0x40c891 MOV	-0x2c(%RBP),%EAX

0x40c894 VXORPD	%XMM5,%XMM5,%XMM5

0x40c898 MOV	%RAX,-0x50(%RBP)

0x40c89c CMP	%EAX,%ECX

0x40c89e JBE	40c940

0x40c8a4 MOV	0x30(%RBP),%R15

0x40c8a8 VMOVSD	%XMM5,-0x38(%RBP)

0x40c8ad MOV	$0x422760,%EDI

0x40c8b2 MOV	-0x3c(%RBP),%ESI

0x40c8b5 CALL	403100 <__kmpc_for_static_fini@plt>

0x40c8ba MOV	-0x68(%RBP),%RBX

0x40c8be MOV	(%RBX),%ESI

0x40c8c0 SUB	$0x8,%RSP

0x40c8c4 MOV	$0x423c00,%RAX

0x40c8cb LEA	-0x38(%RBP),%R8

0x40c8cf MOV	$0x4227a0,%EDI

0x40c8d4 MOV	$0x40c810,%R9D

0x40c8da MOV	$0x1,%EDX

0x40c8df MOV	$0x8,%ECX

0x40c8e4 PUSH	%RAX

0x40c8e5 CALL	403350 <__kmpc_reduce@plt>

0x40c8ea ADD	$0x10,%RSP

0x40c8ee CMP	$0x2,%EAX

0x40c8f1 JE	40ccc0

0x40c8f7 CMP	$0x1,%EAX

0x40c8fa JNE	40cce7

0x40c900 VMOVSD	-0x38(%RBP),%XMM0

0x40c905 VADDSD	(%R15),%XMM0,%XMM0

0x40c90a VMOVSD	%XMM0,(%R15)

0x40c90f MOV	(%RBX),%ESI

0x40c911 MOV	$0x423c00,%RDX

0x40c918 MOV	$0x4227c0,%EDI

0x40c91d JMP	40cce2

0x40c922 NOPW	%CS:(%RAX,%RAX,1)

0x40c931 NOPW	%CS:(%RAX,%RAX,1)

0x40c940 VMOVSD	0x10(%RBP),%XMM0

0x40c945 VMOVQ	%R14,%XMM1

0x40c94a VMOVQ	%R13,%XMM2

0x40c94f VMOVQ	%R12,%XMM3

0x40c954 MOV	-0x58(%RBP),%RAX

0x40c958 MOV	0x18(%RAX),%RAX

0x40c95c MOV	0x78(%RAX),%RDX

0x40c960 MOV	%RDX,-0x60(%RBP)

0x40c964 MOV	0x80(%RAX),%RAX

0x40c96b MOV	%RAX,-0x70(%RBP)

0x40c96f VMULSD	0xd049(%RIP),%XMM3,%XMM3

0x40c977 MOV	%ECX,%EDI

0x40c979 SAL	$0x6,%EDI

0x40c97c INCQ	-0x50(%RBP)

0x40c980 VXORPD	%XMM4,%XMM4,%XMM4

0x40c984 VMOVSD	0xb7dc(%RIP),%XMM6

0x40c98c VMOVSD	0xc8b4(%RIP),%XMM7

0x40c994 VMOVSD	0xd02c(%RIP),%XMM8

0x40c99c VMOVSD	0xd02c(%RIP),%XMM9

0x40c9a4 VMOVSD	0xd02c(%RIP),%XMM10

0x40c9ac JMP	40c9d4

0x40c9ae NOPW	%CS:(%RAX,%RAX,1)

0x40c9bd NOPL	(%RAX)

(85) 0x40c9c0 MOV	-0x78(%RBP),%RCX

(85) 0x40c9c4 INC	%RCX

(85) 0x40c9c7 ADD	$0x40,%EDI

(85) 0x40c9ca CMP	-0x50(%RBP),%RCX

(85) 0x40c9ce JE	40c8a4

(85) 0x40c9d4 MOV	%EDI,%EDI

(85) 0x40c9d6 MOV	-0x60(%RBP),%RAX

(85) 0x40c9da MOV	(%RAX,%RCX,4),%EAX

(85) 0x40c9dd MOV	-0x70(%RBP),%RDX

(85) 0x40c9e1 MOV	(%RDX,%RCX,8),%R8

(85) 0x40c9e5 TEST	%EAX,%EAX

(85) 0x40c9e7 MOV	%RCX,-0x78(%RBP)

(85) 0x40c9eb JLE	40cbc0

(85) 0x40c9f1 SAL	$0x6,%ECX

(85) 0x40c9f4 ADD	%ECX,%EAX

(85) 0x40c9f6 LEA	0x1(%RDI),%ECX

(85) 0x40c9f9 CMP	%ECX,%EAX

(85) 0x40c9fb CMOVLE	%ECX,%EAX

(85) 0x40c9fe MOV	%EDI,%R9D

(85) 0x40ca01 NOT	%R9D

(85) 0x40ca04 ADD	%EAX,%R9D

(85) 0x40ca07 XOR	%R10D,%R10D

(85) 0x40ca0a JMP	40ca4d

0x40ca0c NOPW	%CS:(%RAX,%RAX,1)

0x40ca1b NOPW	%CS:(%RAX,%RAX,1)

0x40ca2a NOPW	%CS:(%RAX,%RAX,1)

0x40ca39 NOPL	(%RAX)

  (86) 0x40ca40 INC	%R10

  (86) 0x40ca43 CMP	$0x1b,%R10

  (86) 0x40ca47 JE	40c9c0

  (86) 0x40ca4d MOVSXD	(%R8,%R10,4),%RAX

  (86) 0x40ca51 TEST	%RAX,%RAX

  (86) 0x40ca54 JS	40cca4

  (86) 0x40ca5a MOV	-0x60(%RBP),%RCX

  (86) 0x40ca5e MOV	(%RCX,%RAX,4),%ECX

  (86) 0x40ca61 TEST	%ECX,%ECX

  (86) 0x40ca63 JLE	40ca40

  (86) 0x40ca65 SAL	$0x6,%EAX

  (86) 0x40ca68 MOV	-0x58(%RBP),%RDX

  (86) 0x40ca6c MOV	0x20(%RDX),%R11

  (86) 0x40ca70 MOV	0x18(%R11),%R14

  (86) 0x40ca74 DEC	%ECX

  (86) 0x40ca76 LEA	(%RCX,%RCX,2),%RCX

  (86) 0x40ca7a LEA	0x18(,%RCX,8),%R12

  (86) 0x40ca82 LEA	(%RAX,%RAX,2),%RAX

  (86) 0x40ca86 LEA	0x10(%R14,%RAX,8),%R13

  (86) 0x40ca8b XOR	%EBX,%EBX

  (86) 0x40ca8d JMP	40cacd

0x40ca8f NOPW	%CS:(%RAX,%RAX,1)

0x40ca9e NOPW	%CS:(%RAX,%RAX,1)

0x40caad NOPW	%CS:(%RAX,%RAX,1)

0x40cabc NOPL	(%RAX)

    (87) 0x40cac0 CMP	%R9,%RBX

    (87) 0x40cac3 LEA	0x1(%RBX),%RBX

    (87) 0x40cac7 JE	40ca40

    (87) 0x40cacd LEA	(%RBX,%RDI,1),%RSI

    (87) 0x40cad1 LEA	(%RSI,%RSI,2),%RCX

    (87) 0x40cad5 LEA	(%R14,%RCX,8),%RAX

    (87) 0x40cad9 XOR	%R15D,%R15D

    (87) 0x40cadc JMP	40cb09

0x40cade NOPW	%CS:(%RAX,%RAX,1)

0x40caed NOPW	%CS:(%RAX,%RAX,1)

0x40cafc NOPL	(%RAX)

      (88) 0x40cb00 ADD	$0x18,%R15

      (88) 0x40cb04 CMP	%R15,%R12

      (88) 0x40cb07 JE	40cac0

      (88) 0x40cb09 VMOVUPD	(%RAX),%XMM11

      (88) 0x40cb0d VSUBPD	-0x10(%R13,%R15,1),%XMM11,%XMM11

      (88) 0x40cb14 VMULPD	%XMM11,%XMM11,%XMM12

      (88) 0x40cb19 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

      (88) 0x40cb1f VADDSD	%XMM12,%XMM13,%XMM13

      (88) 0x40cb24 VMOVSD	0x10(%RAX),%XMM12

      (88) 0x40cb29 VSUBSD	(%R13,%R15,1),%XMM12,%XMM12

      (88) 0x40cb30 VFMADD231SD	%XMM12,%XMM12,%XMM13

      (88) 0x40cb35 VUCOMISD	%XMM13,%XMM2

      (88) 0x40cb3a JB	40cb00

      (88) 0x40cb3c VUCOMISD	%XMM4,%XMM13

      (88) 0x40cb40 JBE	40cb00

      (88) 0x40cb42 VDIVSD	%XMM13,%XMM6,%XMM13

      (88) 0x40cb47 VMULSD	%XMM13,%XMM13,%XMM14

      (88) 0x40cb4c VMULSD	%XMM1,%XMM13,%XMM15

      (88) 0x40cb50 VMULSD	%XMM15,%XMM14,%XMM14

      (88) 0x40cb55 VADDSD	%XMM7,%XMM14,%XMM15

      (88) 0x40cb59 VFNMADD213SD	%XMM0,%XMM14,%XMM15

      (88) 0x40cb5e VMULSD	%XMM8,%XMM15,%XMM15

      (88) 0x40cb63 MOV	0x30(%R11),%RDX

      (88) 0x40cb67 VADDSD	(%RDX,%RSI,8),%XMM15,%XMM16

      (88) 0x40cb6e VMOVSD	%XMM16,(%RDX,%RSI,8)

      (88) 0x40cb75 VMOVAPD	%XMM9,%XMM16

      (88) 0x40cb7b VFMADD213SD	%XMM10,%XMM14,%XMM16

      (88) 0x40cb81 VMULSD	%XMM3,%XMM13,%XMM13

      (88) 0x40cb85 VMULSD	%XMM14,%XMM13,%XMM13

      (88) 0x40cb8a VMULSD	%XMM16,%XMM13,%XMM13

      (88) 0x40cb90 MOV	0x28(%R11),%RDX

      (88) 0x40cb94 VMOVDDUP	%XMM13,%XMM14

      (88) 0x40cb99 VFMADD213PD	(%RDX,%RCX,8),%XMM14,%XMM11

      (88) 0x40cb9f VMOVUPD	%XMM11,(%RDX,%RCX,8)

      (88) 0x40cba4 VFMADD213SD	0x10(%RDX,%RCX,8),%XMM13,%XMM12

      (88) 0x40cbab VMOVSD	%XMM12,0x10(%RDX,%RCX,8)

      (88) 0x40cbb1 VADDSD	%XMM5,%XMM15,%XMM5

      (88) 0x40cbb5 JMP	40cb00

0x40cbba NOPW	(%RAX,%RAX,1)

(85) 0x40cbc0 CMPL	$0,(%R8)

(85) 0x40cbc4 JS	40cca4

(85) 0x40cbca CMPL	$0,0x4(%R8)

(85) 0x40cbcf JS	40cca4

(85) 0x40cbd5 CMPL	$0,0x8(%R8)

(85) 0x40cbda JS	40cca4

(85) 0x40cbe0 CMPL	$0,0xc(%R8)

(85) 0x40cbe5 JS	40cca4

(85) 0x40cbeb CMPL	$0,0x10(%R8)

(85) 0x40cbf0 JS	40cca4

(85) 0x40cbf6 CMPL	$0,0x14(%R8)

(85) 0x40cbfb JS	40cca4

(85) 0x40cc01 CMPL	$0,0x18(%R8)

(85) 0x40cc06 JS	40cca4

(85) 0x40cc0c CMPL	$0,0x1c(%R8)

(85) 0x40cc11 JS	40cca4

(85) 0x40cc17 CMPL	$0,0x20(%R8)

(85) 0x40cc1c JS	40cca4

(85) 0x40cc22 CMPL	$0,0x24(%R8)

(85) 0x40cc27 JS	40cca4

(85) 0x40cc29 CMPL	$0,0x28(%R8)

(85) 0x40cc2e JS	40cca4

(85) 0x40cc30 CMPL	$0,0x2c(%R8)

(85) 0x40cc35 JS	40cca4

(85) 0x40cc37 CMPL	$0,0x30(%R8)

(85) 0x40cc3c JS	40cca4

(85) 0x40cc3e CMPL	$0,0x34(%R8)

(85) 0x40cc43 JS	40cca4

(85) 0x40cc45 CMPL	$0,0x38(%R8)

(85) 0x40cc4a JS	40cca4

(85) 0x40cc4c CMPL	$0,0x3c(%R8)

(85) 0x40cc51 JS	40cca4

(85) 0x40cc53 CMPL	$0,0x40(%R8)

(85) 0x40cc58 JS	40cca4

(85) 0x40cc5a CMPL	$0,0x44(%R8)

(85) 0x40cc5f JS	40cca4

(85) 0x40cc61 CMPL	$0,0x48(%R8)

(85) 0x40cc66 JS	40cca4

(85) 0x40cc68 CMPL	$0,0x4c(%R8)

(85) 0x40cc6d JS	40cca4

(85) 0x40cc6f CMPL	$0,0x50(%R8)

(85) 0x40cc74 JS	40cca4

(85) 0x40cc76 CMPL	$0,0x54(%R8)

(85) 0x40cc7b JS	40cca4

(85) 0x40cc7d CMPL	$0,0x58(%R8)

(85) 0x40cc82 JS	40cca4

(85) 0x40cc84 CMPL	$0,0x5c(%R8)

(85) 0x40cc89 JS	40cca4

(85) 0x40cc8b CMPL	$0,0x60(%R8)

(85) 0x40cc90 JS	40cca4

(85) 0x40cc92 CMPL	$0,0x64(%R8)

(85) 0x40cc97 JS	40cca4

(85) 0x40cc99 CMPL	$0,0x68(%R8)

(85) 0x40cc9e JNS	40c9c0

0x40cca4 MOV	$0x4199e3,%EDI

0x40cca9 MOV	$0x4199eb,%ESI

0x40ccae MOV	$0x419a44,%ECX

0x40ccb3 MOV	$0xb6,%EDX

0x40ccb8 CALL	4030c0 <__assert_fail@plt>

0x40ccbd NOPL	(%RAX)

0x40ccc0 VMOVSD	-0x38(%RBP),%XMM0

0x40ccc5 MOV	(%RBX),%ESI

0x40ccc7 MOV	$0x422780,%EDI

0x40cccc MOV	%R15,%RDX

0x40cccf CALL	403160 <__kmpc_atomic_float8_add@plt>

0x40ccd4 MOV	(%RBX),%ESI

0x40ccd6 MOV	$0x423c00,%RDX

0x40ccdd MOV	$0x4227e0,%EDI

0x40cce2 CALL	4033b0 <__kmpc_end_reduce@plt>

0x40cce7 ADD	$0x58,%RSP

0x40cceb POP	%RBX

0x40ccec POP	%R12

0x40ccee POP	%R13

0x40ccf0 POP	%R14

0x40ccf2 POP	%R15

0x40ccf4 POP	%RBP

0x40ccf5 RET

0x40ccf6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►99.98+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	ljForce.c:172-222
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216,222.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.50 to 4.33 cycles (5.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 22.50 to 1.62 cycles (13.92x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
__kmpc_atomic_float8_add@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

1: addition or subtraction
1: multiply

The binary function is loading 172 bytes (21 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	127
nb uops	135
loop length	649
used x86 registers	14
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.50 cycles
front end	22.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.20	6.30	11.00	11.00	14.50	6.20	6.10	14.50	14.50	14.50	6.20	11.00
cycles	6.20	6.30	11.00	11.00	14.50	6.20	6.10	14.50	14.50	14.50	6.20	11.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.50
Dispatch	14.50
Overall L1	22.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	10%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.50 cycles. At this rate:

3% of peak load performance is reached (7.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.50 to 14.50 cycles (1.55x speedup).

ASM code

In the binary file, the address of the function is: 40c820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDI,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x422740,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40c940 <ljForce.extracted+0x120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM5,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x422760,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 403100 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x423c00,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4227a0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x40c810,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403350 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40ccc0 <ljForce.extracted+0x4a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40cce7 <ljForce.extracted+0x4c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R15),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x423c00,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4227c0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40cce2 <ljForce.extracted+0x4c2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x10(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ %R14,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVQ %R13,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVQ %R12,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD 0xd049(%RIP),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%EDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INCQ -0x50(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0xb7dc(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc8b4(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd02c(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd02c(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd02c(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 40c9d4 <ljForce.extracted+0x1b4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4199e3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4199eb,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x419a44,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xb6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x422780,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 403160 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x423c00,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4227e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4033b0 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	ljForce.c:172-222
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216,222.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.50 to 4.33 cycles (5.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
__kmpc_atomic_float8_add@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

1: addition or subtraction
1: multiply

The binary function is loading 172 bytes (21 double precision FP elements). The binary function is storing 84 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	127
nb uops	135
loop length	649
used x86 registers	14
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	14
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.50 cycles
front end	22.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.20	6.30	11.00	11.00	14.50	6.20	6.10	14.50	14.50	14.50	6.20	11.00
cycles	6.20	6.30	11.00	11.00	14.50	6.20	6.10	14.50	14.50	14.50	6.20	11.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.50
Dispatch	14.50
Overall L1	22.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	14%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

INT

all	8%
load	7%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	10%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.50 cycles. At this rate:

3% of peak load performance is reached (7.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40c820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDI,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVL $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x44(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x30(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x2c(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x422740,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403250 <__kmpc_for_static_init_4@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x2c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %EAX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 40c940 <ljForce.extracted+0x120>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM5,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x422760,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 403100 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x68(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x423c00,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x38(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4227a0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x40c810,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 403350 <__kmpc_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40ccc0 <ljForce.extracted+0x4a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40cce7 <ljForce.extracted+0x4c7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDSD (%R15),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x423c00,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4227c0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40cce2 <ljForce.extracted+0x4c2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x10(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ %R14,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVQ %R13,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVQ %R12,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD 0xd049(%RIP),%XMM3,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%EDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INCQ -0x50(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0xb7dc(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xc8b4(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd02c(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd02c(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xd02c(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 40c9d4 <ljForce.extracted+0x1b4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4199e3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4199eb,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x419a44,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xb6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x422780,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R15,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 403160 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%RBX),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV $0x423c00,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4227e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4033b0 <__kmpc_end_reduce@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼ljForce.extracted–	45.46	2.20
▼Loop 85 - ljForce.c:172-222 - exec–	0.01	0.01
▼Loop 86 - ljForce.c:178-216 - exec–	0.18	0.01
▼Loop 87 - ljForce.c:187-216 - exec–	0.61	0.03
○Loop 88 - ljForce.c:191-216 - exec	44.65	2.15

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FMA

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Cycles summary

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Cycles and memory resources usage

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