OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:209-385 [...]	Coverage (incl. loops): 0.44% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 209 - 385

--------------------------------------------------------------------------------

209:    if (iz == gridSize[2])

210:    {

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

[...]

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

[...]

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40bde0 PUSH	%RBP

0x40bde1 MOV	%RSP,%RBP

0x40bde4 PUSH	%R15

0x40bde6 PUSH	%R14

0x40bde8 PUSH	%R13

0x40bdea PUSH	%R12

0x40bdec PUSH	%RBX

0x40bded SUB	$0x78,%RSP

0x40bdf1 MOV	%RSI,-0x48(%RBP)

0x40bdf5 MOV	0xc(%RDI),%R14D

0x40bdf9 MOV	%RDI,-0x40(%RBP)

0x40bdfd MOV	0x14(%RDI),%R15D

0x40be01 CMP	%R15D,%R14D

0x40be04 MOV	%R15D,-0x38(%RBP)

0x40be08 JGE	40be34

0x40be0a MOVSXD	%R14D,%RDI

0x40be0d SAL	$0x2,%RDI

0x40be11 MOV	-0x40(%RBP),%RAX

0x40be15 ADD	0x78(%RAX),%RDI

0x40be19 MOV	%R14D,%EAX

0x40be1c NOT	%EAX

0x40be1e ADD	%R15D,%EAX

0x40be21 LEA	0x4(,%RAX,4),%RDX

0x40be29 XOR	%ESI,%ESI

0x40be2b CALL	4157a0 <__intel_avx_rep_memset>

0x40be30 MOV	-0x38(%RBP),%R15D

0x40be34 TEST	%R14D,%R14D

0x40be37 JLE	40c300

0x40be3d MOV	-0x40(%RBP),%RAX

0x40be41 MOV	0x78(%RAX),%RAX

0x40be45 LEA	0x1(%R14),%ECX

0x40be49 MOV	%ECX,-0x2c(%RBP)

0x40be4c XOR	%R9D,%R9D

0x40be4f VPCMPEQD	%XMM0,%XMM0,%XMM0

0x40be53 MOV	%RAX,-0x58(%RBP)

0x40be57 MOV	%R14,-0xa0(%RBP)

0x40be5e JMP	40be8c

0x40be60 NOPW	%CS:(%RAX,%RAX,1)

0x40be6f NOPW	%CS:(%RAX,%RAX,1)

0x40be7e XCHG	%AX,%AX

(81) 0x40be80 INC	%R9

(81) 0x40be83 CMP	%R14,%R9

(81) 0x40be86 JE	40c300

(81) 0x40be8c CMPL	$0,(%RAX,%R9,4)

(81) 0x40be91 JLE	40be80

(81) 0x40be93 MOVSXD	%R9D,%RCX

(81) 0x40be96 SAL	$0x6,%RCX

(81) 0x40be9a MOV	%RCX,-0x88(%RBP)

(81) 0x40bea1 MOV	-0x48(%RBP),%RCX

(81) 0x40bea5 MOV	0x18(%RCX),%R10

(81) 0x40bea9 MOV	-0x40(%RBP),%RAX

(81) 0x40bead VMOVSD	0x30(%RAX),%XMM1

(81) 0x40beb2 MOV	(%RAX),%R11D

(81) 0x40beb5 LEA	-0x1(%R11),%ECX

(81) 0x40beb9 MOV	%ECX,-0x64(%RBP)

(81) 0x40bebc VMOVUPD	0x38(%RAX),%XMM2

(81) 0x40bec1 VMOVUPD	0x20(%RAX),%XMM3

(81) 0x40bec6 VMOVUPD	0x68(%RAX),%XMM4

(81) 0x40becb MOV	0x4(%RAX),%R13

(81) 0x40becf MOV	-0x58(%RBP),%RAX

(81) 0x40bed3 VMOVQ	%R13,%XMM5

(81) 0x40bed8 MOV	%R13,%RCX

(81) 0x40bedb SHR	$0x20,%RCX

(81) 0x40bedf VPADDD	%XMM0,%XMM5,%XMM6

(81) 0x40bee3 MOV	%RCX,-0x98(%RBP)

(81) 0x40beea LEA	(%RCX,%RCX,1),%EDX

(81) 0x40beed MOV	%RDX,%RCX

(81) 0x40bef0 MOV	%RDX,-0x80(%RBP)

(81) 0x40bef4 IMUL	%R13D,%ECX

(81) 0x40bef8 MOV	%ECX,-0x34(%RBP)

(81) 0x40befb LEA	0x2(%R11),%ECX

(81) 0x40beff MOV	%ECX,-0x30(%RBP)

(81) 0x40bf02 VPINSRD	$0,%R14D,%XMM5,%XMM7

(81) 0x40bf08 XOR	%EBX,%EBX

(81) 0x40bf0a MOV	%R11,-0x78(%RBP)

(81) 0x40bf0e MOV	%R13,-0x70(%RBP)

(81) 0x40bf12 MOV	%R9,-0x50(%RBP)

(81) 0x40bf16 JMP	40bf50

0x40bf18 NOPW	%CS:(%RAX,%RAX,1)

0x40bf27 NOPW	%CS:(%RAX,%RAX,1)

0x40bf36 NOPW	%CS:(%RAX,%RAX,1)

  (82) 0x40bf40 MOV	-0x60(%RBP),%RBX

  (82) 0x40bf44 INC	%EBX

  (82) 0x40bf46 CMP	(%RAX,%R9,4),%EBX

  (82) 0x40bf4a JGE	40be80

  (82) 0x40bf50 MOV	-0x88(%RBP),%RCX

  (82) 0x40bf57 ADD	%EBX,%ECX

  (82) 0x40bf59 MOVSXD	%ECX,%RCX

  (82) 0x40bf5c MOV	%RCX,-0x90(%RBP)

  (82) 0x40bf63 LEA	(%RCX,%RCX,2),%R12

  (82) 0x40bf67 VMOVSD	(%R10,%R12,8),%XMM8

  (82) 0x40bf6d VUCOMISD	%XMM8,%XMM1

  (82) 0x40bf72 MOV	%R11D,%ECX

  (82) 0x40bf75 JBE	40bf9b

  (82) 0x40bf77 MOV	-0x40(%RBP),%RAX

  (82) 0x40bf7b VSUBSD	0x18(%RAX),%XMM8,%XMM8

  (82) 0x40bf80 VMULSD	0x60(%RAX),%XMM8,%XMM8

  (82) 0x40bf85 MOV	-0x58(%RBP),%RAX

  (82) 0x40bf89 VROUNDSD	$0x9,%XMM8,%XMM8,%XMM8

  (82) 0x40bf8f VCVTTSD2SI	%XMM8,%ECX

  (82) 0x40bf94 CMP	%ECX,%R11D

  (82) 0x40bf97 CMOVE	-0x64(%RBP),%ECX

  (82) 0x40bf9b VMOVUPD	0x8(%R10,%R12,8),%XMM9

  (82) 0x40bfa2 VSUBPD	%XMM3,%XMM9,%XMM8

  (82) 0x40bfa6 VMULPD	%XMM4,%XMM8,%XMM8

  (82) 0x40bfaa VROUNDPD	$0x9,%XMM8,%XMM8

  (82) 0x40bfb0 VCVTTPD2DQ	%XMM8,%XMM8

  (82) 0x40bfb5 VPCMPEQD	%XMM8,%XMM5,%K1

  (82) 0x40bfbb VCMPPD	$0x5,%XMM2,%XMM9,%K0

  (82) 0x40bfc2 KMOVD	%K0,%EDX

  (82) 0x40bfc6 VMOVDQA32	%XMM6,%XMM8{%K1}

  (82) 0x40bfcc VMOVD	%XMM8,%ESI

  (82) 0x40bfd0 TEST	$0x1,%DL

  (82) 0x40bfd3 MOV	%ESI,%R8D

  (82) 0x40bfd6 CMOVNE	%R13D,%R8D

  (82) 0x40bfda TEST	$0x2,%DL

  (82) 0x40bfdd JE	40c000

  (82) 0x40bfdf ADD	%R13D,%R8D

  (82) 0x40bfe2 MOV	-0x80(%RBP),%RDX

  (82) 0x40bfe6 LEA	0x3(%RDX,%R8,1),%EDX

  (82) 0x40bfeb IMUL	-0x30(%RBP),%EDX

  (82) 0x40bfef ADD	-0x2c(%RBP),%ECX

  (82) 0x40bff2 ADD	-0x34(%RBP),%ECX

  (82) 0x40bff5 ADD	%EDX,%ECX

  (82) 0x40bff7 JMP	40c0d1

0x40bffc NOPL	(%RAX)

  (82) 0x40c000 MOV	%R15D,%EDI

  (82) 0x40c003 VPEXTRD	$0x1,%XMM8,%R15D

  (82) 0x40c009 CMP	$-0x1,%R15D

  (82) 0x40c00d JE	40c040

  (82) 0x40c00f TEST	$0x1,%DL

  (82) 0x40c012 JE	40c080

  (82) 0x40c014 ADD	-0x98(%RBP),%R15D

  (82) 0x40c01b JMP	40c0c0

0x40c020 NOPW	%CS:(%RAX,%RAX,1)

0x40c02f NOPW	%CS:(%RAX,%RAX,1)

0x40c03e XCHG	%AX,%AX

  (82) 0x40c040 MOV	-0x80(%RBP),%RDX

  (82) 0x40c044 LEA	0x1(%R8,%RDX,1),%EDX

  (82) 0x40c049 IMUL	-0x30(%RBP),%EDX

  (82) 0x40c04d ADD	-0x2c(%RBP),%ECX

  (82) 0x40c050 ADD	-0x34(%RBP),%ECX

  (82) 0x40c053 ADD	%EDX,%ECX

  (82) 0x40c055 JMP	40c0ce

0x40c057 NOPW	%CS:(%RAX,%RAX,1)

0x40c066 NOPW	%CS:(%RAX,%RAX,1)

0x40c075 NOPW	%CS:(%RAX,%RAX,1)

  (82) 0x40c080 CMP	$-0x1,%ESI

  (82) 0x40c083 JE	40c0c0

  (82) 0x40c085 CMP	%ECX,%R11D

  (82) 0x40c088 JNE	40c280

  (82) 0x40c08e VPADDD	%XMM7,%XMM8,%XMM8

  (82) 0x40c092 VPEXTRD	$0x1,%XMM8,%EDX

  (82) 0x40c098 IMUL	%R13D,%EDX

  (82) 0x40c09c VMOVD	%XMM8,%ECX

  (82) 0x40c0a0 ADD	%EDX,%ECX

  (82) 0x40c0a2 JMP	40c0ce

0x40c0a4 NOPW	%CS:(%RAX,%RAX,1)

0x40c0b3 NOPW	%CS:(%RAX,%RAX,1)

  (82) 0x40c0c0 IMUL	-0x30(%RBP),%R15D

  (82) 0x40c0c5 ADD	-0x2c(%RBP),%ECX

  (82) 0x40c0c8 ADD	-0x34(%RBP),%ECX

  (82) 0x40c0cb ADD	%R15D,%ECX

  (82) 0x40c0ce MOV	%EDI,%R15D

  (82) 0x40c0d1 TEST	%ECX,%ECX

  (82) 0x40c0d3 JS	40c340

  (82) 0x40c0d9 CMP	%R15D,%ECX

  (82) 0x40c0dc JGE	40c380

  (82) 0x40c0e2 MOV	%RBX,-0x60(%RBP)

  (82) 0x40c0e6 MOV	%ECX,%EBX

  (82) 0x40c0e8 CMP	%RBX,%R9

  (82) 0x40c0eb JE	40bf40

  (82) 0x40c0f1 MOVSXD	(%RAX,%RBX,4),%RSI

  (82) 0x40c0f5 MOVSXD	%ECX,%RDX

  (82) 0x40c0f8 SAL	$0x6,%RDX

  (82) 0x40c0fc ADD	%RSI,%RDX

  (82) 0x40c0ff MOV	-0x48(%RBP),%RAX

  (82) 0x40c103 MOV	0x8(%RAX),%R14

  (82) 0x40c107 MOV	-0x90(%RBP),%R13

  (82) 0x40c10e MOV	(%R14,%R13,4),%ESI

  (82) 0x40c112 MOV	%ESI,(%R14,%RDX,4)

  (82) 0x40c116 MOV	0x10(%RAX),%R11

  (82) 0x40c11a MOV	(%R11,%R13,4),%ESI

  (82) 0x40c11e MOV	%ESI,(%R11,%RDX,4)

  (82) 0x40c122 LEA	(%R10,%R12,8),%R12

  (82) 0x40c126 LEA	(,%RDX,8),%RSI

  (82) 0x40c12e MOV	%R10,%R8

  (82) 0x40c131 LEA	(%RSI,%RSI,2),%R10

  (82) 0x40c135 MOV	0x10(%R12),%RSI

  (82) 0x40c13a MOV	%RSI,0x10(%R8,%R10,1)

  (82) 0x40c13f VMOVUPS	(%R12),%XMM8

  (82) 0x40c145 MOV	%R8,%RDI

  (82) 0x40c148 VMOVUPS	%XMM8,(%R8,%R10,1)

  (82) 0x40c14e MOV	0x20(%RAX),%RSI

  (82) 0x40c152 LEA	(,%R13,8),%R8

  (82) 0x40c15a LEA	(%R8,%R8,2),%R15

  (82) 0x40c15e MOV	0x10(%RSI,%R15,1),%R8

  (82) 0x40c163 MOV	%R8,0x10(%RSI,%R10,1)

  (82) 0x40c168 VMOVUPS	(%RSI,%R15,1),%XMM8

  (82) 0x40c16e VMOVUPS	%XMM8,(%RSI,%R10,1)

  (82) 0x40c174 MOV	0x28(%RAX),%R8

  (82) 0x40c178 MOV	0x10(%R8,%R15,1),%R9

  (82) 0x40c17d MOV	%R9,0x10(%R8,%R10,1)

  (82) 0x40c182 VMOVDQU	(%R8,%R15,1),%XMM8

  (82) 0x40c188 VMOVDQU	%XMM8,(%R8,%R10,1)

  (82) 0x40c18e MOV	0x30(%RAX),%R10

  (82) 0x40c192 MOV	-0x58(%RBP),%RAX

  (82) 0x40c196 MOV	(%R10,%R13,8),%R9

  (82) 0x40c19a MOV	%R9,(%R10,%RDX,8)

  (82) 0x40c19e MOV	(%RAX,%RBX,4),%EDX

  (82) 0x40c1a1 LEA	0x1(%RDX),%R9D

  (82) 0x40c1a5 MOV	%R9D,(%RAX,%RBX,4)

  (82) 0x40c1a9 CMP	$0x3f,%EDX

  (82) 0x40c1ac JGE	40c3c0

  (82) 0x40c1b2 MOV	-0x50(%RBP),%RDX

  (82) 0x40c1b6 MOVSXD	(%RAX,%RDX,4),%RBX

  (82) 0x40c1ba DEC	%RBX

  (82) 0x40c1bd MOV	%EBX,(%RAX,%RDX,4)

  (82) 0x40c1c0 TEST	%EBX,%EBX

  (82) 0x40c1c2 JE	40c23a

  (82) 0x40c1c4 LEA	(%RSI,%R15,1),%RDX

  (82) 0x40c1c8 ADD	-0x88(%RBP),%RBX

  (82) 0x40c1cf MOV	(%R14,%RBX,4),%R9D

  (82) 0x40c1d3 MOV	-0x90(%RBP),%R13

  (82) 0x40c1da MOV	%R9D,(%R14,%R13,4)

  (82) 0x40c1de MOV	(%R11,%RBX,4),%R9D

  (82) 0x40c1e2 MOV	%R9D,(%R11,%R13,4)

  (82) 0x40c1e6 ADD	%R8,%R15

  (82) 0x40c1e9 LEA	(,%RBX,8),%R9

  (82) 0x40c1f1 LEA	(%R9,%R9,2),%R9

  (82) 0x40c1f5 MOV	0x10(%RDI,%R9,1),%R11

  (82) 0x40c1fa MOV	%R11,0x10(%R12)

  (82) 0x40c1ff VMOVUPS	(%RDI,%R9,1),%XMM8

  (82) 0x40c205 VMOVUPS	%XMM8,(%R12)

  (82) 0x40c20b MOV	0x10(%RSI,%R9,1),%R11

  (82) 0x40c210 MOV	%R11,0x10(%RDX)

  (82) 0x40c214 VMOVUPS	(%RSI,%R9,1),%XMM8

  (82) 0x40c21a VMOVUPS	%XMM8,(%RDX)

  (82) 0x40c21e MOV	0x10(%R8,%R9,1),%RDX

  (82) 0x40c223 MOV	%RDX,0x10(%R15)

  (82) 0x40c227 VMOVDQU	(%R8,%R9,1),%XMM8

  (82) 0x40c22d VMOVDQU	%XMM8,(%R15)

  (82) 0x40c232 MOV	(%R10,%RBX,8),%RDX

  (82) 0x40c236 MOV	%RDX,(%R10,%R13,8)

  (82) 0x40c23a MOV	-0xa0(%RBP),%R14

  (82) 0x40c241 CMP	%ECX,%R14D

  (82) 0x40c244 JGE	40c24c

  (82) 0x40c246 MOV	-0x48(%RBP),%RCX

  (82) 0x40c24a DECL	(%RCX)

  (82) 0x40c24c MOV	-0x38(%RBP),%R15D

  (82) 0x40c250 MOV	-0x50(%RBP),%R9

  (82) 0x40c254 MOV	%RDI,%R10

  (82) 0x40c257 MOV	-0x78(%RBP),%R11

  (82) 0x40c25b MOV	-0x70(%RBP),%R13

  (82) 0x40c25f MOV	-0x60(%RBP),%RBX

  (82) 0x40c263 CMP	(%RAX,%R9,4),%EBX

  (82) 0x40c267 JL	40bf50

(81) 0x40c26d JMP	40be80

0x40c272 NOPW	%CS:(%RAX,%RAX,1)

  (82) 0x40c280 IMUL	%R13D,%R15D

  (82) 0x40c284 CMP	$-0x1,%ECX

  (82) 0x40c287 JE	40c2c0

  (82) 0x40c289 ADD	%ESI,%R15D

  (82) 0x40c28c IMUL	%R11D,%R15D

  (82) 0x40c290 JMP	40c0cb

0x40c295 NOPW	%CS:(%RAX,%RAX,1)

0x40c2a4 NOPW	%CS:(%RAX,%RAX,1)

0x40c2b3 NOPW	%CS:(%RAX,%RAX,1)

  (82) 0x40c2c0 ADD	%R14D,%ESI

  (82) 0x40c2c3 ADD	%R15D,%ESI

  (82) 0x40c2c6 MOV	%ESI,%ECX

  (82) 0x40c2c8 JMP	40c0ce

0x40c2cd NOPW	%CS:(%RAX,%RAX,1)

0x40c2dc NOPW	%CS:(%RAX,%RAX,1)

0x40c2eb NOPW	%CS:(%RAX,%RAX,1)

0x40c2fa NOPW	(%RAX,%RAX,1)

0x40c300 ADD	$0x78,%RSP

0x40c304 POP	%RBX

0x40c305 POP	%R12

0x40c307 POP	%R13

0x40c309 POP	%R14

0x40c30b POP	%R15

0x40c30d POP	%RBP

0x40c30e RET

0x40c30f NOPW	%CS:(%RAX,%RAX,1)

0x40c31e NOPW	%CS:(%RAX,%RAX,1)

0x40c32d NOPW	%CS:(%RAX,%RAX,1)

0x40c33c NOPL	(%RAX)

0x40c340 MOV	$0x4198f4,%EDI

0x40c345 MOV	$0x41981e,%ESI

0x40c34a MOV	$0x4198fe,%ECX

0x40c34f MOV	$0xf6,%EDX

0x40c354 CALL	4030c0 <__assert_fail@plt>

0x40c359 NOPW	%CS:(%RAX,%RAX,1)

0x40c368 NOPW	%CS:(%RAX,%RAX,1)

0x40c377 NOPW	(%RAX,%RAX,1)

0x40c380 MOV	$0x41992d,%EDI

0x40c385 MOV	$0x41981e,%ESI

0x40c38a MOV	$0x4198fe,%ECX

0x40c38f MOV	$0xf7,%EDX

0x40c394 CALL	4030c0 <__assert_fail@plt>

0x40c399 NOPW	%CS:(%RAX,%RAX,1)

0x40c3a8 NOPW	%CS:(%RAX,%RAX,1)

0x40c3b7 NOPW	(%RAX,%RAX,1)

0x40c3c0 MOV	$0x419947,%EDI

0x40c3c5 MOV	$0x41981e,%ESI

0x40c3ca MOV	$0x419966,%ECX

0x40c3cf MOV	$0x106,%EDX

0x40c3d4 CALL	4030c0 <__assert_fail@plt>

0x40c3d9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►60.26+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►37.75+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►1.99+	redistributeAtoms	timestep.c:148	exec
○	main	CoMD.c:207	exec
○	__libc_start_call_main		libc.so.6

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	linkCells.c:209-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:209-221,227-247,258-269,288-304,327-334,352-353,359-365,371,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 1.00 cycles (16.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.33 to 1.10 cycles (14.89x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262
__intel_avx_rep_memset: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:385

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	94
nb uops	98
loop length	637
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67
cycles	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.33
Dispatch	8.00
Overall L1	16.33

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

1% of peak load performance is reached (2.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.33 to 8.00 cycles (2.04x speedup).

ASM code

In the binary file, the address of the function is: 40bde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x14(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP %R15D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JGE 40be34 <updateLinkCells+0x54>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %R14D,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
SAL $0x2,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x78(%RAX),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4157a0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40c300 <updateLinkCells+0x520>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPCMPEQD %XMM0,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 40be8c <updateLinkCells+0xac>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4198f4,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41981e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4198fe,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x41992d,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41981e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4198fe,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x419947,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41981e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x419966,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x106,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_1

Source file and lines	linkCells.c:209-385
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262
__intel_avx_rep_memset: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:385

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	94
nb uops	98
loop length	637
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67
cycles	4.80	4.80	4.67	4.67	8.00	4.87	4.80	8.00	8.00	8.00	4.73	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.33
Dispatch	8.00
Overall L1	16.33

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	8%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

1% of peak load performance is reached (2.69 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40bde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc(%RDI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x14(%RDI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP %R15D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R15D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JGE 40be34 <updateLinkCells+0x54>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %R14D,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
SAL $0x2,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x78(%RAX),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4157a0 <__intel_avx_rep_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40c300 <updateLinkCells+0x520>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R14),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ECX,-0x2c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VPCMPEQD %XMM0,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 40be8c <updateLinkCells+0xac>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x4198f4,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41981e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4198fe,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x41992d,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41981e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x4198fe,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x419947,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x41981e,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x419966,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x106,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.44	0.02
▼Loop 81 - linkCells.c:209-371 - exec–	0.01	0.02
○Loop 82 - linkCells.c:209-371 - exec	0.43	0.87

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code