OV - exec - Function sortAtomsInCell

	Function: sortAtomsInCell	Module: exec	Source: haloExchange.c:614-645	Coverage (incl. loops): 0.43% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 614 - 645

--------------------------------------------------------------------------------

614: {

615:    int nAtoms = boxes->nAtoms[iBox];

616:

617:    AtomMsg tmp[nAtoms];

618:

619:    int begin = iBox*MAXATOMS;

620:    int end = begin + nAtoms;

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

630:       tmp[iTmp].pz =   atoms->p[ii][2];

631:    }

632:    qsort(&tmp, nAtoms, sizeof(AtomMsg), sortAtomsById);

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

643:    }

644:

645: }

0x4091b0 PUSH	%RBP

0x4091b1 MOV	%RSP,%RBP

0x4091b4 PUSH	%R15

0x4091b6 PUSH	%R14

0x4091b8 PUSH	%R13

0x4091ba PUSH	%R12

0x4091bc PUSH	%RBX

0x4091bd SUB	$0x18,%RSP

0x4091c1 MOV	0x78(%RSI),%RAX

0x4091c5 MOVSXD	%EDX,%RCX

0x4091c8 MOV	(%RAX,%RCX,4),%ESI

0x4091cb IMUL	$0x38,%RSI,%RAX

0x4091cf ADD	$0xf,%RAX

0x4091d3 AND	$-0x10,%RAX

0x4091d7 MOV	%RSP,%RBX

0x4091da SUB	%RAX,%RBX

0x4091dd MOV	%RBX,%RSP

0x4091e0 TEST	%ESI,%ESI

0x4091e2 JLE	409300

0x4091e8 SAL	$0x6,%EDX

0x4091eb LEA	(%RSI,%RDX,1),%EAX

0x4091ee MOV	0x8(%RDI),%R8

0x4091f2 MOV	0x10(%RDI),%R9

0x4091f6 MOV	0x18(%RDI),%R12

0x4091fa MOV	0x20(%RDI),%R13

0x4091fe MOVSXD	%EDX,%R14

0x409201 MOVSXD	%EAX,%R15

0x409204 LEA	(,%R14,8),%RAX

0x40920c LEA	(%RAX,%RAX,2),%RAX

0x409210 MOV	%RBX,%RCX

0x409213 MOV	%R14,%RDX

0x409216 NOPW	%CS:(%RAX,%RAX,1)

(58) 0x409220 MOV	(%R8,%RDX,4),%EDI

(58) 0x409224 MOV	%EDI,(%RCX)

(58) 0x409226 MOV	(%R9,%RDX,4),%EDI

(58) 0x40922a MOV	%EDI,0x4(%RCX)

(58) 0x40922d VMOVUPS	(%R12,%RAX,1),%XMM0

(58) 0x409233 VBROADCASTSD	0x10(%R12,%RAX,1),%YMM1

(58) 0x40923a VBLENDPS	$0x30,%YMM1,%YMM0,%YMM0

(58) 0x409240 VBROADCASTSD	(%R13,%RAX,1),%YMM1

(58) 0x409247 VBLENDPS	$-0x40,%YMM1,%YMM0,%YMM0

(58) 0x40924d VMOVUPS	%YMM0,0x8(%RCX)

(58) 0x409252 VMOVUPS	0x8(%R13,%RAX,1),%XMM0

(58) 0x409259 VMOVUPS	%XMM0,0x28(%RCX)

(58) 0x40925e INC	%RDX

(58) 0x409261 ADD	$0x18,%RAX

(58) 0x409265 ADD	$0x38,%RCX

(58) 0x409269 CMP	%R15,%RDX

(58) 0x40926c JL	409220

0x40926e MOV	$0x38,%EDX

0x409273 MOV	$0x409330,%ECX

0x409278 MOV	%RBX,%RDI

0x40927b MOV	%R8,-0x38(%RBP)

0x40927f MOV	%R9,-0x30(%RBP)

0x409283 VZEROUPPER

0x409286 CALL	4032a0 <qsort@plt>

0x40928b MOV	-0x30(%RBP),%RSI

0x40928f MOV	-0x38(%RBP),%RDX

0x409293 LEA	(%R14,%R14,2),%RAX

0x409297 LEA	0x10(,%RAX,8),%RAX

0x40929f NOP

(59) 0x4092a0 MOV	(%RBX),%ECX

(59) 0x4092a2 MOV	%ECX,(%RDX,%R14,4)

(59) 0x4092a6 MOV	0x4(%RBX),%ECX

(59) 0x4092a9 MOV	%ECX,(%RSI,%R14,4)

(59) 0x4092ad VMOVUPS	0x8(%RBX),%XMM0

(59) 0x4092b2 VMOVUPS	%XMM0,-0x10(%R12,%RAX,1)

(59) 0x4092b9 VMOVSD	0x18(%RBX),%XMM0

(59) 0x4092be VMOVSD	%XMM0,(%R12,%RAX,1)

(59) 0x4092c4 VMOVUPS	0x20(%RBX),%XMM0

(59) 0x4092c9 VMOVUPS	%XMM0,-0x10(%R13,%RAX,1)

(59) 0x4092d0 VMOVSD	0x30(%RBX),%XMM0

(59) 0x4092d5 VMOVSD	%XMM0,(%R13,%RAX,1)

(59) 0x4092dc INC	%R14

(59) 0x4092df ADD	$0x18,%RAX

(59) 0x4092e3 ADD	$0x38,%RBX

(59) 0x4092e7 CMP	%R15,%R14

(59) 0x4092ea JL	4092a0

0x4092ec JMP	409315

0x4092ee NOPW	%CS:(%RAX,%RAX,1)

0x4092fd NOPL	(%RAX)

0x409300 MOVSXD	%ESI,%RSI

0x409303 MOV	$0x38,%EDX

0x409308 MOV	$0x409330,%ECX

0x40930d MOV	%RBX,%RDI

0x409310 CALL	4032a0 <qsort@plt>

0x409315 LEA	-0x28(%RBP),%RSP

0x409319 POP	%RBX

0x40931a POP	%R12

0x40931c POP	%R13

0x40931e POP	%R14

0x409320 POP	%R15

0x409322 POP	%RBP

0x409323 RET

0x409324 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►14.92+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►13.38+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.61+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►12.51+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.84+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.74+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.65+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►11.36+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_1

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.67 to 0.79 cycles (13.56x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qsort@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	61
nb uops	64
loop length	230
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.67 cycles
front end	10.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.10	3.27	5.00	5.00	5.00	3.27	3.10	5.00	5.00	5.00	3.27	5.00
cycles	3.10	3.93	5.00	5.00	5.00	3.27	3.10	5.00	5.00	5.00	3.27	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.67
Dispatch	5.00
Overall L1	10.67

Vectorization ratios

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.67 cycles. At this rate:

2% of peak load performance is reached (5.63 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.67 to 5.00 cycles (2.13x speedup).

ASM code

In the binary file, the address of the function is: 4091b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x78(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%RAX,%RCX,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL $0x38,%RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD $0xf,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSP,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RBX,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 409300 <sortAtomsInCell+0x150>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x6,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RSI,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x8(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EDX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
LEA (,%R14,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x38,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x409330,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4032a0 <qsort@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R14,%R14,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 409315 <sortAtomsInCell+0x165>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x38,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x409330,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4032a0 <qsort@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_1

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

qsort@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	61
nb uops	64
loop length	230
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.67 cycles
front end	10.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.10	3.27	5.00	5.00	5.00	3.27	3.10	5.00	5.00	5.00	3.27	5.00
cycles	3.10	3.93	5.00	5.00	5.00	3.27	3.10	5.00	5.00	5.00	3.27	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.67
Dispatch	5.00
Overall L1	10.67

Vectorization ratios

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.67 cycles. At this rate:

2% of peak load performance is reached (5.63 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4091b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x18,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x78(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%RAX,%RCX,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL $0x38,%RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD $0xf,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RSP,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RBX,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JLE 409300 <sortAtomsInCell+0x150>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x6,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RSI,%RDX,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x8(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EDX,%R14	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %EAX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
LEA (,%R14,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RAX,%RAX,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x38,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x409330,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4032a0 <qsort@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x30(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R14,%R14,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 409315 <sortAtomsInCell+0x165>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV $0x38,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x409330,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4032a0 <qsort@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼sortAtomsInCell–	0.43	0.02
○Loop 58 - haloExchange.c:621-629 - exec	0.39	0.02
○Loop 59 - haloExchange.c:633-642 - exec	0.03	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code