OV - exec - Function __libm_log

	Function: __libm_log_l9	Module: exec	Source: :0-0	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x411110 ENDBR64

0x411114 VMOVQ	%XMM0,%RAX

0x411119 MOV	%RAX,%RCX

0x41111c SHR	$0x20,%RCX

0x411120 ADD	$-0x7ff00000,%ECX

0x411126 CMP	$-0x7fe00000,%ECX

0x41112c JB	411215

0x411132 VPAND	0x9be6(%RIP),%XMM0,%XMM1

0x41113a VPOR	0x9bee(%RIP),%XMM1,%XMM1

0x411142 VPSRLQ	$0x34,%XMM0,%XMM0

0x411147 VMOVD	%XMM0,%EAX

0x41114b ADD	$-0x3ff,%EAX

0x411150 VCVTSI2SD	%EAX,%XMM2,%XMM0

0x411154 VMOVQ	%XMM1,%XMM2

0x411158 VPSRLQ	$0x1d,%XMM2,%XMM2

0x41115d VRCPSS	%XMM2,%XMM2,%XMM2

0x411161 VPBROADCASTD	0x9c36(%RIP),%XMM3

0x41116a VPADDD	%XMM3,%XMM2,%XMM2

0x41116e VPSRLD	$0x10,%XMM2,%XMM2

0x411173 VPSLLQ	$0x2d,%XMM2,%XMM3

0x411178 VPOR	0x9bc0(%RIP),%XMM1,%XMM1

0x411180 VFMADD213SD	0x80bf(%RIP),%XMM3,%XMM1

0x411189 VMOVSD	0x9bcf(%RIP),%XMM3

0x411191 VFMADD213SD	0x9bce(%RIP),%XMM1,%XMM3

0x41119a VMOVSD	0x9bce(%RIP),%XMM4

0x4111a2 VFMADD213SD	0x9bcd(%RIP),%XMM1,%XMM4

0x4111ab VMOVSD	0x9bcd(%RIP),%XMM5

0x4111b3 VFMADD213SD	0x9bcc(%RIP),%XMM1,%XMM5

0x4111bc VPADDQ	%XMM2,%XMM2,%XMM2

0x4111c0 VMOVD	%XMM2,%EAX

0x4111c4 AND	$0x1fe,%EAX

0x4111c9 LEA	0x9be0(%RIP),%RCX

0x4111d0 VMOVSD	0x9bb8(%RIP),%XMM2

0x4111d8 VFMADD213SD	0x8(%RCX,%RAX,8),%XMM0,%XMM2

0x4111df VMOVSD	0x9bb1(%RIP),%XMM6

0x4111e7 VFMADD213SD	(%RCX,%RAX,8),%XMM0,%XMM6

0x4111ed VADDSD	%XMM1,%XMM6,%XMM0

0x4111f1 VSUBSD	%XMM6,%XMM0,%XMM6

0x4111f5 VSUBSD	%XMM6,%XMM1,%XMM6

0x4111f9 VADDSD	%XMM6,%XMM2,%XMM2

0x4111fd VMULSD	%XMM1,%XMM1,%XMM1

0x411201 VFMADD231SD	%XMM3,%XMM1,%XMM4

0x411206 VFMADD213SD	%XMM5,%XMM1,%XMM4

0x41120b VFMADD213SD	%XMM2,%XMM1,%XMM4

0x411210 VADDSD	%XMM4,%XMM0,%XMM0

0x411214 RET

0x411215 VXORPD	%XMM2,%XMM2,%XMM2

0x411219 VADDSD	%XMM2,%XMM0,%XMM1

0x41121d VUCOMISD	%XMM2,%XMM0

0x411221 JNE	411225

0x411223 JNP	411262

0x411225 SHR	$0x34,%RAX

0x411229 JNE	411262

0x41122b VMULSD	0x9b1d(%RIP),%XMM1,%XMM0

0x411233 VANDPD	0x9ae5(%RIP),%XMM0,%XMM1

0x41123b VORPD	0x9aed(%RIP),%XMM1,%XMM1

0x411243 VPSRLQ	$0x34,%XMM0,%XMM0

0x411248 VMOVD	%XMM0,%EAX

0x41124c ADD	$-0x3ff,%EAX

0x411251 VCVTSI2SD	%EAX,%XMM3,%XMM0

0x411255 VADDSD	0x9afb(%RIP),%XMM0,%XMM0

0x41125d JMP	411154

0x411262 VMOVAPD	%XMM1,%XMM0

0x411266 JMP	411270

0x41126b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►59.26+	setTemperature.extracted.30	initAtoms.c:160	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►22.22+	setTemperature.extracted.30	initAtoms.c:162	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
►18.52+	setTemperature.extracted.30	initAtoms.c:161	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_1

Source file and lines
Module	exec

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 6 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.67 to 1.95 cycles (7.02x speedup).

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
22% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
54% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.67 to 11.33 cycles (1.21x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SD: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 19 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 28 FP arithmetical operations:

16: addition or subtraction (9 inside FMA instructions)
11: multiply (9 inside FMA instructions)
1: fast reciprocal

The binary function is loading 188 bytes (23 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	66
loop length	352
used x86 registers	2
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.67	13.67	6.67	6.67	0.00	13.67	7.00	0.00	0.00	0.00	5.00	6.67
cycles	13.67	13.67	6.67	6.67	0.00	13.67	7.00	0.00	0.00	0.00	5.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	13.67
Overall L1	13.67

Vectorization ratios

INT

all	52%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	47%

all	13%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	80%

INT+FP

all	29%
load	26%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	22%
fma	0%
div/sqrt	0%
other	54%

Vector efficiency ratios

INT

all	16%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	14%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	6%
other	22%

INT+FP

all	15%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	15%
fma	12%
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

7% of peak load performance is reached (13.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411110

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $-0x7ff00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $-0x7fe00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 411215 <__libm_log_l9+0x105>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPAND 0x9be6(%RIP),%XMM0,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPOR 0x9bee(%RIP),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x34,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VMOVD %XMM0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD $-0x3ff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VCVTSI2SD %EAX,%XMM2,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	scal (6.3%)
VMOVQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPSRLQ $0x1d,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VRCPSS %XMM2,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	4	1	scal (6.3%)
VPBROADCASTD 0x9c36(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VPADDD %XMM3,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLD $0x10,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPSLLQ $0x2d,%XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPOR 0x9bc0(%RIP),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VFMADD213SD 0x80bf(%RIP),%XMM3,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bcf(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x9bce(%RIP),%XMM1,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bce(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x9bcd(%RIP),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bcd(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x9bcc(%RIP),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VPADDQ %XMM2,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVD %XMM2,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
AND $0x1fe,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x9be0(%RIP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x9bb8(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%RCX,%RAX,8),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bb1(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD (%RCX,%RAX,8),%XMM0,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM6,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM3,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM5,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM2,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 411225 <__libm_log_l9+0x115>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JNP 411262 <__libm_log_l9+0x152>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SHR $0x34,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 411262 <__libm_log_l9+0x152>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD 0x9b1d(%RIP),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VANDPD 0x9ae5(%RIP),%XMM0,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VORPD 0x9aed(%RIP),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x34,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VMOVD %XMM0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD $-0x3ff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VCVTSI2SD %EAX,%XMM3,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	scal (6.3%)
VADDSD 0x9afb(%RIP),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
JMP 411154 <__libm_log_l9+0x44>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 411270 <__libm_log_e7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_1

Source file and lines
Module	exec

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=6

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

26% of SSE/AVX loads are used in vector version.
22% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
54% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SD: 2 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 2 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 28 FP arithmetical operations:

16: addition or subtraction (9 inside FMA instructions)
11: multiply (9 inside FMA instructions)
1: fast reciprocal

The binary function is loading 188 bytes (23 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	66
loop length	352
used x86 registers	2
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.33 cycles
front end	11.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.67	13.67	6.67	6.67	0.00	13.67	7.00	0.00	0.00	0.00	5.00	6.67
cycles	13.67	13.67	6.67	6.67	0.00	13.67	7.00	0.00	0.00	0.00	5.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.33
Dispatch	13.67
Overall L1	13.67

Vectorization ratios

INT

all	52%
load	75%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	47%

all	13%
load	13%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	80%

INT+FP

all	29%
load	26%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	22%
fma	0%
div/sqrt	0%
other	54%

Vector efficiency ratios

INT

all	16%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	14%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	6%
other	22%

INT+FP

all	15%
load	15%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	15%
fma	12%
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

7% of peak load performance is reached (13.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411110

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVQ %XMM0,%RAX	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD $-0x7ff00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $-0x7fe00000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 411215 <__libm_log_l9+0x105>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPAND 0x9be6(%RIP),%XMM0,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPOR 0x9bee(%RIP),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x34,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VMOVD %XMM0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD $-0x3ff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VCVTSI2SD %EAX,%XMM2,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	scal (6.3%)
VMOVQ %XMM1,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
VPSRLQ $0x1d,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VRCPSS %XMM2,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	4	1	scal (6.3%)
VPBROADCASTD 0x9c36(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VPADDD %XMM3,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLD $0x10,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPSLLQ $0x2d,%XMM2,%XMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPOR 0x9bc0(%RIP),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VFMADD213SD 0x80bf(%RIP),%XMM3,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bcf(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x9bce(%RIP),%XMM1,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bce(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x9bcd(%RIP),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bcd(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x9bcc(%RIP),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VPADDQ %XMM2,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVD %XMM2,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
AND $0x1fe,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x9be0(%RIP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x9bb8(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%RCX,%RAX,8),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x9bb1(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD (%RCX,%RAX,8),%XMM0,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM6,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM0,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VSUBSD %XMM6,%XMM1,%XMM6	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM6,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM3,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM5,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD %XMM2,%XMM1,%XMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 411225 <__libm_log_l9+0x115>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JNP 411262 <__libm_log_l9+0x152>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SHR $0x34,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
JNE 411262 <__libm_log_l9+0x152>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD 0x9b1d(%RIP),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VANDPD 0x9ae5(%RIP),%XMM0,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VORPD 0x9aed(%RIP),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x34,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VMOVD %XMM0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD $-0x3ff,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VCVTSI2SD %EAX,%XMM3,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	7	1	scal (6.3%)
VADDSD 0x9afb(%RIP),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
JMP 411154 <__libm_log_l9+0x44>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 411270 <__libm_log_e7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
○__libm_log_l9	0.02	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code