OV - exec - Loop 93

	Loop Id: 93	Module: exec	Source: ljForce.c:187-216 [...]	Coverage: 11.61%

0x40d790 MOV	0x18(%R11),%RSI

0x40d794 LEA	(%R8,%R8,2),%RBX

0x40d798 LEA	(%RSI,%RBX,1),%RDX

0x40d79c VMOVSD	0x8(%RDX),%XMM1

0x40d7a1 ADD	%R15,%RSI

0x40d7a4 VSUBSD	0x8(%RSI),%XMM1,%XMM1

0x40d7a9 VMOVSD	(%RDX),%XMM2

0x40d7ad VMOVSD	0x10(%RDX),%XMM13

0x40d7b2 VMULSD	%XMM1,%XMM1,%XMM0

0x40d7b6 VSUBSD	(%RSI),%XMM2,%XMM2

0x40d7ba VSUBSD	0x10(%RSI),%XMM13,%XMM13

0x40d7bf MOV	%R13D,%EDI

0x40d7c2 NOT	%EDI

0x40d7c4 VFMADD231SD	%XMM2,%XMM2,%XMM0

0x40d7c9 ADD	%R9D,%EDI

0x40d7cc AND	$0x1,%EDI

0x40d7cf VFMADD231SD	%XMM13,%XMM13,%XMM0

0x40d7d4 VCOMISD	%XMM3,%XMM0

0x40d7d8 JBE	40d854

0x40d7da VCOMISD	%XMM0,%XMM4

0x40d7de JB	40d854

0x40d7e0 VDIVSD	%XMM0,%XMM7,%XMM0

0x40d7e4 MOV	0x30(%R11),%RAX

0x40d7e8 MOV	0x28(%R11),%RCX

0x40d7ec ADD	%R8,%RAX

0x40d7ef ADD	%RBX,%RCX

0x40d7f2 VMULSD	%XMM0,%XMM8,%XMM15

0x40d7f6 VMULSD	%XMM0,%XMM0,%XMM14

0x40d7fa VMULSD	%XMM0,%XMM10,%XMM0

0x40d7fe VMULSD	%XMM0,%XMM14,%XMM14

0x40d802 VSUBSD	%XMM7,%XMM14,%XMM0

0x40d806 VFMSUB132SD	%XMM14,%XMM9,%XMM0

0x40d80b VMOVAPD	%XMM0,%XMM16

0x40d811 VFMADD231SD	%XMM6,%XMM0,%XMM5

0x40d816 VMOVAPD	%XMM14,%XMM0

0x40d81a VFMADD132SD	%XMM12,%XMM11,%XMM0

0x40d81f VFMADD213SD	(%RAX),%XMM6,%XMM16

0x40d825 VMULSD	%XMM14,%XMM0,%XMM14

0x40d82a VMOVSD	%XMM16,(%RAX)

0x40d830 VMULSD	%XMM15,%XMM14,%XMM15

0x40d835 VFNMADD213SD	(%RCX),%XMM15,%XMM2

0x40d83a VFNMADD213SD	0x8(%RCX),%XMM15,%XMM1

0x40d840 VFNMADD213SD	0x10(%RCX),%XMM13,%XMM15

0x40d846 VMOVSD	%XMM2,(%RCX)

0x40d84a VMOVSD	%XMM1,0x8(%RCX)

0x40d84f VMOVSD	%XMM15,0x10(%RCX)

0x40d854 LEA	0x1(%R13),%ECX

0x40d858 LEA	0x18(%RSI),%RAX

0x40d85c CMP	%ECX,%R9D

0x40d85f JLE	40da9a

0x40d865 TEST	%EDI,%EDI

0x40d867 JE	40d930

0x40d86d VMOVSD	0x8(%RDX),%XMM1

0x40d872 VMOVSD	(%RDX),%XMM2

0x40d876 VSUBSD	0x8(%RAX),%XMM1,%XMM1

0x40d87b VSUBSD	0x18(%RSI),%XMM2,%XMM2

0x40d880 VMOVSD	0x10(%RDX),%XMM13

0x40d885 VMULSD	%XMM1,%XMM1,%XMM0

0x40d889 VSUBSD	0x10(%RAX),%XMM13,%XMM13

0x40d88e VFMADD231SD	%XMM2,%XMM2,%XMM0

0x40d893 VFMADD231SD	%XMM13,%XMM13,%XMM0

0x40d898 VCOMISD	%XMM3,%XMM0

0x40d89c JBE	40d918

0x40d89e VCOMISD	%XMM0,%XMM4

0x40d8a2 JB	40d918

0x40d8a4 VDIVSD	%XMM0,%XMM7,%XMM0

0x40d8a8 MOV	0x30(%R11),%RSI

0x40d8ac MOV	0x28(%R11),%RDI

0x40d8b0 ADD	%R8,%RSI

0x40d8b3 ADD	%RBX,%RDI

0x40d8b6 VMULSD	%XMM0,%XMM8,%XMM15

0x40d8ba VMULSD	%XMM0,%XMM0,%XMM14

0x40d8be VMULSD	%XMM0,%XMM10,%XMM0

0x40d8c2 VMULSD	%XMM0,%XMM14,%XMM14

0x40d8c6 VSUBSD	%XMM7,%XMM14,%XMM0

0x40d8ca VFMSUB132SD	%XMM14,%XMM9,%XMM0

0x40d8cf VMOVAPD	%XMM0,%XMM17

0x40d8d5 VFMADD231SD	%XMM6,%XMM0,%XMM5

0x40d8da VMOVAPD	%XMM14,%XMM0

0x40d8de VFMADD132SD	%XMM12,%XMM11,%XMM0

0x40d8e3 VFMADD213SD	(%RSI),%XMM6,%XMM17

0x40d8e9 VMULSD	%XMM14,%XMM0,%XMM14

0x40d8ee VMOVSD	%XMM17,(%RSI)

0x40d8f4 VMULSD	%XMM15,%XMM14,%XMM15

0x40d8f9 VFNMADD213SD	(%RDI),%XMM15,%XMM2

0x40d8fe VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

0x40d904 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

0x40d90a VMOVSD	%XMM2,(%RDI)

0x40d90e VMOVSD	%XMM1,0x8(%RDI)

0x40d913 VMOVSD	%XMM15,0x10(%RDI)

0x40d918 INC	%ECX

0x40d91a ADD	$0x18,%RAX

0x40d91e CMP	%ECX,%R9D

0x40d921 JLE	40da9a

0x40d927 NOPW	(%RAX,%RAX,1)

  (94) 0x40d930 VMOVSD	0x8(%RDX),%XMM1

  (94) 0x40d935 VMOVSD	(%RDX),%XMM2

  (94) 0x40d939 VSUBSD	0x8(%RAX),%XMM1,%XMM1

  (94) 0x40d93e VSUBSD	(%RAX),%XMM2,%XMM2

  (94) 0x40d942 VMOVSD	0x10(%RDX),%XMM13

  (94) 0x40d947 VMULSD	%XMM1,%XMM1,%XMM0

  (94) 0x40d94b VSUBSD	0x10(%RAX),%XMM13,%XMM13

  (94) 0x40d950 VFMADD231SD	%XMM2,%XMM2,%XMM0

  (94) 0x40d955 VFMADD231SD	%XMM13,%XMM13,%XMM0

  (94) 0x40d95a VCOMISD	%XMM3,%XMM0

  (94) 0x40d95e JBE	40d9da

  (94) 0x40d960 VCOMISD	%XMM0,%XMM4

  (94) 0x40d964 JB	40d9da

  (94) 0x40d966 VDIVSD	%XMM0,%XMM7,%XMM0

  (94) 0x40d96a MOV	0x30(%R11),%RSI

  (94) 0x40d96e MOV	0x28(%R11),%RDI

  (94) 0x40d972 ADD	%R8,%RSI

  (94) 0x40d975 ADD	%RBX,%RDI

  (94) 0x40d978 VMULSD	%XMM0,%XMM8,%XMM15

  (94) 0x40d97c VMULSD	%XMM0,%XMM0,%XMM14

  (94) 0x40d980 VMULSD	%XMM0,%XMM10,%XMM0

  (94) 0x40d984 VMULSD	%XMM0,%XMM14,%XMM14

  (94) 0x40d988 VSUBSD	%XMM7,%XMM14,%XMM0

  (94) 0x40d98c VFMSUB132SD	%XMM14,%XMM9,%XMM0

  (94) 0x40d991 VMOVAPD	%XMM0,%XMM18

  (94) 0x40d997 VFMADD231SD	%XMM6,%XMM0,%XMM5

  (94) 0x40d99c VMOVAPD	%XMM14,%XMM0

  (94) 0x40d9a0 VFMADD132SD	%XMM12,%XMM11,%XMM0

  (94) 0x40d9a5 VFMADD213SD	(%RSI),%XMM6,%XMM18

  (94) 0x40d9ab VMULSD	%XMM14,%XMM0,%XMM14

  (94) 0x40d9b0 VMOVSD	%XMM18,(%RSI)

  (94) 0x40d9b6 VMULSD	%XMM15,%XMM14,%XMM15

  (94) 0x40d9bb VFNMADD213SD	(%RDI),%XMM15,%XMM2

  (94) 0x40d9c0 VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

  (94) 0x40d9c6 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

  (94) 0x40d9cc VMOVSD	%XMM2,(%RDI)

  (94) 0x40d9d0 VMOVSD	%XMM1,0x8(%RDI)

  (94) 0x40d9d5 VMOVSD	%XMM15,0x10(%RDI)

  (94) 0x40d9da VMOVSD	0x8(%RDX),%XMM1

  (94) 0x40d9df VMOVSD	(%RDX),%XMM2

  (94) 0x40d9e3 VSUBSD	0x20(%RAX),%XMM1,%XMM1

  (94) 0x40d9e8 VSUBSD	0x18(%RAX),%XMM2,%XMM2

  (94) 0x40d9ed VMOVSD	0x10(%RDX),%XMM13

  (94) 0x40d9f2 VMULSD	%XMM1,%XMM1,%XMM0

  (94) 0x40d9f6 VSUBSD	0x28(%RAX),%XMM13,%XMM13

  (94) 0x40d9fb INC	%ECX

  (94) 0x40d9fd LEA	0x18(%RAX),%RSI

  (94) 0x40da01 VFMADD231SD	%XMM2,%XMM2,%XMM0

  (94) 0x40da06 VFMADD231SD	%XMM13,%XMM13,%XMM0

  (94) 0x40da0b VCOMISD	%XMM3,%XMM0

  (94) 0x40da0f JBE	40da8b

  (94) 0x40da11 VCOMISD	%XMM0,%XMM4

  (94) 0x40da15 JB	40da8b

  (94) 0x40da17 VDIVSD	%XMM0,%XMM7,%XMM0

  (94) 0x40da1b MOV	0x30(%R11),%RAX

  (94) 0x40da1f MOV	0x28(%R11),%RDI

  (94) 0x40da23 ADD	%R8,%RAX

  (94) 0x40da26 ADD	%RBX,%RDI

  (94) 0x40da29 VMULSD	%XMM0,%XMM8,%XMM15

  (94) 0x40da2d VMULSD	%XMM0,%XMM0,%XMM14

  (94) 0x40da31 VMULSD	%XMM0,%XMM10,%XMM0

  (94) 0x40da35 VMULSD	%XMM0,%XMM14,%XMM14

  (94) 0x40da39 VSUBSD	%XMM7,%XMM14,%XMM0

  (94) 0x40da3d VFMSUB132SD	%XMM14,%XMM9,%XMM0

  (94) 0x40da42 VMOVAPD	%XMM0,%XMM19

  (94) 0x40da48 VFMADD231SD	%XMM6,%XMM0,%XMM5

  (94) 0x40da4d VMOVAPD	%XMM14,%XMM0

  (94) 0x40da51 VFMADD132SD	%XMM12,%XMM11,%XMM0

  (94) 0x40da56 VFMADD213SD	(%RAX),%XMM6,%XMM19

  (94) 0x40da5c VMULSD	%XMM14,%XMM0,%XMM14

  (94) 0x40da61 VMOVSD	%XMM19,(%RAX)

  (94) 0x40da67 VMULSD	%XMM15,%XMM14,%XMM15

  (94) 0x40da6c VFNMADD213SD	(%RDI),%XMM15,%XMM2

  (94) 0x40da71 VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

  (94) 0x40da77 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

  (94) 0x40da7d VMOVSD	%XMM2,(%RDI)

  (94) 0x40da81 VMOVSD	%XMM1,0x8(%RDI)

  (94) 0x40da86 VMOVSD	%XMM15,0x10(%RDI)

  (94) 0x40da8b INC	%ECX

  (94) 0x40da8d LEA	0x18(%RSI),%RAX

  (94) 0x40da91 CMP	%ECX,%R9D

  (94) 0x40da94 JG	40d930

0x40da9a INC	%R12D

0x40da9d ADD	$0x8,%R8

0x40daa1 CMP	%R12D,%R14D

0x40daa4 JG	40d790

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 187 - 216

--------------------------------------------------------------------------------

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
○98.04	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.96	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.91
CQA speedup if fully vectorized	5.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P1,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	6.88
CQA cycles if fully vectorized	4.00
Front-end cycles	16.33
P0 cycles	19.50
P1 cycles	20.00
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	4.00
P5 cycles	9.80
P6 cycles	9.60
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	9.60
P11 cycles	8.33
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	98.00
Nb loads	25.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	18.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.20
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.97
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	36.36
Vector-efficiency ratio all	12.97
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.34

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.91
CQA speedup if fully vectorized	5.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P1,
Function	ljForce._omp_fn.1
Source	ljForce.c:187-187,ljForce.c:191-191,ljForce.c:197-198,ljForce.c:201-201,ljForce.c:206-210,ljForce.c:213-213,ljForce.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	6.88
CQA cycles if fully vectorized	4.00
Front-end cycles	16.33
P0 cycles	19.50
P1 cycles	20.00
P2 cycles	8.33
P3 cycles	8.33
P4 cycles	4.00
P5 cycles	9.80
P6 cycles	9.60
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	9.60
P11 cycles	8.33
DIV/SQRT cycles	8.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	99.00
Nb uops	98.00
Nb loads	25.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	8.00
Nb FLOP mul	14.00
Nb FLOP fma	18.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.20
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.97
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	36.36
Vector-efficiency ratio all	12.97
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.34

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187,191,197-198,201,206-210,213,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 120 paths individually, rerun with max-paths=120
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 120 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 20.00 to 4.00 cycles (5.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

46 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (18 inside FMA instructions)
32: multiply (18 inside FMA instructions)
2: divide

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	98
loop length	432
used x86 registers	13
used mmx registers	0
used xmm registers	18
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.57

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	19.50	19.50	8.33	8.33	4.00	9.80	9.60	4.00	4.00	4.00	9.60	8.33
cycles	19.50	20.00	8.33	8.33	4.00	9.80	9.60	4.00	4.00	4.00	9.60	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

8.00

Cycles summary

Front-end	16.33
Dispatch	20.00
DIV/SQRT	8.00
Overall L1	20.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

5% of peak load performance is reached (10.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40d790

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x18(%R11),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R8,2),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RBX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSUBSD 0x8(%RSI),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD (%RSI),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD 0x10(%RSI),%XMM13,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV %R13D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R9D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VFMADD231SD %XMM13,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM3,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 40d854 <ljForce._omp_fn.1+0x314>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM0,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JB 40d854 <ljForce._omp_fn.1+0x314>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VDIVSD %XMM0,%XMM7,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV 0x30(%R11),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R11),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM0,%XMM8,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM14,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMSUB132SD %XMM14,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD231SD %XMM6,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD132SD %XMM12,%XMM11,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD (%RAX),%XMM6,%XMM16	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM16,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD (%RCX),%XMM15,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%RCX),%XMM15,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x10(%RCX),%XMM13,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R13),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x18(%RSI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %ECX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40da9a <ljForce._omp_fn.1+0x55a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40d930 <ljForce._omp_fn.1+0x3f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x8(%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x8(%RAX),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD 0x18(%RSI),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x10(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD 0x10(%RAX),%XMM13,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM3,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 40d918 <ljForce._omp_fn.1+0x3d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM0,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JB 40d918 <ljForce._omp_fn.1+0x3d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VDIVSD %XMM0,%XMM7,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV 0x30(%R11),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R11),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM0,%XMM8,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM14,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMSUB132SD %XMM14,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD231SD %XMM6,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD132SD %XMM12,%XMM11,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD (%RSI),%XMM6,%XMM17	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM17,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD (%RDI),%XMM15,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%RDI),%XMM15,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x10(%RDI),%XMM13,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40da9a <ljForce._omp_fn.1+0x55a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JG 40d790 <ljForce._omp_fn.1+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:187-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 120 paths individually, rerun with max-paths=120
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 18 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

46 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (18 inside FMA instructions)
32: multiply (18 inside FMA instructions)
2: divide

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	98
loop length	432
used x86 registers	13
used mmx registers	0
used xmm registers	18
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.57

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	19.50	19.50	8.33	8.33	4.00	9.80	9.60	4.00	4.00	4.00	9.60	8.33
cycles	19.50	20.00	8.33	8.33	4.00	9.80	9.60	4.00	4.00	4.00	9.60	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

8.00

Cycles summary

Front-end	16.33
Dispatch	20.00
DIV/SQRT	8.00
Overall L1	20.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	13%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

5% of peak load performance is reached (10.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40d790

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x18(%R11),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R8,2),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RBX,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VSUBSD 0x8(%RSI),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD (%RSI),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD 0x10(%RSI),%XMM13,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
MOV %R13D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R9D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VFMADD231SD %XMM13,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM3,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 40d854 <ljForce._omp_fn.1+0x314>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM0,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JB 40d854 <ljForce._omp_fn.1+0x314>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VDIVSD %XMM0,%XMM7,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV 0x30(%R11),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R11),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM0,%XMM8,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM14,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMSUB132SD %XMM14,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD231SD %XMM6,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD132SD %XMM12,%XMM11,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD (%RAX),%XMM6,%XMM16	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM16,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD (%RCX),%XMM15,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%RCX),%XMM15,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x10(%RCX),%XMM13,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R13),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x18(%RSI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %ECX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40da9a <ljForce._omp_fn.1+0x55a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40d930 <ljForce._omp_fn.1+0x3f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x8(%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VSUBSD 0x8(%RAX),%XMM1,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VSUBSD 0x18(%RSI),%XMM2,%XMM2	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD 0x10(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULSD %XMM1,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD 0x10(%RAX),%XMM13,%XMM13	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VFMADD231SD %XMM2,%XMM2,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCOMISD %XMM3,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JBE 40d918 <ljForce._omp_fn.1+0x3d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM0,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JB 40d918 <ljForce._omp_fn.1+0x3d8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VDIVSD %XMM0,%XMM7,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
MOV 0x30(%R11),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R11),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMULSD %XMM0,%XMM8,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM10,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM0,%XMM14,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBSD %XMM7,%XMM14,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VFMSUB132SD %XMM14,%XMM9,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM0,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD231SD %XMM6,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VFMADD132SD %XMM12,%XMM11,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD213SD (%RSI),%XMM6,%XMM17	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMULSD %XMM14,%XMM0,%XMM14	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM17,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD %XMM15,%XMM14,%XMM15	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFNMADD213SD (%RDI),%XMM15,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x8(%RDI),%XMM15,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFNMADD213SD 0x10(%RDI),%XMM13,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ECX,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40da9a <ljForce._omp_fn.1+0x55a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JG 40d790 <ljForce._omp_fn.1+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code