OV - exec - Loop 91

	Loop Id: 91	Module: exec	Source: ljForce.c:178-216 [...]	Coverage: 0.36%

0x40d651 MOV	(%RAX),%R13D

0x40d654 TEST	%R13D,%R13D

0x40d657 JS	40dbc6

0x40d65d MOV	-0x50(%RBP),%RBX

0x40d661 MOV	-0x38(%RBP),%R15D

0x40d665 MOVSXD	%R13D,%RDI

0x40d668 MOV	(%RBX,%RDI,4),%ESI

0x40d66b TEST	%R15D,%R15D

0x40d66e JLE	40d73f

0x40d674 MOV	%EDX,%ECX

0x40d676 NOT	%ECX

0x40d678 SAL	$0x6,%R13D

0x40d67c LEA	(%RDI,%RDI,2),%R15

0x40d680 ADD	%R14D,%ECX

0x40d683 MOV	-0x48(%RBP),%R8

0x40d687 LEA	(%RSI,%R13,1),%R9D

0x40d68b SAL	$0x9,%R15

0x40d68f MOV	%EDX,%R12D

0x40d692 AND	$0x7,%ECX

0x40d695 TEST	%ESI,%ESI

0x40d697 JG	40d77a

0x40d69d LEA	0x1(%RDX),%R12D

0x40d6a1 LEA	0x8(%R8),%R8

0x40d6a5 CMP	%R14D,%R12D

0x40d6a8 JGE	40d73f

0x40d6ae TEST	%ECX,%ECX

0x40d6b0 JE	40d72e

0x40d6b2 CMP	$0x1,%ECX

0x40d6b5 JE	40d71e

0x40d6b7 CMP	$0x2,%ECX

0x40d6ba JE	40d713

0x40d6bc CMP	$0x3,%ECX

0x40d6bf JE	40d708

0x40d6c1 CMP	$0x4,%ECX

0x40d6c4 JE	40d6fd

0x40d6c6 CMP	$0x5,%ECX

0x40d6c9 JE	40d6ee

0x40d6cb CMP	$0x6,%ECX

0x40d6ce JE	40d6df

0x40d6d0 TEST	%ESI,%ESI

0x40d6d2 JG	40d77a

0x40d6d8 INC	%R12D

0x40d6db ADD	$0x8,%R8

0x40d6df TEST	%ESI,%ESI

0x40d6e1 JG	40d77a

0x40d6e7 INC	%R12D

0x40d6ea ADD	$0x8,%R8

0x40d6ee TEST	%ESI,%ESI

0x40d6f0 JG	40d77a

0x40d6f6 INC	%R12D

0x40d6f9 ADD	$0x8,%R8

0x40d6fd TEST	%ESI,%ESI

0x40d6ff JG	40d77a

0x40d701 INC	%R12D

0x40d704 ADD	$0x8,%R8

0x40d708 TEST	%ESI,%ESI

0x40d70a JG	40d77a

0x40d70c INC	%R12D

0x40d70f ADD	$0x8,%R8

0x40d713 TEST	%ESI,%ESI

0x40d715 JG	40d77a

0x40d717 INC	%R12D

0x40d71a ADD	$0x8,%R8

0x40d71e TEST	%ESI,%ESI

0x40d720 JG	40d77a

0x40d722 INC	%R12D

0x40d725 ADD	$0x8,%R8

0x40d729 CMP	%R14D,%R12D

0x40d72c JGE	40d73f

  (95) 0x40d72e TEST	%ESI,%ESI

  (95) 0x40d730 JG	40d77a

  (95) 0x40d732 ADD	$0x8,%R12D

  (95) 0x40d736 ADD	$0x40,%R8

  (95) 0x40d73a CMP	%R14D,%R12D

  (95) 0x40d73d JL	40d72e

0x40d73f ADD	$0x4,%RAX

0x40d743 CMP	%RAX,-0x60(%RBP)

0x40d747 JNE	40d651

0x40d77a MOV	-0x58(%RBP),%R11

0x40d77e MOV	%EDX,-0x34(%RBP)

0x40d781 MOV	%RAX,-0x40(%RBP)

0x40d785 MOV	0x20(%R11),%R11

0x40d789 VXORPD	%XMM3,%XMM3,%XMM3

0x40d78d NOPL	(%RAX)

  (93) 0x40d790 MOV	0x18(%R11),%RSI

  (93) 0x40d794 LEA	(%R8,%R8,2),%RBX

  (93) 0x40d798 LEA	(%RSI,%RBX,1),%RDX

  (93) 0x40d79c VMOVSD	0x8(%RDX),%XMM1

  (93) 0x40d7a1 ADD	%R15,%RSI

  (93) 0x40d7a4 VSUBSD	0x8(%RSI),%XMM1,%XMM1

  (93) 0x40d7a9 VMOVSD	(%RDX),%XMM2

  (93) 0x40d7ad VMOVSD	0x10(%RDX),%XMM13

  (93) 0x40d7b2 VMULSD	%XMM1,%XMM1,%XMM0

  (93) 0x40d7b6 VSUBSD	(%RSI),%XMM2,%XMM2

  (93) 0x40d7ba VSUBSD	0x10(%RSI),%XMM13,%XMM13

  (93) 0x40d7bf MOV	%R13D,%EDI

  (93) 0x40d7c2 NOT	%EDI

  (93) 0x40d7c4 VFMADD231SD	%XMM2,%XMM2,%XMM0

  (93) 0x40d7c9 ADD	%R9D,%EDI

  (93) 0x40d7cc AND	$0x1,%EDI

  (93) 0x40d7cf VFMADD231SD	%XMM13,%XMM13,%XMM0

  (93) 0x40d7d4 VCOMISD	%XMM3,%XMM0

  (93) 0x40d7d8 JBE	40d854

  (93) 0x40d7da VCOMISD	%XMM0,%XMM4

  (93) 0x40d7de JB	40d854

  (93) 0x40d7e0 VDIVSD	%XMM0,%XMM7,%XMM0

  (93) 0x40d7e4 MOV	0x30(%R11),%RAX

  (93) 0x40d7e8 MOV	0x28(%R11),%RCX

  (93) 0x40d7ec ADD	%R8,%RAX

  (93) 0x40d7ef ADD	%RBX,%RCX

  (93) 0x40d7f2 VMULSD	%XMM0,%XMM8,%XMM15

  (93) 0x40d7f6 VMULSD	%XMM0,%XMM0,%XMM14

  (93) 0x40d7fa VMULSD	%XMM0,%XMM10,%XMM0

  (93) 0x40d7fe VMULSD	%XMM0,%XMM14,%XMM14

  (93) 0x40d802 VSUBSD	%XMM7,%XMM14,%XMM0

  (93) 0x40d806 VFMSUB132SD	%XMM14,%XMM9,%XMM0

  (93) 0x40d80b VMOVAPD	%XMM0,%XMM16

  (93) 0x40d811 VFMADD231SD	%XMM6,%XMM0,%XMM5

  (93) 0x40d816 VMOVAPD	%XMM14,%XMM0

  (93) 0x40d81a VFMADD132SD	%XMM12,%XMM11,%XMM0

  (93) 0x40d81f VFMADD213SD	(%RAX),%XMM6,%XMM16

  (93) 0x40d825 VMULSD	%XMM14,%XMM0,%XMM14

  (93) 0x40d82a VMOVSD	%XMM16,(%RAX)

  (93) 0x40d830 VMULSD	%XMM15,%XMM14,%XMM15

  (93) 0x40d835 VFNMADD213SD	(%RCX),%XMM15,%XMM2

  (93) 0x40d83a VFNMADD213SD	0x8(%RCX),%XMM15,%XMM1

  (93) 0x40d840 VFNMADD213SD	0x10(%RCX),%XMM13,%XMM15

  (93) 0x40d846 VMOVSD	%XMM2,(%RCX)

  (93) 0x40d84a VMOVSD	%XMM1,0x8(%RCX)

  (93) 0x40d84f VMOVSD	%XMM15,0x10(%RCX)

  (93) 0x40d854 LEA	0x1(%R13),%ECX

  (93) 0x40d858 LEA	0x18(%RSI),%RAX

  (93) 0x40d85c CMP	%ECX,%R9D

  (93) 0x40d85f JLE	40da9a

  (93) 0x40d865 TEST	%EDI,%EDI

  (93) 0x40d867 JE	40d930

  (93) 0x40d86d VMOVSD	0x8(%RDX),%XMM1

  (93) 0x40d872 VMOVSD	(%RDX),%XMM2

  (93) 0x40d876 VSUBSD	0x8(%RAX),%XMM1,%XMM1

  (93) 0x40d87b VSUBSD	0x18(%RSI),%XMM2,%XMM2

  (93) 0x40d880 VMOVSD	0x10(%RDX),%XMM13

  (93) 0x40d885 VMULSD	%XMM1,%XMM1,%XMM0

  (93) 0x40d889 VSUBSD	0x10(%RAX),%XMM13,%XMM13

  (93) 0x40d88e VFMADD231SD	%XMM2,%XMM2,%XMM0

  (93) 0x40d893 VFMADD231SD	%XMM13,%XMM13,%XMM0

  (93) 0x40d898 VCOMISD	%XMM3,%XMM0

  (93) 0x40d89c JBE	40d918

  (93) 0x40d89e VCOMISD	%XMM0,%XMM4

  (93) 0x40d8a2 JB	40d918

  (93) 0x40d8a4 VDIVSD	%XMM0,%XMM7,%XMM0

  (93) 0x40d8a8 MOV	0x30(%R11),%RSI

  (93) 0x40d8ac MOV	0x28(%R11),%RDI

  (93) 0x40d8b0 ADD	%R8,%RSI

  (93) 0x40d8b3 ADD	%RBX,%RDI

  (93) 0x40d8b6 VMULSD	%XMM0,%XMM8,%XMM15

  (93) 0x40d8ba VMULSD	%XMM0,%XMM0,%XMM14

  (93) 0x40d8be VMULSD	%XMM0,%XMM10,%XMM0

  (93) 0x40d8c2 VMULSD	%XMM0,%XMM14,%XMM14

  (93) 0x40d8c6 VSUBSD	%XMM7,%XMM14,%XMM0

  (93) 0x40d8ca VFMSUB132SD	%XMM14,%XMM9,%XMM0

  (93) 0x40d8cf VMOVAPD	%XMM0,%XMM17

  (93) 0x40d8d5 VFMADD231SD	%XMM6,%XMM0,%XMM5

  (93) 0x40d8da VMOVAPD	%XMM14,%XMM0

  (93) 0x40d8de VFMADD132SD	%XMM12,%XMM11,%XMM0

  (93) 0x40d8e3 VFMADD213SD	(%RSI),%XMM6,%XMM17

  (93) 0x40d8e9 VMULSD	%XMM14,%XMM0,%XMM14

  (93) 0x40d8ee VMOVSD	%XMM17,(%RSI)

  (93) 0x40d8f4 VMULSD	%XMM15,%XMM14,%XMM15

  (93) 0x40d8f9 VFNMADD213SD	(%RDI),%XMM15,%XMM2

  (93) 0x40d8fe VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

  (93) 0x40d904 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

  (93) 0x40d90a VMOVSD	%XMM2,(%RDI)

  (93) 0x40d90e VMOVSD	%XMM1,0x8(%RDI)

  (93) 0x40d913 VMOVSD	%XMM15,0x10(%RDI)

  (93) 0x40d918 INC	%ECX

  (93) 0x40d91a ADD	$0x18,%RAX

  (93) 0x40d91e CMP	%ECX,%R9D

  (93) 0x40d921 JLE	40da9a

  (93) 0x40d927 NOPW	(%RAX,%RAX,1)

    (94) 0x40d930 VMOVSD	0x8(%RDX),%XMM1

    (94) 0x40d935 VMOVSD	(%RDX),%XMM2

    (94) 0x40d939 VSUBSD	0x8(%RAX),%XMM1,%XMM1

    (94) 0x40d93e VSUBSD	(%RAX),%XMM2,%XMM2

    (94) 0x40d942 VMOVSD	0x10(%RDX),%XMM13

    (94) 0x40d947 VMULSD	%XMM1,%XMM1,%XMM0

    (94) 0x40d94b VSUBSD	0x10(%RAX),%XMM13,%XMM13

    (94) 0x40d950 VFMADD231SD	%XMM2,%XMM2,%XMM0

    (94) 0x40d955 VFMADD231SD	%XMM13,%XMM13,%XMM0

    (94) 0x40d95a VCOMISD	%XMM3,%XMM0

    (94) 0x40d95e JBE	40d9da

    (94) 0x40d960 VCOMISD	%XMM0,%XMM4

    (94) 0x40d964 JB	40d9da

    (94) 0x40d966 VDIVSD	%XMM0,%XMM7,%XMM0

    (94) 0x40d96a MOV	0x30(%R11),%RSI

    (94) 0x40d96e MOV	0x28(%R11),%RDI

    (94) 0x40d972 ADD	%R8,%RSI

    (94) 0x40d975 ADD	%RBX,%RDI

    (94) 0x40d978 VMULSD	%XMM0,%XMM8,%XMM15

    (94) 0x40d97c VMULSD	%XMM0,%XMM0,%XMM14

    (94) 0x40d980 VMULSD	%XMM0,%XMM10,%XMM0

    (94) 0x40d984 VMULSD	%XMM0,%XMM14,%XMM14

    (94) 0x40d988 VSUBSD	%XMM7,%XMM14,%XMM0

    (94) 0x40d98c VFMSUB132SD	%XMM14,%XMM9,%XMM0

    (94) 0x40d991 VMOVAPD	%XMM0,%XMM18

    (94) 0x40d997 VFMADD231SD	%XMM6,%XMM0,%XMM5

    (94) 0x40d99c VMOVAPD	%XMM14,%XMM0

    (94) 0x40d9a0 VFMADD132SD	%XMM12,%XMM11,%XMM0

    (94) 0x40d9a5 VFMADD213SD	(%RSI),%XMM6,%XMM18

    (94) 0x40d9ab VMULSD	%XMM14,%XMM0,%XMM14

    (94) 0x40d9b0 VMOVSD	%XMM18,(%RSI)

    (94) 0x40d9b6 VMULSD	%XMM15,%XMM14,%XMM15

    (94) 0x40d9bb VFNMADD213SD	(%RDI),%XMM15,%XMM2

    (94) 0x40d9c0 VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

    (94) 0x40d9c6 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

    (94) 0x40d9cc VMOVSD	%XMM2,(%RDI)

    (94) 0x40d9d0 VMOVSD	%XMM1,0x8(%RDI)

    (94) 0x40d9d5 VMOVSD	%XMM15,0x10(%RDI)

    (94) 0x40d9da VMOVSD	0x8(%RDX),%XMM1

    (94) 0x40d9df VMOVSD	(%RDX),%XMM2

    (94) 0x40d9e3 VSUBSD	0x20(%RAX),%XMM1,%XMM1

    (94) 0x40d9e8 VSUBSD	0x18(%RAX),%XMM2,%XMM2

    (94) 0x40d9ed VMOVSD	0x10(%RDX),%XMM13

    (94) 0x40d9f2 VMULSD	%XMM1,%XMM1,%XMM0

    (94) 0x40d9f6 VSUBSD	0x28(%RAX),%XMM13,%XMM13

    (94) 0x40d9fb INC	%ECX

    (94) 0x40d9fd LEA	0x18(%RAX),%RSI

    (94) 0x40da01 VFMADD231SD	%XMM2,%XMM2,%XMM0

    (94) 0x40da06 VFMADD231SD	%XMM13,%XMM13,%XMM0

    (94) 0x40da0b VCOMISD	%XMM3,%XMM0

    (94) 0x40da0f JBE	40da8b

    (94) 0x40da11 VCOMISD	%XMM0,%XMM4

    (94) 0x40da15 JB	40da8b

    (94) 0x40da17 VDIVSD	%XMM0,%XMM7,%XMM0

    (94) 0x40da1b MOV	0x30(%R11),%RAX

    (94) 0x40da1f MOV	0x28(%R11),%RDI

    (94) 0x40da23 ADD	%R8,%RAX

    (94) 0x40da26 ADD	%RBX,%RDI

    (94) 0x40da29 VMULSD	%XMM0,%XMM8,%XMM15

    (94) 0x40da2d VMULSD	%XMM0,%XMM0,%XMM14

    (94) 0x40da31 VMULSD	%XMM0,%XMM10,%XMM0

    (94) 0x40da35 VMULSD	%XMM0,%XMM14,%XMM14

    (94) 0x40da39 VSUBSD	%XMM7,%XMM14,%XMM0

    (94) 0x40da3d VFMSUB132SD	%XMM14,%XMM9,%XMM0

    (94) 0x40da42 VMOVAPD	%XMM0,%XMM19

    (94) 0x40da48 VFMADD231SD	%XMM6,%XMM0,%XMM5

    (94) 0x40da4d VMOVAPD	%XMM14,%XMM0

    (94) 0x40da51 VFMADD132SD	%XMM12,%XMM11,%XMM0

    (94) 0x40da56 VFMADD213SD	(%RAX),%XMM6,%XMM19

    (94) 0x40da5c VMULSD	%XMM14,%XMM0,%XMM14

    (94) 0x40da61 VMOVSD	%XMM19,(%RAX)

    (94) 0x40da67 VMULSD	%XMM15,%XMM14,%XMM15

    (94) 0x40da6c VFNMADD213SD	(%RDI),%XMM15,%XMM2

    (94) 0x40da71 VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

    (94) 0x40da77 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

    (94) 0x40da7d VMOVSD	%XMM2,(%RDI)

    (94) 0x40da81 VMOVSD	%XMM1,0x8(%RDI)

    (94) 0x40da86 VMOVSD	%XMM15,0x10(%RDI)

    (94) 0x40da8b INC	%ECX

    (94) 0x40da8d LEA	0x18(%RSI),%RAX

    (94) 0x40da91 CMP	%ECX,%R9D

    (94) 0x40da94 JG	40d930

  (93) 0x40da9a INC	%R12D

  (93) 0x40da9d ADD	$0x8,%R8

  (93) 0x40daa1 CMP	%R12D,%R14D

  (93) 0x40daa4 JG	40d790

0x40daaa MOV	-0x40(%RBP),%RAX

0x40daae MOV	-0x34(%RBP),%EDX

0x40dab1 ADD	$0x4,%RAX

0x40dab5 CMP	%RAX,-0x60(%RBP)

0x40dab9 JNE	40d651

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
○97.57	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.43	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:201-201
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.67
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	13.67
CQA cycles if fully vectorized	0.89
Front-end cycles	13.67
P0 cycles	11.50
P1 cycles	11.13
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	1.00
P5 cycles	10.93
P6 cycles	11.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	10.93
P11 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	82.00
Nb loads	11.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.15
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.70
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	3.85
Vector-efficiency ratio all	7.26
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.45

Metric	Value
CQA speedup if no scalar integer	1.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	ljForce._omp_fn.1
Source	ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:201-201
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.67
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	13.67
CQA cycles if fully vectorized	0.89
Front-end cycles	13.67
P0 cycles	11.50
P1 cycles	11.13
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	1.00
P5 cycles	10.93
P6 cycles	11.50
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	10.93
P11 cycles	3.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	82.00
Nb loads	11.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.15
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.70
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	3.85
Vector-efficiency ratio all	7.26
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.45

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187,191,201.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 4457 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 10.50 cycles (1.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.67 to 0.89 cycles (15.44x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	83
nb uops	82
loop length	278
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	11.13	3.67	3.67	1.00	10.93	11.50	1.00	1.00	1.00	10.93	3.67
cycles	11.50	11.13	3.67	3.67	1.00	10.93	11.50	1.00	1.00	1.00	10.93	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.67
Dispatch	11.50
Overall L1	13.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	6%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	7%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.67 cycles. At this rate:

2% of peak load performance is reached (5.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.88 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.67 to 11.50 cycles (1.19x speedup).

ASM code

In the binary file, the address of the loop is: 40d651

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RAX),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R13D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 40dbc6 <ljForce._omp_fn.1+0x686>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVSXD %R13D,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%RBX,%RDI,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40d73f <ljForce._omp_fn.1+0x1ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
NOT %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SAL $0x6,%R13D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RDI,%RDI,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SAL $0x9,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RDX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x8(%R8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R14D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40d73f <ljForce._omp_fn.1+0x1ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40d72e <ljForce._omp_fn.1+0x1ee>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d71e <ljForce._omp_fn.1+0x1de>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d713 <ljForce._omp_fn.1+0x1d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d708 <ljForce._omp_fn.1+0x1c8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d6fd <ljForce._omp_fn.1+0x1bd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d6ee <ljForce._omp_fn.1+0x1ae>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d6df <ljForce._omp_fn.1+0x19f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40d73f <ljForce._omp_fn.1+0x1ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 40d651 <ljForce._omp_fn.1+0x111>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R11),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x34(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 40d651 <ljForce._omp_fn.1+0x111>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	ljForce._omp_fn.1
Source file and lines	ljForce.c:178-216
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 4457 paths individually, rerun with max-paths=4457
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	83
nb uops	82
loop length	278
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	11.13	3.67	3.67	1.00	10.93	11.50	1.00	1.00	1.00	10.93	3.67
cycles	11.50	11.13	3.67	3.67	1.00	10.93	11.50	1.00	1.00	1.00	10.93	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.67
Dispatch	11.50
Overall L1	13.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

Vector efficiency ratios

INT

all	6%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	7%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.67 cycles. At this rate:

2% of peak load performance is reached (5.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.88 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40d651

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RAX),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R13D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JS 40dbc6 <ljForce._omp_fn.1+0x686>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOVSXD %R13D,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%RBX,%RDI,4),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R15D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40d73f <ljForce._omp_fn.1+0x1ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
NOT %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
SAL $0x6,%R13D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%RDI,%RDI,2),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%R13,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SAL $0x9,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RDX),%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA 0x8(%R8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R14D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40d73f <ljForce._omp_fn.1+0x1ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40d72e <ljForce._omp_fn.1+0x1ee>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d71e <ljForce._omp_fn.1+0x1de>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d713 <ljForce._omp_fn.1+0x1d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d708 <ljForce._omp_fn.1+0x1c8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d6fd <ljForce._omp_fn.1+0x1bd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d6ee <ljForce._omp_fn.1+0x1ae>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40d6df <ljForce._omp_fn.1+0x19f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST %ESI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d77a <ljForce._omp_fn.1+0x23a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD $0x8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14D,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40d73f <ljForce._omp_fn.1+0x1ff>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 40d651 <ljForce._omp_fn.1+0x111>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x58(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R11),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x34(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 40d651 <ljForce._omp_fn.1+0x111>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code