OV - exec - Loop 84

	Loop Id: 84	Module: exec	Source: linkCells.c:211-373 [...]	Coverage: 0.55%

0x40ca42 MOVSXD	%R15D,%R8

0x40ca45 LEA	(%R8,%R8,2),%R9

0x40ca49 LEA	(%R10,%R9,8),%R11

0x40ca4d VMOVSD	(%R11),%XMM2    [1]

0x40ca52 VMOVSD	0x8(%R11),%XMM1    [1]

0x40ca58 VCOMISD	0x30(%RBX),%XMM2    [4]

0x40ca5d VMOVSD	0x10(%R11),%XMM0    [1]

0x40ca63 MOV	%EDI,%EAX

0x40ca65 JAE	40ca85

0x40ca67 VSUBSD	0x18(%RBX),%XMM2,%XMM3    [4]

0x40ca6c XOR	%EDX,%EDX

0x40ca6e VMULSD	0x60(%RBX),%XMM3,%XMM4    [4]

0x40ca73 VRNDSCALESD	$0x9,%XMM4,%XMM4,%XMM5

0x40ca7a VCVTTSD2SI	%XMM5,%EAX

0x40ca7e CMP	%EDI,%EAX

0x40ca80 SETE	%DL

0x40ca83 SUB	%EDX,%EAX

0x40ca85 VCOMISD	0x38(%RBX),%XMM1    [4]

0x40ca8a MOV	%ECX,%R8D

0x40ca8d JAE	40cab2

0x40ca8f VSUBSD	0x20(%RBX),%XMM1,%XMM6    [4]

0x40ca94 XOR	%R9D,%R9D

0x40ca97 VMULSD	0x68(%RBX),%XMM6,%XMM7    [4]

0x40ca9c VRNDSCALESD	$0x9,%XMM7,%XMM7,%XMM8

0x40caa3 VCVTTSD2SI	%XMM8,%R8D

0x40caa8 CMP	%ECX,%R8D

0x40caab SETE	%R9B

0x40caaf SUB	%R9D,%R8D

0x40cab2 VCOMISD	0x40(%RBX),%XMM0    [4]

0x40cab7 JAE	40cba0

0x40cabd VSUBSD	0x28(%RBX),%XMM0,%XMM9    [4]

0x40cac2 XOR	%R9D,%R9D

0x40cac5 VMULSD	0x70(%RBX),%XMM9,%XMM10    [4]

0x40caca VRNDSCALESD	$0x9,%XMM10,%XMM10,%XMM11

0x40cad1 VCVTTSD2SI	%XMM11,%EDX

0x40cad6 CMP	%ESI,%EDX

0x40cad8 SETE	%R9B

0x40cadc SUB	%R9D,%EDX

0x40cadf CMP	$-0x1,%EDX

0x40cae2 JE	40cbe0

0x40cae8 CMP	%ECX,%R8D

0x40caeb JE	40cc18

0x40caf1 CMP	$-0x1,%R8D

0x40caf5 JE	40cc50

0x40cafb CMP	%EDI,%EAX

0x40cafd JE	40cc78

0x40cb03 CMP	$-0x1,%EAX

0x40cb06 JE	40cc98

0x40cb0c IMUL	%EDI,%R8D

0x40cb10 ADD	%EAX,%R8D

0x40cb13 MOV	%ECX,%EAX

0x40cb15 IMUL	%EDI,%EAX

0x40cb18 IMUL	%EDX,%EAX

0x40cb1b ADD	%EAX,%R8D

0x40cb1e XCHG	%AX,%AX

0x40cb20 TEST	%R8D,%R8D

0x40cb23 JS	40cca6

0x40cb29 CMP	0x14(%RBX),%R8D    [4]

0x40cb2d JGE	40ccbf

0x40cb33 CMP	%R13D,%R8D

0x40cb36 JE	40cb80

0x40cb80 MOV	-0x38(%RBP),%R15    [2]

0x40cb84 INC	%R14D

0x40cb87 CMP	%R14D,(%R12,%R15,1)    [3]

0x40cb8b JLE	40cb5c

0x40cb8d MOV	-0x48(%RBP),%EAX    [2]

0x40cb90 LEA	(%RAX,%R14,1),%R15D

0x40cb94 JMP	40ca42

0x40cba0 MOV	%ESI,%R11D

0x40cba3 IMUL	%ECX,%R11D

0x40cba7 MOV	0xc(%RBX),%EDX    [4]

0x40cbaa LEA	0x2(%RDI),%R9D

0x40cbae LEA	(%RDX,%R11,2),%EDX

0x40cbb2 MOV	%R9D,%R11D

0x40cbb5 IMUL	%ESI,%R11D

0x40cbb9 INC	%R8D

0x40cbbc IMUL	%R9D,%R8D

0x40cbc0 LEA	(%RDX,%R11,2),%EDX

0x40cbc4 LEA	0x2(%RCX),%R11D

0x40cbc8 IMUL	%R9D,%R11D

0x40cbcc ADD	%R11D,%EDX

0x40cbcf ADD	%EDX,%R8D

0x40cbd2 LEA	0x1(%R8,%RAX,1),%R8D

0x40cbd7 JMP	40cb20

0x40cbe0 MOV	%ESI,%R11D

0x40cbe3 IMUL	%ECX,%R11D

0x40cbe7 MOV	0xc(%RBX),%EDX    [4]

0x40cbea LEA	0x2(%RDI),%R9D

0x40cbee LEA	(%RDX,%R11,2),%EDX

0x40cbf2 MOV	%R9D,%R11D

0x40cbf5 IMUL	%ESI,%R11D

0x40cbf9 INC	%R8D

0x40cbfc IMUL	%R9D,%R8D

0x40cc00 LEA	(%RDX,%R11,2),%EDX

0x40cc04 ADD	%EDX,%R8D

0x40cc07 LEA	0x1(%R8,%RAX,1),%R8D

0x40cc0c JMP	40cb20

0x40cc18 MOV	%ESI,%R11D

0x40cc1b IMUL	%ECX,%R11D

0x40cc1f MOV	0xc(%RBX),%R8D    [4]

0x40cc23 LEA	0x2(%RDI),%R9D

0x40cc27 LEA	(%R8,%R11,2),%R8D

0x40cc2b MOV	%R9D,%R11D

0x40cc2e IMUL	%ESI,%R11D

0x40cc32 IMUL	%EDX,%R9D

0x40cc36 ADD	%R11D,%R8D

0x40cc39 LEA	(%R8,%R9,1),%EDX

0x40cc3d LEA	0x1(%RDX,%RAX,1),%R8D

0x40cc42 JMP	40cb20

0x40cc50 MOV	%ESI,%R9D

0x40cc53 IMUL	%ECX,%R9D

0x40cc57 MOV	0xc(%RBX),%R8D    [4]

0x40cc5b LEA	(%R8,%R9,2),%R11D

0x40cc5f LEA	0x2(%RDI),%R9D

0x40cc63 IMUL	%R9D,%EDX

0x40cc67 ADD	%R11D,%EDX

0x40cc6a LEA	0x1(%RDX,%RAX,1),%R8D

0x40cc6f JMP	40cb20

0x40cc78 MOV	%ESI,%R11D

0x40cc7b IMUL	%ECX,%R11D

0x40cc7f IMUL	%ECX,%EDX

0x40cc82 ADD	0xc(%RBX),%R11D    [4]

0x40cc86 ADD	%R11D,%EDX

0x40cc89 ADD	%EDX,%R8D

0x40cc8c JMP	40cb20

0x40cc98 IMUL	%ECX,%EDX

0x40cc9b ADD	0xc(%RBX),%EDX    [4]

0x40cc9e ADD	%EDX,%R8D

0x40cca1 JMP	40cb20

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 373

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

Coverage (%)	Name	Source Location	Module
►61.94+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►36.19+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
►1.77+	redistributeAtoms	timestep.c:148	exec
○	main	CoMD.c:207	exec
○	__libc_start_call_main		libc.so.6

Path /

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	3.39
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.34
Bottlenecks	P1,
Function	updateLinkCells
Source	linkCells.c:211-247,linkCells.c:295-301,linkCells.c:352-373
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.73
CQA cycles if no scalar integer	14.53
CQA cycles if FP arith vectorized	9.06
CQA cycles if fully vectorized	1.92
Front-end cycles	23.00
P0 cycles	19.60
P1 cycles	30.73
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.00
P5 cycles	19.80
P6 cycles	19.80
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	19.80
P11 cycles	7.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	137.00
Nb loads	22.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.20
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.56
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.00
Vector-efficiency ratio load	11.61
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.93

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	3.39
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.34
Bottlenecks	P1,
Function	updateLinkCells
Source	linkCells.c:211-247,linkCells.c:295-301,linkCells.c:352-373
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	30.73
CQA cycles if no scalar integer	14.53
CQA cycles if FP arith vectorized	9.06
CQA cycles if fully vectorized	1.92
Front-end cycles	23.00
P0 cycles	19.60
P1 cycles	30.73
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.00
P5 cycles	19.80
P6 cycles	19.80
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	19.80
P11 cycles	7.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	137.00
Nb loads	22.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.20
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.56
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.00
Vector-efficiency ratio load	11.61
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	updateLinkCells
Source file and lines	linkCells.c:211-373
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,295-301,352-373.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=28
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 28 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 30.73 to 14.53 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 30.73 to 1.92 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 30.73 to 23.00 cycles (1.34x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:359
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 140 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	137
loop length	502
used x86 registers	15
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	23.00 cycles
front end	23.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	19.60	22.00	7.33	7.33	0.00	19.80	19.80	0.00	0.00	0.00	19.80	7.33
cycles	19.60	30.73	7.33	7.33	0.00	19.80	19.80	0.00	0.00	0.00	19.80	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.00
Dispatch	30.73
Overall L1	30.73

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.73 cycles. At this rate:

2% of peak load performance is reached (4.56 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ca42

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD %R15D,%R8	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
LEA (%R8,%R8,2),%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R9,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R11),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%R11),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x30(%RBX),%XMM2	2	1	0	0.33	0.33	0	0	0	0.33	3	1	scal (12.5%)
VMOVSD 0x10(%R11),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JAE 40ca85 <updateLinkCells+0xe5>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VSUBSD 0x18(%RBX),%XMM2,%XMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x60(%RBX),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM4,%XMM4,%XMM5	2	1	1	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM5,%EAX	2	1.50	0.50	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %EDI,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
SETE %DL	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
SUB %EDX,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VCOMISD 0x38(%RBX),%XMM1	2	1	0	0.33	0.33	0	0	0	0.33	3	1	scal (12.5%)
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JAE 40cab2 <updateLinkCells+0x112>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VSUBSD 0x20(%RBX),%XMM1,%XMM6	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x68(%RBX),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM8	2	1	1	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM8,%R8D	2	1.50	0.50	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ECX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
SETE %R9B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
SUB %R9D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VCOMISD 0x40(%RBX),%XMM0	2	1	0	0.33	0.33	0	0	0	0.33	3	1	scal (12.5%)
JAE 40cba0 <updateLinkCells+0x200>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VSUBSD 0x28(%RBX),%XMM0,%XMM9	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x70(%RBX),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM10,%XMM10,%XMM11	2	1	1	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM11,%EDX	2	1.50	0.50	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ESI,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
SETE %R9B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
SUB %R9D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP $-0x1,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cbe0 <updateLinkCells+0x240>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %ECX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc18 <updateLinkCells+0x278>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $-0x1,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc50 <updateLinkCells+0x2b0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %EDI,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc78 <updateLinkCells+0x2d8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $-0x1,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc98 <updateLinkCells+0x2f8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EDI,%EAX	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (6.3%)
JS 40cca6 <updateLinkCells+0x306>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP 0x14(%RBX),%R8D	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (6.3%)
JGE 40ccbf <updateLinkCells+0x31f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %R13D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cb80 <updateLinkCells+0x1e0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
INC %R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP %R14D,(%R12,%R15,1)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (6.3%)
JLE 40cb5c <updateLinkCells+0x1bc>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R14,1),%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
JMP 40ca42 <updateLinkCells+0xa2>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
INC %R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA 0x2(%RCX),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
IMUL %R9D,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %R11D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA 0x1(%R8,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
INC %R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA 0x1(%R8,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%R8D	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%R8,%R11,2),%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%R9D	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %R11D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA (%R8,%R9,1),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA 0x1(%RDX,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%R8D	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R9,2),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
IMUL %R9D,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %R11D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA 0x1(%RDX,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD 0xc(%RBX),%R11D	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
ADD %R11D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD 0xc(%RBX),%EDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	updateLinkCells
Source file and lines	linkCells.c:211-373
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=28
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Recompile with march=sapphirerapids. CQA target is Granite_Rapids_ad (Intel(R) Xeon(R) Granite Rapids) but specialization flags are -march=graniterapids
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:359
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:365
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:371
VCVTTSD2SI: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354
VRNDSCALESD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTSD2SI (FP64 to INT32/64, scalar): 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:352
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:353
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:354

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 140 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	137
loop length	502
used x86 registers	15
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	23.00 cycles
front end	23.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	19.60	22.00	7.33	7.33	0.00	19.80	19.80	0.00	0.00	0.00	19.80	7.33
cycles	19.60	30.73	7.33	7.33	0.00	19.80	19.80	0.00	0.00	0.00	19.80	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.00
Dispatch	30.73
Overall L1	30.73

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 30.73 cycles. At this rate:

2% of peak load performance is reached (4.56 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ca42

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD %R15D,%R8	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
LEA (%R8,%R8,2),%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R9,8),%R11	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%R11),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%R11),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x30(%RBX),%XMM2	2	1	0	0.33	0.33	0	0	0	0.33	3	1	scal (12.5%)
VMOVSD 0x10(%R11),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JAE 40ca85 <updateLinkCells+0xe5>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VSUBSD 0x18(%RBX),%XMM2,%XMM3	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x60(%RBX),%XMM3,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM4,%XMM4,%XMM5	2	1	1	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM5,%EAX	2	1.50	0.50	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %EDI,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
SETE %DL	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
SUB %EDX,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VCOMISD 0x38(%RBX),%XMM1	2	1	0	0.33	0.33	0	0	0	0.33	3	1	scal (12.5%)
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JAE 40cab2 <updateLinkCells+0x112>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VSUBSD 0x20(%RBX),%XMM1,%XMM6	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x68(%RBX),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM7,%XMM7,%XMM8	2	1	1	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM8,%R8D	2	1.50	0.50	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ECX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
SETE %R9B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
SUB %R9D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VCOMISD 0x40(%RBX),%XMM0	2	1	0	0.33	0.33	0	0	0	0.33	3	1	scal (12.5%)
JAE 40cba0 <updateLinkCells+0x200>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VSUBSD 0x28(%RBX),%XMM0,%XMM9	1	0	0.50	0.33	0.33	0.50	0	0	0.33	3	0.50	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMULSD 0x70(%RBX),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VRNDSCALESD $0x9,%XMM10,%XMM10,%XMM11	2	1	1	0	0	0	0	0	0	8	1	scal (12.5%)
VCVTTSD2SI %XMM11,%EDX	2	1.50	0.50	0	0	0	0	0	0	7	1	scal (12.5%)
CMP %ESI,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
SETE %R9B	1	0.50	0	0	0	0	0.50	0	0	1	0.50	N/A
SUB %R9D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP $-0x1,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cbe0 <updateLinkCells+0x240>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %ECX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc18 <updateLinkCells+0x278>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $-0x1,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc50 <updateLinkCells+0x2b0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %EDI,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc78 <updateLinkCells+0x2d8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP $-0x1,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cc98 <updateLinkCells+0x2f8>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
IMUL %EDI,%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EDI,%EAX	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%EAX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	scal (6.3%)
JS 40cca6 <updateLinkCells+0x306>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP 0x14(%RBX),%R8D	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (6.3%)
JGE 40ccbf <updateLinkCells+0x31f>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMP %R13D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JE 40cb80 <updateLinkCells+0x1e0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x38(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
INC %R14D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
CMP %R14D,(%R12,%R15,1)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (6.3%)
JLE 40cb5c <updateLinkCells+0x1bc>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x48(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R14,1),%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
JMP 40ca42 <updateLinkCells+0xa2>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
INC %R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA 0x2(%RCX),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
IMUL %R9D,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %R11D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA 0x1(%R8,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%EDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
INC %R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
IMUL %R9D,%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
LEA (%RDX,%R11,2),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA 0x1(%R8,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%R8D	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%R8,%R11,2),%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ESI,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %EDX,%R9D	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %R11D,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA (%R8,%R9,1),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA 0x1(%RDX,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R9D	1	0	1	0	0	0	0	0	0	3	1	N/A
MOV 0xc(%RBX),%R8D	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R9,2),%R11D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA 0x2(%RDI),%R9D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
IMUL %R9D,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %R11D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
LEA 0x1(%RDX,%RAX,1),%R8D	1	0	1	0	0	0	0	0	0	3	1	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %ESI,%R11D	1	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R11D	1	0	1	0	0	0	0	0	0	3	1	N/A
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD 0xc(%RBX),%R11D	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
ADD %R11D,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD 0xc(%RBX),%EDX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
ADD %EDX,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JMP 40cb20 <updateLinkCells+0x180>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code