OV - exec - Loop 61

	Loop Id: 61	Module: exec	Source: haloExchange.c:621-628	Coverage: 0.39%

0x4094e0 MOV	-0x38(%RBP),%RSI    [4]

0x4094e4 LEA	(%R11,%R8,1),%RDI

0x4094e8 VMOVD	(%RDI),%XMM7    [3]

0x4094ec LEA	(%RSI,%R8,1),%RSI

0x4094f0 VMOVD	0x1c(%RDI),%XMM0    [3]

0x4094f5 VMOVD	0x18(%RDI),%XMM1    [3]

0x4094fa VMOVD	0x10(%RDI),%XMM3    [3]

0x4094ff VMOVD	0xc(%RDI),%XMM4    [3]

0x409504 VMOVD	0x8(%RDI),%XMM5    [3]

0x409509 VMOVD	0x4(%RDI),%XMM6    [3]

0x40950e VMOVD	0x14(%RDI),%XMM2    [3]

0x409513 MOV	0x4(%RSI),%R15D    [2]

0x409517 MOV	0x1c(%RSI),%R9D    [2]

0x40951b MOV	0x18(%RSI),%R10D    [2]

0x40951f MOV	0x14(%RSI),%EBX    [2]

0x409522 MOV	0x10(%RSI),%R12D    [2]

0x409526 MOV	0xc(%RSI),%R13D    [2]

0x40952a MOV	0x8(%RSI),%R14D    [2]

0x40952e VPINSRD	$0x1,(%RSI),%XMM7,%XMM8    [2]

0x409534 VPINSRD	$0x1,%R15D,%XMM6,%XMM9

0x40953a VPINSRD	$0x1,%R14D,%XMM5,%XMM10

0x409540 VPINSRD	$0x1,%R13D,%XMM4,%XMM11

0x409546 VPINSRD	$0x1,%R12D,%XMM3,%XMM12

0x40954c VPINSRD	$0x1,%EBX,%XMM2,%XMM13

0x409552 VPINSRD	$0x1,%R10D,%XMM1,%XMM14

0x409558 VPINSRD	$0x1,%R9D,%XMM0,%XMM15

0x40955e VMOVUPD	(%RDX),%XMM19    [5]

0x409564 VMOVSD	0x18(%RDX),%XMM17    [5]

0x40956b VMOVSD	0x10(%RDX),%XMM18    [5]

0x409572 VMOVSD	0x28(%RDX),%XMM16    [5]

0x409579 VMOVSD	0x20(%RDX),%XMM3    [5]

0x40957e VMOVQ	%XMM8,-0x8(%RAX)    [1]

0x409583 VMOVQ	%XMM9,0x30(%RAX)    [1]

0x409588 VMOVQ	%XMM10,0x68(%RAX)    [1]

0x40958d VMOVQ	%XMM11,0xa0(%RAX)    [1]

0x409595 VMOVQ	%XMM12,0xd8(%RAX)    [1]

0x40959d VMOVQ	%XMM13,0x110(%RAX)    [1]

0x4095a5 VMOVSD	0x58(%RDX),%XMM12    [5]

0x4095aa VMOVQ	%XMM14,0x148(%RAX)    [1]

0x4095b2 VMOVQ	%XMM15,0x180(%RAX)    [1]

0x4095ba VMOVUPD	0x30(%RDX),%XMM15    [5]

0x4095bf VMOVSD	0x50(%RDX),%XMM2    [5]

0x4095c4 VMOVSD	0x48(%RDX),%XMM13    [5]

0x4095c9 VMOVSD	0x78(%RDX),%XMM9    [5]

0x4095ce VMOVSD	0x80(%RDX),%XMM1    [5]

0x4095d6 VMOVSD	0xb0(%RDX),%XMM0    [5]

0x4095de VMOVSD	0xa8(%RDX),%XMM5    [5]

0x4095e6 VMOVSD	0x40(%RDX),%XMM14    [5]

0x4095eb VMOVUPD	0x60(%RDX),%XMM11    [5]

0x4095f0 VMOVSD	0x70(%RDX),%XMM10    [5]

0x4095f5 VMOVUPD	0x90(%RDX),%XMM7    [5]

0x4095fd VMOVSD	0x88(%RDX),%XMM8    [5]

0x409605 VMOVSD	0xb8(%RDX),%XMM4    [5]

0x40960d VMOVSD	0xa0(%RDX),%XMM6    [5]

0x409615 VUNPCKLPD	%XMM3,%XMM17,%XMM3

0x40961b VMOVUPD	%XMM15,0x70(%RAX)    [1]

0x409620 VMOVSD	%XMM12,0xb8(%RAX)    [1]

0x409628 VUNPCKLPD	%XMM2,%XMM13,%XMM15

0x40962c VUNPCKLPD	%XMM1,%XMM9,%XMM12

0x409630 VUNPCKLPD	%XMM0,%XMM5,%XMM2

0x409634 VMOVUPD	%XMM3,0x38(%RAX)    [1]

0x409639 VMOVSD	%XMM14,0x80(%RAX)    [1]

0x409641 VMOVUPD	%XMM11,0xe0(%RAX)    [1]

0x409649 VMOVSD	%XMM10,0xf0(%RAX)    [1]

0x409651 VMOVUPD	%XMM12,0x118(%RAX)    [1]

0x409659 VMOVSD	%XMM8,0x128(%RAX)    [1]

0x409661 VMOVUPD	%XMM7,0x150(%RAX)    [1]

0x409669 VMOVSD	%XMM6,0x160(%RAX)    [1]

0x409671 VMOVUPD	%XMM2,0x188(%RAX)    [1]

0x409679 VMOVSD	%XMM4,0x198(%RAX)    [1]

0x409681 VMOVUPD	%XMM19,(%RAX)    [1]

0x409687 VMOVSD	%XMM18,0x10(%RAX)    [1]

0x40968e VMOVSD	%XMM16,0x48(%RAX)    [1]

0x409695 VMOVUPD	%XMM15,0xa8(%RAX)    [1]

0x40969d VMOVUPD	(%RCX),%XMM20    [6]

0x4096a3 VMOVSD	0x18(%RCX),%XMM21    [6]

0x4096aa VMOVSD	0x10(%RCX),%XMM22    [6]

0x4096b1 VMOVUPD	0x30(%RCX),%XMM15    [6]

0x4096b6 VMOVSD	0x50(%RCX),%XMM2    [6]

0x4096bb VMOVSD	0x20(%RCX),%XMM3    [6]

0x4096c0 VMOVSD	0x58(%RCX),%XMM12    [6]

0x4096c5 VMOVSD	0x48(%RCX),%XMM13    [6]

0x4096ca VMOVSD	0x78(%RCX),%XMM9    [6]

0x4096cf VMOVSD	0x80(%RCX),%XMM1    [6]

0x4096d7 VMOVSD	0xb0(%RCX),%XMM0    [6]

0x4096df VMOVSD	0xa8(%RCX),%XMM5    [6]

0x4096e7 VMOVSD	0x28(%RCX),%XMM23    [6]

0x4096ee VMOVSD	0x40(%RCX),%XMM14    [6]

0x4096f3 VMOVUPD	0x60(%RCX),%XMM11    [6]

0x4096f8 VMOVSD	0x70(%RCX),%XMM10    [6]

0x4096fd VMOVUPD	0x90(%RCX),%XMM7    [6]

0x409705 VMOVSD	0x88(%RCX),%XMM8    [6]

0x40970d VMOVSD	0xb8(%RCX),%XMM4    [6]

0x409715 VMOVSD	0xa0(%RCX),%XMM6    [6]

0x40971d VUNPCKLPD	%XMM3,%XMM21,%XMM3

0x409723 VMOVUPD	%XMM15,0x88(%RAX)    [1]

0x40972b VMOVSD	%XMM12,0xd0(%RAX)    [1]

0x409733 VUNPCKLPD	%XMM2,%XMM13,%XMM15

0x409737 VUNPCKLPD	%XMM1,%XMM9,%XMM12

0x40973b VUNPCKLPD	%XMM0,%XMM5,%XMM2

0x40973f ADD	$0x20,%R8

0x409743 VMOVUPD	%XMM20,0x18(%RAX)    [1]

0x40974d VMOVSD	%XMM22,0x28(%RAX)    [1]

0x409754 VMOVUPD	%XMM3,0x50(%RAX)    [1]

0x409759 VMOVSD	%XMM23,0x60(%RAX)    [1]

0x409760 VMOVSD	%XMM14,0x98(%RAX)    [1]

0x409768 VMOVUPD	%XMM15,0xc0(%RAX)    [1]

0x409770 VMOVUPD	%XMM11,0xf8(%RAX)    [1]

0x409778 VMOVSD	%XMM10,0x108(%RAX)    [1]

0x409780 VMOVUPD	%XMM12,0x130(%RAX)    [1]

0x409788 VMOVSD	%XMM8,0x140(%RAX)    [1]

0x409790 VMOVUPD	%XMM7,0x168(%RAX)    [1]

0x409798 VMOVSD	%XMM6,0x178(%RAX)    [1]

0x4097a0 VMOVUPD	%XMM2,0x1a0(%RAX)    [1]

0x4097a8 ADD	$0xc0,%RDX

0x4097af VMOVSD	%XMM4,0x1b0(%RAX)    [1]

0x4097b7 ADD	$0xc0,%RCX

0x4097be ADD	$0x1c0,%RAX

0x4097c4 CMP	%R8,-0x48(%RBP)    [4]

0x4097c8 JNE	4094e0

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 621 - 628

--------------------------------------------------------------------------------

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

Coverage (%)	Name	Source Location	Module
►13.93+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►13.67+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►13.02+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►12.76+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►11.85+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►11.46+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►10.55+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►10.16+	redistributeAtoms._omp_fn.0	timestep.c:154	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	sortAtomsInCell
Source	haloExchange.c:621-628
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	21.17
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	21.17
CQA cycles if fully vectorized	3.50
Front-end cycles	21.17
P0 cycles	1.30
P1 cycles	8.00
P2 cycles	19.33
P3 cycles	19.33
P4 cycles	20.00
P5 cycles	15.00
P6 cycles	1.30
P7 cycles	20.00
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	1.40
P11 cycles	19.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	120.00
Nb uops	127.00
Nb loads	58.00
Nb stores	40.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	43.09
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	448.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	21.62
Vectorization ratio load	14.29
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.91
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	17.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	sortAtomsInCell
Source	haloExchange.c:621-628
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	21.17
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	21.17
CQA cycles if fully vectorized	3.50
Front-end cycles	21.17
P0 cycles	1.30
P1 cycles	8.00
P2 cycles	19.33
P3 cycles	19.33
P4 cycles	20.00
P5 cycles	15.00
P6 cycles	1.30
P7 cycles	20.00
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	1.40
P11 cycles	19.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	120.00
Nb uops	127.00
Nb loads	58.00
Nb stores	40.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	43.09
Bytes prefetched	0.00
Bytes loaded	464.00
Bytes stored	448.00
Stride 0	1.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	21.62
Vectorization ratio load	14.29
Vectorization ratio store	40.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	13.91
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	17.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-628
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-628.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.17 to 20.00 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 21.17 to 3.50 cycles (6.05x speedup).

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPINSRD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 464 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	120
nb uops	127
loop length	750
used x86 registers	15
used mmx registers	0
used xmm registers	24
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.30	8.00	19.33	19.33	20.00	15.00	1.30	20.00	20.00	20.00	1.40	19.33
cycles	1.30	8.00	19.33	19.33	20.00	15.00	1.30	20.00	20.00	20.00	1.40	19.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	21.17
Dispatch	20.00
Data deps.	1.00
Overall L1	21.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	30%
load	20%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	21%
load	14%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	13%
load	12%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.17 cycles. At this rate:

11% of peak load performance is reached (21.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.17 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.17 to 20.00 cycles (1.06x speedup).

ASM code

In the binary file, the address of the loop is: 4094e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%R8,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD (%RDI),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
LEA (%RSI,%R8,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD 0x1c(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x18(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x10(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0xc(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x8(%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x4(%RDI),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x14(%RDI),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x4(%RSI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x1c(%RSI),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%RSI),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x14(%RSI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%RSI),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0xc(%RSI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%RSI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPINSRD $0x1,(%RSI),%XMM7,%XMM8	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1-4	0.50	scal (6.3%)
VPINSRD $0x1,%R15D,%XMM6,%XMM9	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R14D,%XMM5,%XMM10	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R13D,%XMM4,%XMM11	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R12D,%XMM3,%XMM12	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%EBX,%XMM2,%XMM13	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R10D,%XMM1,%XMM14	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R9D,%XMM0,%XMM15	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VMOVUPD (%RDX),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x18(%RDX),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RDX),%XMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x28(%RDX),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x20(%RDX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ %XMM8,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM9,0x30(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM10,0x68(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM11,0xa0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM12,0xd8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM13,0x110(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x58(%RDX),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ %XMM14,0x148(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM15,0x180(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD 0x30(%RDX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x50(%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x48(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x78(%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x80(%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0(%RDX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa8(%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x40(%RDX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x60(%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x70(%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x90(%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x88(%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb8(%RDX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa0(%RDX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUNPCKLPD %XMM3,%XMM17,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD %XMM15,0x70(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM12,0xb8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VUNPCKLPD %XMM2,%XMM13,%XMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM1,%XMM9,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM0,%XMM5,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD %XMM3,0x38(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM14,0x80(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM11,0xe0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM10,0xf0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM12,0x118(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM8,0x128(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM7,0x150(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM6,0x160(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM2,0x188(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM4,0x198(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM19,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM18,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM16,0x48(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM15,0xa8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD (%RCX),%XMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x18(%RCX),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RCX),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x30(%RCX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x50(%RCX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x20(%RCX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x58(%RCX),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x48(%RCX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x78(%RCX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x80(%RCX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0(%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa8(%RCX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x28(%RCX),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x40(%RCX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x60(%RCX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x70(%RCX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x90(%RCX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x88(%RCX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb8(%RCX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa0(%RCX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUNPCKLPD %XMM3,%XMM21,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD %XMM15,0x88(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM12,0xd0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VUNPCKLPD %XMM2,%XMM13,%XMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM1,%XMM9,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM0,%XMM5,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
ADD $0x20,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM20,0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM22,0x28(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM3,0x50(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM23,0x60(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM14,0x98(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM15,0xc0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM11,0xf8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM10,0x108(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM12,0x130(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM8,0x140(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM7,0x168(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM6,0x178(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM2,0x1a0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0xc0,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,0x1b0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0xc0,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x1c0,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 4094e0 <sortAtomsInCell+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-628
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

14% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPINSRD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:624

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 464 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	120
nb uops	127
loop length	750
used x86 registers	15
used mmx registers	0
used xmm registers	24
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.30	8.00	19.33	19.33	20.00	15.00	1.30	20.00	20.00	20.00	1.40	19.33
cycles	1.30	8.00	19.33	19.33	20.00	15.00	1.30	20.00	20.00	20.00	1.40	19.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	21.17
Dispatch	20.00
Data deps.	1.00
Overall L1	21.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	30%
load	20%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	21%
load	14%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	13%
load	12%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.17 cycles. At this rate:

11% of peak load performance is reached (21.92 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.17 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4094e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R11,%R8,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD (%RDI),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
LEA (%RSI,%R8,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD 0x1c(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x18(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x10(%RDI),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0xc(%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x8(%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x4(%RDI),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVD 0x14(%RDI),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x4(%RSI),%R15D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x1c(%RSI),%R9D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x18(%RSI),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x14(%RSI),%EBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%RSI),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0xc(%RSI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x8(%RSI),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VPINSRD $0x1,(%RSI),%XMM7,%XMM8	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1-4	0.50	scal (6.3%)
VPINSRD $0x1,%R15D,%XMM6,%XMM9	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R14D,%XMM5,%XMM10	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R13D,%XMM4,%XMM11	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R12D,%XMM3,%XMM12	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%EBX,%XMM2,%XMM13	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R10D,%XMM1,%XMM14	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VPINSRD $0x1,%R9D,%XMM0,%XMM15	2	0	0.50	0	0	0	1.50	0	0	0	0	0	0	1-4	1	scal (6.3%)
VMOVUPD (%RDX),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x18(%RDX),%XMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RDX),%XMM18	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x28(%RDX),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x20(%RDX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ %XMM8,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM9,0x30(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM10,0x68(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM11,0xa0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM12,0xd8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM13,0x110(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x58(%RDX),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVQ %XMM14,0x148(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM15,0x180(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD 0x30(%RDX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x50(%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x48(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x78(%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x80(%RDX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0(%RDX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa8(%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x40(%RDX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x60(%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x70(%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x90(%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x88(%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb8(%RDX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa0(%RDX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUNPCKLPD %XMM3,%XMM17,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD %XMM15,0x70(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM12,0xb8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VUNPCKLPD %XMM2,%XMM13,%XMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM1,%XMM9,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM0,%XMM5,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD %XMM3,0x38(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM14,0x80(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM11,0xe0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM10,0xf0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM12,0x118(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM8,0x128(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM7,0x150(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM6,0x160(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM2,0x188(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM4,0x198(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM19,(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM18,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM16,0x48(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM15,0xa8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD (%RCX),%XMM20	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x18(%RCX),%XMM21	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RCX),%XMM22	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x30(%RCX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x50(%RCX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x20(%RCX),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x58(%RCX),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x48(%RCX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x78(%RCX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x80(%RCX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb0(%RCX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa8(%RCX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x28(%RCX),%XMM23	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x40(%RCX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x60(%RCX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x70(%RCX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVUPD 0x90(%RCX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVSD 0x88(%RCX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xb8(%RCX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0xa0(%RCX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VUNPCKLPD %XMM3,%XMM21,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVUPD %XMM15,0x88(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM12,0xd0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VUNPCKLPD %XMM2,%XMM13,%XMM15	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM1,%XMM9,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VUNPCKLPD %XMM0,%XMM5,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
ADD $0x20,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %XMM20,0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM22,0x28(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM3,0x50(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM23,0x60(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM14,0x98(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM15,0xc0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM11,0xf8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM10,0x108(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM12,0x130(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM8,0x140(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM7,0x168(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSD %XMM6,0x178(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVUPD %XMM2,0x1a0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0xc0,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,0x1b0(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0xc0,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x1c0,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 4094e0 <sortAtomsInCell+0x190>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code