OV - exec - Loop 110

	Loop Id: 110	Module: exec	Source: timestep.c:110-115	Coverage: 0.03%

0x410ec0 VMOVUPD	0x20(%RDX),%YMM14    [3]

0x410ec5 VMOVUPD	(%RDX),%YMM1    [3]

0x410ec9 VMOVUPD	0x40(%RDX),%YMM3    [3]

0x410ece VMOVAPD	%YMM1,%YMM4

0x410ed2 VMOVAPD	%YMM1,%YMM15

0x410ed6 VPERMT2PD	%YMM14,%YMM7,%YMM1

0x410edc VPERMT2PD	%YMM3,%YMM6,%YMM1

0x410ee2 VMOVAPD	%YMM1,%YMM2

0x410ee6 VMOVUPD	0x60(%RDX),%YMM1    [3]

0x410eeb VMOVUPD	0x80(%RDX),%YMM17    [3]

0x410ef2 VMOVUPD	0xa0(%RDX),%YMM16    [3]

0x410ef9 VPERMT2PD	%YMM14,%YMM11,%YMM4

0x410eff VPERMT2PD	%YMM14,%YMM9,%YMM15

0x410f05 VMOVAPD	%YMM1,%YMM14

0x410f09 VPERMT2PD	%YMM17,%YMM9,%YMM14

0x410f0f VPERMT2PD	%YMM3,%YMM8,%YMM15

0x410f15 VPERMT2PD	%YMM16,%YMM8,%YMM14

0x410f1b VMULPD	%YMM14,%YMM14,%YMM14

0x410f20 VMULPD	%YMM15,%YMM15,%YMM15

0x410f25 VPERMT2PD	%YMM3,%YMM10,%YMM4

0x410f2b VMOVAPD	%YMM1,%YMM3

0x410f2f VPERMT2PD	%YMM17,%YMM11,%YMM3

0x410f35 VPERMT2PD	%YMM16,%YMM10,%YMM3

0x410f3b VFMADD132PD	%YMM4,%YMM15,%YMM4

0x410f40 VFMADD132PD	%YMM3,%YMM14,%YMM3

0x410f45 MOVSXD	(%RAX),%RDI    [1]

0x410f48 MOVSXD	0x8(%RAX),%R14    [1]

0x410f4c VPERMT2PD	%YMM17,%YMM7,%YMM1

0x410f52 MOVSXD	0x4(%RAX),%RSI    [1]

0x410f56 MOVSXD	0xc(%RAX),%R9    [1]

0x410f5a SAL	$0x4,%RDI

0x410f5e SAL	$0x4,%R14

0x410f62 VPERMT2PD	%YMM16,%YMM6,%YMM1

0x410f68 VFMADD132PD	%YMM2,%YMM4,%YMM2

0x410f6d VFMADD132PD	%YMM1,%YMM3,%YMM1

0x410f72 VMOVSD	(%RCX,%R14,1),%XMM4    [2]

0x410f78 VMOVSD	(%RCX,%RDI,1),%XMM3    [2]

0x410f7d SAL	$0x4,%RSI

0x410f81 SAL	$0x4,%R9

0x410f85 VMOVHPD	(%RCX,%RSI,1),%XMM3,%XMM15    [2]

0x410f8a VMOVHPD	(%RCX,%R9,1),%XMM4,%XMM14    [2]

0x410f90 VINSERTF64X2	$0x1,%XMM14,%YMM15,%YMM4

0x410f97 VDIVPD	%YMM4,%YMM5,%YMM14

0x410f9b MOVSXD	0x10(%RAX),%RDI    [1]

0x410f9f MOVSXD	0x18(%RAX),%R14    [1]

0x410fa3 MOVSXD	0x14(%RAX),%RSI    [1]

0x410fa7 MOVSXD	0x1c(%RAX),%R9    [1]

0x410fab SAL	$0x4,%RDI

0x410faf SAL	$0x4,%R14

0x410fb3 VMOVSD	(%RCX,%RDI,1),%XMM15    [2]

0x410fb8 SAL	$0x4,%RSI

0x410fbc SAL	$0x4,%R9

0x410fc0 VMOVHPD	(%RCX,%RSI,1),%XMM15,%XMM4    [2]

0x410fc5 ADD	$0x20,%RAX

0x410fc9 ADD	$0xc0,%RDX

0x410fd0 VFMADD231PD	%YMM2,%YMM14,%YMM0

0x410fd5 VMOVSD	(%RCX,%R14,1),%XMM2    [2]

0x410fdb VMOVHPD	(%RCX,%R9,1),%XMM2,%XMM3    [2]

0x410fe1 VINSERTF64X2	$0x1,%XMM3,%YMM4,%YMM14

0x410fe8 VDIVPD	%YMM14,%YMM5,%YMM2

0x410fed VFMADD231PD	%YMM1,%YMM2,%YMM0

0x410ff2 CMP	%RAX,%R11

0x410ff5 JNE	410ec0

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 115

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

Coverage (%)	Name	Source Location	Module
○98.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.00	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P5,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-115
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	16.00
Front-end cycles	11.00
P0 cycles	6.50
P1 cycles	6.00
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.00
P5 cycles	18.00
P6 cycles	6.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	7.33
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	62.00
Nb loads	22.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.56
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	24.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	81.40
Vectorization ratio load	42.86
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	41.86
Vector-efficiency ratio load	28.57
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.37

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P5,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-115
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	16.00
Front-end cycles	11.00
P0 cycles	6.50
P1 cycles	6.00
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.00
P5 cycles	18.00
P6 cycles	6.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	7.33
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	62.00
Nb loads	22.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.56
Nb FLOP add-sub	0.00
Nb FLOP mul	8.00
Nb FLOP fma	24.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	288.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	81.40
Vectorization ratio load	42.86
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	41.86
Vector-efficiency ratio load	28.57
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	47.37

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-115
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-115.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 41% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 24 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 6 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
32: multiply (24 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes (36 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	62
loop length	315
used x86 registers	8
used mmx registers	0
used xmm registers	5
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.50	6.00	7.33	7.33	0.00	18.00	6.50	0.00	0.00	0.00	1.00	7.33
cycles	6.50	6.00	7.33	7.33	0.00	18.00	6.50	0.00	0.00	0.00	1.00	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	11.00
Dispatch	18.00
DIV/SQRT	16.00
Data deps.	8.00
Overall L1	18.00

Vectorization ratios

all	81%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	41%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410ec0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD 0x20(%RDX),%YMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RDX),%YMM1	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM1,%YMM4	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM1,%YMM15	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPERMT2PD %YMM14,%YMM7,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM3,%YMM6,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMOVAPD %YMM1,%YMM2	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD 0x60(%RDX),%YMM1	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x80(%RDX),%YMM17	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xa0(%RDX),%YMM16	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPERMT2PD %YMM14,%YMM11,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM14,%YMM9,%YMM15	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMOVAPD %YMM1,%YMM14	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPERMT2PD %YMM17,%YMM9,%YMM14	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM3,%YMM8,%YMM15	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM16,%YMM8,%YMM14	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMULPD %YMM14,%YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM15,%YMM15	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VPERMT2PD %YMM3,%YMM10,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMOVAPD %YMM1,%YMM3	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPERMT2PD %YMM17,%YMM11,%YMM3	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM16,%YMM10,%YMM3	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VFMADD132PD %YMM4,%YMM15,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM3,%YMM14,%YMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOVSXD (%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VPERMT2PD %YMM17,%YMM7,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
MOVSXD 0x4(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0xc(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R14	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VPERMT2PD %YMM16,%YMM6,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VFMADD132PD %YMM2,%YMM4,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%RCX,%R14,1),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RCX,%RDI,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x4,%RSI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VMOVHPD (%RCX,%RSI,1),%XMM3,%XMM15	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
VMOVHPD (%RCX,%R9,1),%XMM4,%XMM14	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
VINSERTF64X2 $0x1,%XMM14,%YMM15,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VDIVPD %YMM4,%YMM5,%YMM14	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
MOVSXD 0x10(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x18(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x14(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x1c(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R14	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VMOVSD (%RCX,%RDI,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x4,%RSI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VMOVHPD (%RCX,%RSI,1),%XMM15,%XMM4	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
ADD $0x20,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0xc0,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VFMADD231PD %YMM2,%YMM14,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%RCX,%R14,1),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%RCX,%R9,1),%XMM2,%XMM3	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
VINSERTF64X2 $0x1,%XMM3,%YMM4,%YMM14	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VDIVPD %YMM14,%YMM5,%YMM2	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VFMADD231PD %YMM1,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 410ec0 <kineticEnergy._omp_fn.0+0x130>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-115
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-115.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 41% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 24 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 6 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 6 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
32: multiply (24 inside FMA instructions)
8: divide

The binary loop is loading 288 bytes (36 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	63
nb uops	62
loop length	315
used x86 registers	8
used mmx registers	0
used xmm registers	5
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.50	6.00	7.33	7.33	0.00	18.00	6.50	0.00	0.00	0.00	1.00	7.33
cycles	6.50	6.00	7.33	7.33	0.00	18.00	6.50	0.00	0.00	0.00	1.00	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	11.00
Dispatch	18.00
DIV/SQRT	16.00
Data deps.	8.00
Overall L1	18.00

Vectorization ratios

all	81%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	100%

Vector efficiency ratios

all	41%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	50%
other	47%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 410ec0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD 0x20(%RDX),%YMM14	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD (%RDX),%YMM1	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM3	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPD %YMM1,%YMM4	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVAPD %YMM1,%YMM15	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPERMT2PD %YMM14,%YMM7,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM3,%YMM6,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMOVAPD %YMM1,%YMM2	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VMOVUPD 0x60(%RDX),%YMM1	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x80(%RDX),%YMM17	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0xa0(%RDX),%YMM16	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPERMT2PD %YMM14,%YMM11,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM14,%YMM9,%YMM15	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMOVAPD %YMM1,%YMM14	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPERMT2PD %YMM17,%YMM9,%YMM14	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM3,%YMM8,%YMM15	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM16,%YMM8,%YMM14	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMULPD %YMM14,%YMM14,%YMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM15,%YMM15,%YMM15	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VPERMT2PD %YMM3,%YMM10,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VMOVAPD %YMM1,%YMM3	1	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
VPERMT2PD %YMM17,%YMM11,%YMM3	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPERMT2PD %YMM16,%YMM10,%YMM3	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VFMADD132PD %YMM4,%YMM15,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM3,%YMM14,%YMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOVSXD (%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VPERMT2PD %YMM17,%YMM7,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
MOVSXD 0x4(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0xc(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R14	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VPERMT2PD %YMM16,%YMM6,%YMM1	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VFMADD132PD %YMM2,%YMM4,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD132PD %YMM1,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%RCX,%R14,1),%XMM4	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RCX,%RDI,1),%XMM3	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x4,%RSI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VMOVHPD (%RCX,%RSI,1),%XMM3,%XMM15	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
VMOVHPD (%RCX,%R9,1),%XMM4,%XMM14	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
VINSERTF64X2 $0x1,%XMM14,%YMM15,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VDIVPD %YMM4,%YMM5,%YMM14	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
MOVSXD 0x10(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x18(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x14(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD 0x1c(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
SAL $0x4,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R14	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VMOVSD (%RCX,%RDI,1),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x4,%RSI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SAL $0x4,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
VMOVHPD (%RCX,%RSI,1),%XMM15,%XMM4	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
ADD $0x20,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0xc0,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VFMADD231PD %YMM2,%YMM14,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%RCX,%R14,1),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVHPD (%RCX,%R9,1),%XMM2,%XMM3	1	0	0	0.33	0.33	1	0	0	0.33	4-12	1	scal (12.5%)
VINSERTF64X2 $0x1,%XMM3,%YMM4,%YMM14	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VDIVPD %YMM14,%YMM5,%YMM2	1	1	0	0	0	0	0	0	0	13-15	8	vect (50.0%)
VFMADD231PD %YMM1,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 410ec0 <kineticEnergy._omp_fn.0+0x130>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code