OV - exec - Loop 105

	Loop Id: 105	Module: exec	Source: timestep.c:71-78	Coverage: 0.33%

0x410658 MOV	0x10(%RSP),%R8

0x41065d MOVSXD	(%R8,%RSI,4),%RCX

0x410661 TEST	%ECX,%ECX

0x410663 JLE	41096f

0x410669 MOV	0x20(%R15),%R10

0x41066d MOV	0x20(%R10),%R8

0x410671 MOV	0x28(%R10),%RBX

0x410675 LEA	(%R8,%R9,1),%R11

0x410679 LEA	(%RBX,%R9,1),%R12

0x41067d CMP	$0x1,%ECX

0x410680 JE	410998

0x410686 LEA	0x60(%R9),%R13

0x41068a LEA	(%RBX,%R9,1),%R12

0x41068e LEA	(%R8,%R13,1),%R14

0x410692 LEA	(%R8,%R9,1),%R11

0x410696 CMP	%R14,%R12

0x410699 JAE	4106a7

0x41069b ADD	%RBX,%R13

0x41069e CMP	%R13,%R11

0x4106a1 JB	410998

0x4106a7 MOV	%ESI,%R10D

0x4106aa LEA	-0x1(%RCX),%EAX

0x4106ad SAL	$0x6,%R10D

0x4106b1 MOV	%ECX,%EDX

0x4106b3 CMP	$0x2,%EAX

0x4106b6 JBE	410d34

0x4106bc MOV	%ECX,%R13D

0x4106bf SHR	$0x2,%R13D

0x4106c3 LEA	(%R13,%R13,2),%RDI

0x4106c8 SAL	$0x5,%RDI

0x4106cc LEA	(%R11,%RDI,1),%R13

0x4106d0 SUB	$0x60,%RDI

0x4106d4 SHR	$0x5,%RDI

0x4106d8 MOV	$0x2aaaaaaaaaaaaab,%R14

0x4106e2 IMUL	%R14,%RDI

0x4106e6 MOV	%R11,%RAX

0x4106e9 MOV	%R12,%RDX

0x4106ec INC	%RDI

0x4106ef AND	$0x3,%EDI

0x4106f2 JE	4107b7

0x4106f8 CMP	$0x1,%RDI

0x4106fc JE	410778

0x4106fe CMP	$0x2,%RDI

0x410702 JE	410742

0x410704 VMOVUPD	(%R12),%YMM5

0x41070a VMOVUPD	0x20(%R12),%YMM4

0x410711 VMOVUPD	0x40(%R12),%YMM2

0x410718 VFMADD213PD	(%R11),%YMM0,%YMM5

0x41071d VFMADD213PD	0x20(%R11),%YMM0,%YMM4

0x410723 VFMADD213PD	0x40(%R11),%YMM0,%YMM2

0x410729 ADD	$0x60,%RAX

0x41072d ADD	$0x60,%RDX

0x410731 VMOVUPD	%YMM5,(%R11)

0x410736 VMOVUPD	%YMM4,0x20(%R11)

0x41073c VMOVUPD	%YMM2,0x40(%R11)

0x410742 VMOVUPD	(%RDX),%YMM6

0x410746 VMOVUPD	0x20(%RDX),%YMM7

0x41074b VMOVUPD	0x40(%RDX),%YMM8

0x410750 VFMADD213PD	(%RAX),%YMM0,%YMM6

0x410755 VFMADD213PD	0x20(%RAX),%YMM0,%YMM7

0x41075b VFMADD213PD	0x40(%RAX),%YMM0,%YMM8

0x410761 ADD	$0x60,%RDX

0x410765 ADD	$0x60,%RAX

0x410769 VMOVUPD	%YMM6,-0x60(%RAX)

0x41076e VMOVUPD	%YMM7,-0x40(%RAX)

0x410773 VMOVUPD	%YMM8,-0x20(%RAX)

0x410778 VMOVUPD	(%RDX),%YMM9

0x41077c VMOVUPD	0x20(%RDX),%YMM10

0x410781 VMOVUPD	0x40(%RDX),%YMM11

0x410786 VFMADD213PD	(%RAX),%YMM0,%YMM9

0x41078b VFMADD213PD	0x20(%RAX),%YMM0,%YMM10

0x410791 VFMADD213PD	0x40(%RAX),%YMM0,%YMM11

0x410797 ADD	$0x60,%RAX

0x41079b ADD	$0x60,%RDX

0x41079f VMOVUPD	%YMM9,-0x60(%RAX)

0x4107a4 VMOVUPD	%YMM10,-0x40(%RAX)

0x4107a9 VMOVUPD	%YMM11,-0x20(%RAX)

0x4107ae CMP	%RAX,%R13

0x4107b1 JE	4108c1

  (107) 0x4107b7 VMOVUPD	(%RDX),%YMM12

  (107) 0x4107bb VMOVUPD	0x20(%RDX),%YMM7

  (107) 0x4107c0 VMOVUPD	0x40(%RDX),%YMM13

  (107) 0x4107c5 VFMADD213PD	0x20(%RAX),%YMM0,%YMM7

  (107) 0x4107cb VFMADD213PD	(%RAX),%YMM0,%YMM12

  (107) 0x4107d0 VFMADD213PD	0x40(%RAX),%YMM0,%YMM13

  (107) 0x4107d6 ADD	$0x180,%RAX

  (107) 0x4107dc ADD	$0x180,%RDX

  (107) 0x4107e3 VMOVUPD	%YMM7,-0x160(%RAX)

  (107) 0x4107eb VMOVUPD	%YMM12,-0x180(%RAX)

  (107) 0x4107f3 VMOVUPD	%YMM13,-0x140(%RAX)

  (107) 0x4107fb VMOVUPD	-0x120(%RDX),%YMM14

  (107) 0x410803 VMOVUPD	-0x100(%RDX),%YMM15

  (107) 0x41080b VMOVUPD	-0xe0(%RDX),%YMM5

  (107) 0x410813 VFMADD213PD	-0x120(%RAX),%YMM0,%YMM14

  (107) 0x41081c VFMADD213PD	-0x100(%RAX),%YMM0,%YMM15

  (107) 0x410825 VFMADD213PD	-0xe0(%RAX),%YMM0,%YMM5

  (107) 0x41082e VMOVUPD	%YMM14,-0x120(%RAX)

  (107) 0x410836 VMOVUPD	%YMM15,-0x100(%RAX)

  (107) 0x41083e VMOVUPD	%YMM5,-0xe0(%RAX)

  (107) 0x410846 VMOVUPD	-0xc0(%RDX),%YMM4

  (107) 0x41084e VMOVUPD	-0xa0(%RDX),%YMM6

  (107) 0x410856 VMOVUPD	-0x80(%RDX),%YMM2

  (107) 0x41085b VFMADD213PD	-0xc0(%RAX),%YMM0,%YMM4

  (107) 0x410864 VFMADD213PD	-0xa0(%RAX),%YMM0,%YMM6

  (107) 0x41086d VFMADD213PD	-0x80(%RAX),%YMM0,%YMM2

  (107) 0x410873 VMOVUPD	%YMM4,-0xc0(%RAX)

  (107) 0x41087b VMOVUPD	%YMM6,-0xa0(%RAX)

  (107) 0x410883 VMOVUPD	%YMM2,-0x80(%RAX)

  (107) 0x410888 VMOVUPD	-0x60(%RDX),%YMM8

  (107) 0x41088d VMOVUPD	-0x40(%RDX),%YMM7

  (107) 0x410892 VMOVUPD	-0x20(%RDX),%YMM9

  (107) 0x410897 VFMADD213PD	-0x60(%RAX),%YMM0,%YMM8

  (107) 0x41089d VFMADD213PD	-0x40(%RAX),%YMM0,%YMM7

  (107) 0x4108a3 VFMADD213PD	-0x20(%RAX),%YMM0,%YMM9

  (107) 0x4108a9 VMOVUPD	%YMM8,-0x60(%RAX)

  (107) 0x4108ae VMOVUPD	%YMM7,-0x40(%RAX)

  (107) 0x4108b3 VMOVUPD	%YMM9,-0x20(%RAX)

  (107) 0x4108b8 CMP	%RAX,%R13

  (107) 0x4108bb JNE	4107b7

0x4108c1 MOV	%ECX,%EDI

0x4108c3 AND	$-0x4,%EDI

0x4108c6 TEST	$0x3,%CL

0x4108c9 JE	41096f

0x4108cf SUB	%EDI,%ECX

0x4108d1 ADD	%EDI,%R10D

0x4108d4 MOV	%ECX,%EDX

0x4108d6 CMP	$0x1,%ECX

0x4108d9 JE	41092e

0x4108db LEA	(%RDI,%RDI,2),%RCX

0x4108df LEA	(%R9,%RCX,8),%R11

0x4108e3 LEA	(%R8,%R11,1),%R12

0x4108e7 ADD	%RBX,%R11

0x4108ea VMOVUPD	(%R11),%XMM10

0x4108ef VMOVUPD	0x10(%R11),%XMM11

0x4108f5 VMOVUPD	0x20(%R11),%XMM12

0x4108fb VFMADD213PD	(%R12),%XMM3,%XMM10

0x410901 VFMADD213PD	0x10(%R12),%XMM3,%XMM11

0x410908 VFMADD213PD	0x20(%R12),%XMM3,%XMM12

0x41090f VMOVUPD	%XMM10,(%R12)

0x410915 VMOVUPD	%XMM11,0x10(%R12)

0x41091c VMOVUPD	%XMM12,0x20(%R12)

0x410923 TEST	$0x1,%DL

0x410926 JE	41096f

0x410928 AND	$-0x2,%EDX

0x41092b ADD	%EDX,%R10D

0x41092e MOVSXD	%R10D,%R10

0x410931 LEA	(%R10,%R10,2),%RAX

0x410935 SAL	$0x3,%RAX

0x410939 ADD	%RAX,%R8

0x41093c ADD	%RBX,%RAX

0x41093f VMOVSD	(%RAX),%XMM13

0x410943 VFMADD213SD	(%R8),%XMM1,%XMM13

0x410948 VMOVSD	%XMM13,(%R8)

0x41094d VMOVSD	0x8(%RAX),%XMM14

0x410952 VFMADD213SD	0x8(%R8),%XMM1,%XMM14

0x410958 VMOVSD	%XMM14,0x8(%R8)

0x41095e VMOVSD	0x10(%RAX),%XMM15

0x410963 VFMADD213SD	0x10(%R8),%XMM1,%XMM15

0x410969 VMOVSD	%XMM15,0x10(%R8)

0x41096f INC	%RSI

0x410972 ADD	$0x600,%R9

0x410979 CMP	%ESI,0x1c(%RSP)

0x41097d JG	410658

0x410998 LEA	(%RCX,%RCX,2),%R8

0x41099c LEA	-0x18(,%R8,8),%R13

0x4109a4 SHR	$0x3,%R13

0x4109a8 MOV	$0xaaaaaaaaaaaaaab,%R14

0x4109b2 IMUL	%R14,%R13

0x4109b6 MOV	%R11,%RBX

0x4109b9 MOV	%R12,%RDX

0x4109bc INC	%R13

0x4109bf LEA	(%R11,%R8,8),%RDI

0x4109c3 AND	$0x7,%R13D

0x4109c7 JE	410b54

0x4109cd CMP	$0x1,%R13

0x4109d1 JE	410b14

0x4109d7 CMP	$0x2,%R13

0x4109db JE	410add

0x4109e1 CMP	$0x3,%R13

0x4109e5 JE	410aa6

0x4109eb CMP	$0x4,%R13

0x4109ef JE	410a6f

0x4109f1 CMP	$0x5,%R13

0x4109f5 JE	410a38

0x4109f7 CMP	$0x6,%R13

0x4109fb JNE	410d44

0x410a01 VMOVSD	(%RDX),%XMM2

0x410a05 ADD	$0x18,%RBX

0x410a09 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM2

0x410a0f ADD	$0x18,%RDX

0x410a13 VMOVSD	%XMM2,-0x18(%RBX)

0x410a18 VMOVSD	-0x10(%RDX),%XMM8

0x410a1d VFMADD213SD	-0x10(%RBX),%XMM1,%XMM8

0x410a23 VMOVSD	%XMM8,-0x10(%RBX)

0x410a28 VMOVSD	-0x8(%RDX),%XMM7

0x410a2d VFMADD213SD	-0x8(%RBX),%XMM1,%XMM7

0x410a33 VMOVSD	%XMM7,-0x8(%RBX)

0x410a38 VMOVSD	(%RDX),%XMM9

0x410a3c ADD	$0x18,%RBX

0x410a40 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM9

0x410a46 ADD	$0x18,%RDX

0x410a4a VMOVSD	%XMM9,-0x18(%RBX)

0x410a4f VMOVSD	-0x10(%RDX),%XMM10

0x410a54 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM10

0x410a5a VMOVSD	%XMM10,-0x10(%RBX)

0x410a5f VMOVSD	-0x8(%RDX),%XMM11

0x410a64 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM11

0x410a6a VMOVSD	%XMM11,-0x8(%RBX)

0x410a6f VMOVSD	(%RDX),%XMM12

0x410a73 ADD	$0x18,%RBX

0x410a77 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM12

0x410a7d ADD	$0x18,%RDX

0x410a81 VMOVSD	%XMM12,-0x18(%RBX)

0x410a86 VMOVSD	-0x10(%RDX),%XMM13

0x410a8b VFMADD213SD	-0x10(%RBX),%XMM1,%XMM13

0x410a91 VMOVSD	%XMM13,-0x10(%RBX)

0x410a96 VMOVSD	-0x8(%RDX),%XMM14

0x410a9b VFMADD213SD	-0x8(%RBX),%XMM1,%XMM14

0x410aa1 VMOVSD	%XMM14,-0x8(%RBX)

0x410aa6 VMOVSD	(%RDX),%XMM15

0x410aaa ADD	$0x18,%RBX

0x410aae VFMADD213SD	-0x18(%RBX),%XMM1,%XMM15

0x410ab4 ADD	$0x18,%RDX

0x410ab8 VMOVSD	%XMM15,-0x18(%RBX)

0x410abd VMOVSD	-0x10(%RDX),%XMM5

0x410ac2 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM5

0x410ac8 VMOVSD	%XMM5,-0x10(%RBX)

0x410acd VMOVSD	-0x8(%RDX),%XMM4

0x410ad2 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM4

0x410ad8 VMOVSD	%XMM4,-0x8(%RBX)

0x410add VMOVSD	(%RDX),%XMM6

0x410ae1 ADD	$0x18,%RBX

0x410ae5 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM6

0x410aeb ADD	$0x18,%RDX

0x410aef VMOVSD	%XMM6,-0x18(%RBX)

0x410af4 VMOVSD	-0x10(%RDX),%XMM2

0x410af9 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM2

0x410aff VMOVSD	%XMM2,-0x10(%RBX)

0x410b04 VMOVSD	-0x8(%RDX),%XMM8

0x410b09 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM8

0x410b0f VMOVSD	%XMM8,-0x8(%RBX)

0x410b14 VMOVSD	(%RDX),%XMM7

0x410b18 ADD	$0x18,%RBX

0x410b1c VFMADD213SD	-0x18(%RBX),%XMM1,%XMM7

0x410b22 ADD	$0x18,%RDX

0x410b26 VMOVSD	%XMM7,-0x18(%RBX)

0x410b2b VMOVSD	-0x10(%RDX),%XMM9

0x410b30 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM9

0x410b36 VMOVSD	%XMM9,-0x10(%RBX)

0x410b3b VMOVSD	-0x8(%RDX),%XMM10

0x410b40 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM10

0x410b46 VMOVSD	%XMM10,-0x8(%RBX)

0x410b4b CMP	%RDI,%RBX

0x410b4e JE	41096f

  (106) 0x410b54 VMOVSD	(%RDX),%XMM11

  (106) 0x410b58 ADD	$0xc0,%RBX

  (106) 0x410b5f VFMADD213SD	-0xc0(%RBX),%XMM1,%XMM11

  (106) 0x410b68 ADD	$0xc0,%RDX

  (106) 0x410b6f VMOVSD	%XMM11,-0xc0(%RBX)

  (106) 0x410b77 VMOVSD	-0xb8(%RDX),%XMM12

  (106) 0x410b7f VFMADD213SD	-0xb8(%RBX),%XMM1,%XMM12

  (106) 0x410b88 VMOVSD	%XMM12,-0xb8(%RBX)

  (106) 0x410b90 VMOVSD	-0xb0(%RDX),%XMM13

  (106) 0x410b98 VFMADD213SD	-0xb0(%RBX),%XMM1,%XMM13

  (106) 0x410ba1 VMOVSD	%XMM13,-0xb0(%RBX)

  (106) 0x410ba9 VMOVSD	-0xa8(%RDX),%XMM14

  (106) 0x410bb1 VFMADD213SD	-0xa8(%RBX),%XMM1,%XMM14

  (106) 0x410bba VMOVSD	%XMM14,-0xa8(%RBX)

  (106) 0x410bc2 VMOVSD	-0xa0(%RDX),%XMM15

  (106) 0x410bca VFMADD213SD	-0xa0(%RBX),%XMM1,%XMM15

  (106) 0x410bd3 VMOVSD	%XMM15,-0xa0(%RBX)

  (106) 0x410bdb VMOVSD	-0x98(%RDX),%XMM5

  (106) 0x410be3 VFMADD213SD	-0x98(%RBX),%XMM1,%XMM5

  (106) 0x410bec VMOVSD	%XMM5,-0x98(%RBX)

  (106) 0x410bf4 VMOVSD	-0x90(%RDX),%XMM4

  (106) 0x410bfc VFMADD213SD	-0x90(%RBX),%XMM1,%XMM4

  (106) 0x410c05 VMOVSD	%XMM4,-0x90(%RBX)

  (106) 0x410c0d VMOVSD	-0x88(%RDX),%XMM6

  (106) 0x410c15 VFMADD213SD	-0x88(%RBX),%XMM1,%XMM6

  (106) 0x410c1e VMOVSD	%XMM6,-0x88(%RBX)

  (106) 0x410c26 VMOVSD	-0x80(%RDX),%XMM2

  (106) 0x410c2b VFMADD213SD	-0x80(%RBX),%XMM1,%XMM2

  (106) 0x410c31 VMOVSD	%XMM2,-0x80(%RBX)

  (106) 0x410c36 VMOVSD	-0x78(%RDX),%XMM8

  (106) 0x410c3b VFMADD213SD	-0x78(%RBX),%XMM1,%XMM8

  (106) 0x410c41 VMOVSD	%XMM8,-0x78(%RBX)

  (106) 0x410c46 VMOVSD	-0x70(%RDX),%XMM7

  (106) 0x410c4b VFMADD213SD	-0x70(%RBX),%XMM1,%XMM7

  (106) 0x410c51 VMOVSD	%XMM7,-0x70(%RBX)

  (106) 0x410c56 VMOVSD	-0x68(%RDX),%XMM9

  (106) 0x410c5b VFMADD213SD	-0x68(%RBX),%XMM1,%XMM9

  (106) 0x410c61 VMOVSD	%XMM9,-0x68(%RBX)

  (106) 0x410c66 VMOVSD	-0x60(%RDX),%XMM10

  (106) 0x410c6b VFMADD213SD	-0x60(%RBX),%XMM1,%XMM10

  (106) 0x410c71 VMOVSD	%XMM10,-0x60(%RBX)

  (106) 0x410c76 VMOVSD	-0x58(%RDX),%XMM11

  (106) 0x410c7b VFMADD213SD	-0x58(%RBX),%XMM1,%XMM11

  (106) 0x410c81 VMOVSD	%XMM11,-0x58(%RBX)

  (106) 0x410c86 VMOVSD	-0x50(%RDX),%XMM12

  (106) 0x410c8b VFMADD213SD	-0x50(%RBX),%XMM1,%XMM12

  (106) 0x410c91 VMOVSD	%XMM12,-0x50(%RBX)

  (106) 0x410c96 VMOVSD	-0x48(%RDX),%XMM13

  (106) 0x410c9b VFMADD213SD	-0x48(%RBX),%XMM1,%XMM13

  (106) 0x410ca1 VMOVSD	%XMM13,-0x48(%RBX)

  (106) 0x410ca6 VMOVSD	-0x40(%RDX),%XMM14

  (106) 0x410cab VFMADD213SD	-0x40(%RBX),%XMM1,%XMM14

  (106) 0x410cb1 VMOVSD	%XMM14,-0x40(%RBX)

  (106) 0x410cb6 VMOVSD	-0x38(%RDX),%XMM15

  (106) 0x410cbb VFMADD213SD	-0x38(%RBX),%XMM1,%XMM15

  (106) 0x410cc1 VMOVSD	%XMM15,-0x38(%RBX)

  (106) 0x410cc6 VMOVSD	-0x30(%RDX),%XMM5

  (106) 0x410ccb VFMADD213SD	-0x30(%RBX),%XMM1,%XMM5

  (106) 0x410cd1 VMOVSD	%XMM5,-0x30(%RBX)

  (106) 0x410cd6 VMOVSD	-0x28(%RDX),%XMM4

  (106) 0x410cdb VFMADD213SD	-0x28(%RBX),%XMM1,%XMM4

  (106) 0x410ce1 VMOVSD	%XMM4,-0x28(%RBX)

  (106) 0x410ce6 VMOVSD	-0x20(%RDX),%XMM6

  (106) 0x410ceb VFMADD213SD	-0x20(%RBX),%XMM1,%XMM6

  (106) 0x410cf1 VMOVSD	%XMM6,-0x20(%RBX)

  (106) 0x410cf6 VMOVSD	-0x18(%RDX),%XMM2

  (106) 0x410cfb VFMADD213SD	-0x18(%RBX),%XMM1,%XMM2

  (106) 0x410d01 VMOVSD	%XMM2,-0x18(%RBX)

  (106) 0x410d06 VMOVSD	-0x10(%RDX),%XMM8

  (106) 0x410d0b VFMADD213SD	-0x10(%RBX),%XMM1,%XMM8

  (106) 0x410d11 VMOVSD	%XMM8,-0x10(%RBX)

  (106) 0x410d16 VMOVSD	-0x8(%RDX),%XMM7

  (106) 0x410d1b VFMADD213SD	-0x8(%RBX),%XMM1,%XMM7

  (106) 0x410d21 VMOVSD	%XMM7,-0x8(%RBX)

  (106) 0x410d26 CMP	%RDI,%RBX

  (106) 0x410d29 JNE	410b54

0x410d2f JMP	41096f

0x410d34 XOR	%EDI,%EDI

0x410d36 JMP	4108db

0x410d44 VMOVSD	(%R12),%XMM5

0x410d4a ADD	$0x18,%RBX

0x410d4e VFMADD213SD	(%R11),%XMM1,%XMM5

0x410d53 ADD	$0x18,%RDX

0x410d57 VMOVSD	%XMM5,(%R11)

0x410d5c VMOVSD	0x8(%R12),%XMM4

0x410d63 VFMADD213SD	0x8(%R11),%XMM1,%XMM4

0x410d69 VMOVSD	%XMM4,0x8(%R11)

0x410d6f VMOVSD	0x10(%R12),%XMM6

0x410d76 VFMADD213SD	0x10(%R11),%XMM1,%XMM6

0x410d7c VMOVSD	%XMM6,0x10(%R11)

0x410d82 JMP	410a01

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
○96.77	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○3.23	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	1.56
CQA speedup if fully vectorized	6.79
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	38.17
CQA cycles if no scalar integer	24.33
CQA cycles if FP arith vectorized	24.54
CQA cycles if fully vectorized	5.63
Front-end cycles	38.17
P0 cycles	24.50
P1 cycles	24.00
P2 cycles	26.00
P3 cycles	26.00
P4 cycles	18.00
P5 cycles	17.27
P6 cycles	17.10
P7 cycles	18.00
P8 cycles	18.00
P9 cycles	18.00
P10 cycles	17.13
P11 cycles	26.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	229.00
Nb uops	229.00
Nb loads	78.00
Nb stores	36.00
Nb stack references	2.00
FLOP/cycle	3.46
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	66.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.55
Bytes prefetched	0.00
Bytes loaded	1096.00
Bytes stored	528.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	28.35
Vectorization ratio load	32.88
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	33.33
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.11
Vector-efficiency ratio load	22.69
Vector-efficiency ratio store	22.92
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	22.92
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.86

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	1.56
CQA speedup if fully vectorized	6.79
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	micro-operation queue,
Function	advanceVelocity._omp_fn.0
Source	timestep.c:71-71,timestep.c:74-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	38.17
CQA cycles if no scalar integer	24.33
CQA cycles if FP arith vectorized	24.54
CQA cycles if fully vectorized	5.63
Front-end cycles	38.17
P0 cycles	24.50
P1 cycles	24.00
P2 cycles	26.00
P3 cycles	26.00
P4 cycles	18.00
P5 cycles	17.27
P6 cycles	17.10
P7 cycles	18.00
P8 cycles	18.00
P9 cycles	18.00
P10 cycles	17.13
P11 cycles	26.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	229.00
Nb uops	229.00
Nb loads	78.00
Nb stores	36.00
Nb stack references	2.00
FLOP/cycle	3.46
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	66.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.55
Bytes prefetched	0.00
Bytes loaded	1096.00
Bytes stored	528.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	28.35
Vectorization ratio load	32.88
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	33.33
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.11
Vector-efficiency ratio load	22.69
Vector-efficiency ratio store	22.92
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	22.92
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.86

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71,74-78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 91 paths individually, rerun with max-paths=91
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 91 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 38.17 to 24.33 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

32% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 66 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 18 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 18 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

24 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 9 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 132 FP arithmetical operations:

66: addition or subtraction (all inside FMA instructions)
66: multiply (all inside FMA instructions)

The binary loop is loading 1096 bytes (137 double precision FP elements). The binary loop is storing 528 bytes (66 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	229
nb uops	229
loop length	1068
used x86 registers	15
used mmx registers	0
used xmm registers	15
used ymm registers	10
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.17 cycles
front end	38.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	24.50	24.00	26.00	26.00	18.00	17.27	17.10	18.00	18.00	18.00	17.13	26.00
cycles	24.50	24.00	26.00	26.00	18.00	17.27	17.10	18.00	18.00	18.00	17.13	26.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.17
Dispatch	26.00
Overall L1	38.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	28%
load	32%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	22%
load	22%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	21%
load	22%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 38.17 cycles. At this rate:

14% of peak load performance is reached (28.72 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 38.17 to 26.00 cycles (1.47x speedup).

ASM code

In the binary file, the address of the loop is: 410658

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x10(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%R8,%RSI,4),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R15),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%R10),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R10),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R9,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R9,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 410998 <advanceVelocity._omp_fn.0+0x3b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x60(%R9),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R9,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R13,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R9,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R14,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4106a7 <advanceVelocity._omp_fn.0+0xc7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RBX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R13,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 410998 <advanceVelocity._omp_fn.0+0x3b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ESI,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RCX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SAL $0x6,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 410d34 <advanceVelocity._omp_fn.0+0x754>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R13D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R13,%R13,2),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R11,%RDI,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x60,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x2aaaaaaaaaaaaab,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
IMUL %R14,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4107b7 <advanceVelocity._omp_fn.0+0x1d7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410778 <advanceVelocity._omp_fn.0+0x198>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410742 <advanceVelocity._omp_fn.0+0x162>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R12),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R12),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R12),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%R11),%YMM0,%YMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%R11),%YMM0,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%R11),%YMM0,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x60,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM5,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM4,0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM2,0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%RDX),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%RAX),%YMM0,%YMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%RAX),%YMM0,%YMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%RAX),%YMM0,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM6,-0x60(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,-0x40(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM8,-0x20(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%RDX),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%RAX),%YMM0,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%RAX),%YMM0,%YMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%RAX),%YMM0,%YMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x60,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM9,-0x60(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM10,-0x40(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM11,-0x20(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4108c1 <advanceVelocity._omp_fn.0+0x2e1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST $0x3,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 41092e <advanceVelocity._omp_fn.0+0x34e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RDI,%RDI,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%RCX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R11,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RBX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R11),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x10(%R11),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x20(%R11),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VFMADD213PD (%R12),%XMM3,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%R12),%XMM3,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PD 0x20(%R12),%XMM3,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %XMM10,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM11,0x10(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM12,0x20(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R10D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R10,%R10,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RAX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD (%R8),%XMM1,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM13,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%R8),%XMM1,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM14,0x8(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x10(%R8),%XMM1,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x600,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %ESI,0x1c(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JG 410658 <advanceVelocity._omp_fn.0+0x78>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RCX,%RCX,2),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x18(,%R8,8),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xaaaaaaaaaaaaaab,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
IMUL %R14,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R8,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 410b54 <advanceVelocity._omp_fn.0+0x574>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410b14 <advanceVelocity._omp_fn.0+0x534>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410add <advanceVelocity._omp_fn.0+0x4fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410aa6 <advanceVelocity._omp_fn.0+0x4c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410a6f <advanceVelocity._omp_fn.0+0x48f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410a38 <advanceVelocity._omp_fn.0+0x458>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 410d44 <advanceVelocity._omp_fn.0+0x764>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM7,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM9,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM12,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM13,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM14,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM15,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4108db <advanceVelocity._omp_fn.0+0x2fb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%R12),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%R11),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%R11),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,0x8(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%R12),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x10(%R11),%XMM1,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM6,0x10(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 410a01 <advanceVelocity._omp_fn.0+0x421>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	advanceVelocity._omp_fn.0
Source file and lines	timestep.c:71-78
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 91 paths individually, rerun with max-paths=91
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

32% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 66 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 18 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 18 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 132 FP arithmetical operations:

66: addition or subtraction (all inside FMA instructions)
66: multiply (all inside FMA instructions)

The binary loop is loading 1096 bytes (137 double precision FP elements). The binary loop is storing 528 bytes (66 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	229
nb uops	229
loop length	1068
used x86 registers	15
used mmx registers	0
used xmm registers	15
used ymm registers	10
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.17 cycles
front end	38.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	24.50	24.00	26.00	26.00	18.00	17.27	17.10	18.00	18.00	18.00	17.13	26.00
cycles	24.50	24.00	26.00	26.00	18.00	17.27	17.10	18.00	18.00	18.00	17.13	26.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	38.17
Dispatch	26.00
Overall L1	38.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	28%
load	32%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	33%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	22%
load	22%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	21%
load	22%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	22%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 38.17 cycles. At this rate:

14% of peak load performance is reached (28.72 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 410658

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x10(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD (%R8,%RSI,4),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R15),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%R10),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%R10),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R8,%R9,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R9,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 410998 <advanceVelocity._omp_fn.0+0x3b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x60(%R9),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RBX,%R9,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R13,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R9,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R14,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4106a7 <advanceVelocity._omp_fn.0+0xc7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %RBX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R13,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 410998 <advanceVelocity._omp_fn.0+0x3b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ESI,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RCX),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SAL $0x6,%R10D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JBE 410d34 <advanceVelocity._omp_fn.0+0x754>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%R13D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R13,%R13,2),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
LEA (%R11,%RDI,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x60,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x5,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x2aaaaaaaaaaaaab,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
IMUL %R14,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4107b7 <advanceVelocity._omp_fn.0+0x1d7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410778 <advanceVelocity._omp_fn.0+0x198>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410742 <advanceVelocity._omp_fn.0+0x162>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPD (%R12),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%R12),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%R12),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%R11),%YMM0,%YMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%R11),%YMM0,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%R11),%YMM0,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x60,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM5,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM4,0x20(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM2,0x40(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%RDX),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%RAX),%YMM0,%YMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%RAX),%YMM0,%YMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%RAX),%YMM0,%YMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM6,-0x60(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM7,-0x40(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM8,-0x20(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD (%RDX),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x20(%RDX),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPD 0x40(%RDX),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PD (%RAX),%YMM0,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x20(%RAX),%YMM0,%YMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PD 0x40(%RAX),%YMM0,%YMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
ADD $0x60,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM9,-0x60(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM10,-0x40(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPD %YMM11,-0x20(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP %RAX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4108c1 <advanceVelocity._omp_fn.0+0x2e1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x4,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
TEST $0x3,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDI,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 41092e <advanceVelocity._omp_fn.0+0x34e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RDI,%RDI,2),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%RCX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R11,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RBX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPD (%R11),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x10(%R11),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPD 0x20(%R11),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VFMADD213PD (%R12),%XMM3,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PD 0x10(%R12),%XMM3,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VFMADD213PD 0x20(%R12),%XMM3,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (25.0%)
VMOVUPD %XMM10,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM11,0x10(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVUPD %XMM12,0x20(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
AND $-0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %EDX,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOVSXD %R10D,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R10,%R10,2),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RAX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RBX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%RAX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD (%R8),%XMM1,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM13,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%R8),%XMM1,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM14,0x8(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RAX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x10(%R8),%XMM1,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM15,0x10(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x600,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %ESI,0x1c(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JG 410658 <advanceVelocity._omp_fn.0+0x78>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%RCX,%RCX,2),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x18(,%R8,8),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xaaaaaaaaaaaaaab,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
IMUL %R14,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%R8,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 410b54 <advanceVelocity._omp_fn.0+0x574>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410b14 <advanceVelocity._omp_fn.0+0x534>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410add <advanceVelocity._omp_fn.0+0x4fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410aa6 <advanceVelocity._omp_fn.0+0x4c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410a6f <advanceVelocity._omp_fn.0+0x48f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410a38 <advanceVelocity._omp_fn.0+0x458>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 410d44 <advanceVelocity._omp_fn.0+0x764>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM7,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM9,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM11,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM12,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM13,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM14	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM14,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM15	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM15,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM2,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RDX),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD -0x18(%RBX),%XMM1,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x18(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x10(%RDX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x10(%RBX),%XMM1,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM9,-0x10(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x8(%RDX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD -0x8(%RBX),%XMM1,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x8(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 41096f <advanceVelocity._omp_fn.0+0x38f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4108db <advanceVelocity._omp_fn.0+0x2fb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%R12),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x18,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD (%R11),%XMM1,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x8(%R11),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,0x8(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%R12),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD213SD 0x10(%R11),%XMM1,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM6,0x10(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 410a01 <advanceVelocity._omp_fn.0+0x421>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code