OV - exec - Loop 103

	Loop Id: 103	Module: exec	Source: timestep.c:88-94	Coverage: 0.14%

0x410360 MOVSXD	(%R10),%R8

0x410363 TEST	%R8D,%R8D

0x410366 JLE	4105af

0x41036c MOV	0x20(%R11),%RDX

0x410370 ADD	%R9,%R8

0x410373 MOV	0x10(%RDX),%R12

0x410377 MOVSXD	%R9D,%RCX

0x41037a LEA	(%R12,%R8,4),%R8

0x41037e LEA	(%R12,%RCX,4),%RCX

0x410382 MOV	%R8,%R13

0x410385 SUB	%RCX,%R13

0x410388 SUB	$0x4,%R13

0x41038c MOV	0x18(%RDX),%RAX

0x410390 SHR	$0x2,%R13

0x410394 MOV	0x20(%RDX),%RDX

0x410398 INC	%R13

0x41039b MOV	0x28(%R11),%RSI

0x41039f ADD	%RDI,%RAX

0x4103a2 ADD	%RDI,%RDX

0x4103a5 AND	$0x3,%R13D

0x4103a9 JE	4104a2

0x4103af CMP	$0x1,%R13

0x4103b3 JE	410451

0x4103b9 CMP	$0x2,%R13

0x4103bd JE	410408

0x4103bf VMULSD	(%RDX),%XMM0,%XMM3

0x4103c3 MOVSXD	(%RCX),%R12

0x4103c6 ADD	$0x18,%RAX

0x4103ca SAL	$0x4,%R12

0x4103ce VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM1

0x4103d5 VFMADD213SD	-0x18(%RAX),%XMM1,%XMM3

0x4103db ADD	$0x4,%RCX

0x4103df ADD	$0x18,%RDX

0x4103e3 VMOVSD	%XMM3,-0x18(%RAX)

0x4103e8 VMULSD	-0x10(%RDX),%XMM0,%XMM4

0x4103ed VFMADD213SD	-0x10(%RAX),%XMM1,%XMM4

0x4103f3 VMOVSD	%XMM4,-0x10(%RAX)

0x4103f8 VMULSD	-0x8(%RDX),%XMM0,%XMM5

0x4103fd VFMADD213SD	-0x8(%RAX),%XMM5,%XMM1

0x410403 VMOVSD	%XMM1,-0x8(%RAX)

0x410408 VMULSD	(%RDX),%XMM0,%XMM7

0x41040c MOVSXD	(%RCX),%R13

0x41040f ADD	$0x18,%RAX

0x410413 SAL	$0x4,%R13

0x410417 VDIVSD	0x8(%RSI,%R13,1),%XMM2,%XMM6

0x41041e VFMADD213SD	-0x18(%RAX),%XMM6,%XMM7

0x410424 ADD	$0x4,%RCX

0x410428 ADD	$0x18,%RDX

0x41042c VMOVSD	%XMM7,-0x18(%RAX)

0x410431 VMULSD	-0x10(%RDX),%XMM0,%XMM8

0x410436 VFMADD213SD	-0x10(%RAX),%XMM6,%XMM8

0x41043c VMOVSD	%XMM8,-0x10(%RAX)

0x410441 VMULSD	-0x8(%RDX),%XMM0,%XMM9

0x410446 VFMADD213SD	-0x8(%RAX),%XMM9,%XMM6

0x41044c VMOVSD	%XMM6,-0x8(%RAX)

0x410451 VMULSD	(%RDX),%XMM0,%XMM11

0x410455 MOVSXD	(%RCX),%R12

0x410458 ADD	$0x4,%RCX

0x41045c SAL	$0x4,%R12

0x410460 VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM10

0x410467 VFMADD213SD	(%RAX),%XMM10,%XMM11

0x41046c ADD	$0x18,%RDX

0x410470 ADD	$0x18,%RAX

0x410474 VMOVSD	%XMM11,-0x18(%RAX)

0x410479 VMULSD	-0x10(%RDX),%XMM0,%XMM12

0x41047e VFMADD213SD	-0x10(%RAX),%XMM10,%XMM12

0x410484 VMOVSD	%XMM12,-0x10(%RAX)

0x410489 VMULSD	-0x8(%RDX),%XMM0,%XMM13

0x41048e VFMADD213SD	-0x8(%RAX),%XMM13,%XMM10

0x410494 VMOVSD	%XMM10,-0x8(%RAX)

0x410499 CMP	%RCX,%R8

0x41049c JE	4105af

  (104) 0x4104a2 VMULSD	(%RDX),%XMM0,%XMM15

  (104) 0x4104a6 MOVSXD	(%RCX),%R13

  (104) 0x4104a9 MOVSXD	0x4(%RCX),%R12

  (104) 0x4104ad SAL	$0x4,%R13

  (104) 0x4104b1 VDIVSD	0x8(%RSI,%R13,1),%XMM2,%XMM14

  (104) 0x4104b8 VFMADD213SD	(%RAX),%XMM14,%XMM15

  (104) 0x4104bd SAL	$0x4,%R12

  (104) 0x4104c1 MOVSXD	0x8(%RCX),%R13

  (104) 0x4104c5 ADD	$0x10,%RCX

  (104) 0x4104c9 SAL	$0x4,%R13

  (104) 0x4104cd VMOVSD	%XMM15,(%RAX)

  (104) 0x4104d1 VMULSD	0x8(%RDX),%XMM0,%XMM1

  (104) 0x4104d6 ADD	$0x60,%RAX

  (104) 0x4104da ADD	$0x60,%RDX

  (104) 0x4104de VFMADD213SD	-0x58(%RAX),%XMM14,%XMM1

  (104) 0x4104e4 VMOVSD	%XMM1,-0x58(%RAX)

  (104) 0x4104e9 VMULSD	-0x50(%RDX),%XMM0,%XMM3

  (104) 0x4104ee VFMADD213SD	-0x50(%RAX),%XMM3,%XMM14

  (104) 0x4104f4 VMOVSD	%XMM14,-0x50(%RAX)

  (104) 0x4104f9 VMULSD	-0x48(%RDX),%XMM0,%XMM5

  (104) 0x4104fe VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM4

  (104) 0x410505 VFMADD213SD	-0x48(%RAX),%XMM4,%XMM5

  (104) 0x41050b VMOVSD	%XMM5,-0x48(%RAX)

  (104) 0x410510 VMULSD	-0x40(%RDX),%XMM0,%XMM6

  (104) 0x410515 VFMADD213SD	-0x40(%RAX),%XMM4,%XMM6

  (104) 0x41051b VMOVSD	%XMM6,-0x40(%RAX)

  (104) 0x410520 VMULSD	-0x38(%RDX),%XMM0,%XMM7

  (104) 0x410525 VFMADD213SD	-0x38(%RAX),%XMM7,%XMM4

  (104) 0x41052b VMOVSD	%XMM4,-0x38(%RAX)

  (104) 0x410530 VMULSD	-0x30(%RDX),%XMM0,%XMM9

  (104) 0x410535 VDIVSD	0x8(%RSI,%R13,1),%XMM2,%XMM8

  (104) 0x41053c VFMADD213SD	-0x30(%RAX),%XMM8,%XMM9

  (104) 0x410542 VMOVSD	%XMM9,-0x30(%RAX)

  (104) 0x410547 VMULSD	-0x28(%RDX),%XMM0,%XMM10

  (104) 0x41054c VFMADD213SD	-0x28(%RAX),%XMM8,%XMM10

  (104) 0x410552 VMOVSD	%XMM10,-0x28(%RAX)

  (104) 0x410557 VMULSD	-0x20(%RDX),%XMM0,%XMM11

  (104) 0x41055c VFMADD213SD	-0x20(%RAX),%XMM11,%XMM8

  (104) 0x410562 VMOVSD	%XMM8,-0x20(%RAX)

  (104) 0x410567 VMULSD	-0x18(%RDX),%XMM0,%XMM13

  (104) 0x41056c MOVSXD	-0x4(%RCX),%R12

  (104) 0x410570 SAL	$0x4,%R12

  (104) 0x410574 VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM12

  (104) 0x41057b VFMADD213SD	-0x18(%RAX),%XMM12,%XMM13

  (104) 0x410581 VMOVSD	%XMM13,-0x18(%RAX)

  (104) 0x410586 VMULSD	-0x10(%RDX),%XMM0,%XMM14

  (104) 0x41058b VFMADD213SD	-0x10(%RAX),%XMM12,%XMM14

  (104) 0x410591 VMOVSD	%XMM14,-0x10(%RAX)

  (104) 0x410596 VMULSD	-0x8(%RDX),%XMM0,%XMM15

  (104) 0x41059b VFMADD213SD	-0x8(%RAX),%XMM15,%XMM12

  (104) 0x4105a1 VMOVSD	%XMM12,-0x8(%RAX)

  (104) 0x4105a6 CMP	%RCX,%R8

  (104) 0x4105a9 JNE	4104a2

0x4105af ADD	$0x600,%RDI

0x4105b6 ADD	$0x4,%R10

0x4105ba ADD	$0x40,%R9

0x4105be CMP	%RDI,%RBX

0x4105c1 JNE	410360

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94

--------------------------------------------------------------------------------

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

Coverage (%)	Name	Source Location	Module
○97.05	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.95	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	2.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	advancePosition._omp_fn.0
Source	timestep.c:88-94
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.17
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	7.38
CQA cycles if fully vectorized	6.00
Front-end cycles	13.17
P0 cycles	11.50
P1 cycles	11.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	4.50
P5 cycles	5.47
P6 cycles	8.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	5.53
P11 cycles	10.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	76.00
Nb loads	30.00
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	2.28
Nb FLOP add-sub	0.00
Nb FLOP mul	9.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.48
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.32
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	2.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	advancePosition._omp_fn.0
Source	timestep.c:88-94
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.17
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	7.38
CQA cycles if fully vectorized	6.00
Front-end cycles	13.17
P0 cycles	11.50
P1 cycles	11.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	4.50
P5 cycles	5.47
P6 cycles	8.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	5.53
P11 cycles	10.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	76.00
Nb loads	30.00
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	2.28
Nb FLOP add-sub	0.00
Nb FLOP mul	9.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.48
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.32
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advancePosition._omp_fn.0
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.17 to 12.00 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.17 to 6.00 cycles (2.19x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
18: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	76
loop length	346
used x86 registers	12
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	11.00	10.00	10.00	4.50	5.47	8.50	4.50	4.50	4.50	5.53	10.00
cycles	11.50	11.00	10.00	10.00	4.50	5.47	8.50	4.50	4.50	4.50	5.53	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.17
Dispatch	11.50
DIV/SQRT	12.00
Overall L1	13.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.17 cycles. At this rate:

8% of peak load performance is reached (17.01 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 410360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD (%R10),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4105af <advancePosition._omp_fn.0+0x2cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R11),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x10(%RDX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R9D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R12,%R8,4),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%RCX,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SHR $0x2,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV 0x20(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%R11),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4104a2 <advancePosition._omp_fn.0+0x1c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410451 <advancePosition._omp_fn.0+0x171>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410408 <advancePosition._omp_fn.0+0x128>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD (%RDX),%XMM0,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOVSXD (%RCX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VDIVSD 0x8(%RSI,%R12,1),%XMM2,%XMM1	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM1,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM5,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM1,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDX),%XMM0,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOVSXD (%RCX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VDIVSD 0x8(%RSI,%R13,1),%XMM2,%XMM6	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM9,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDX),%XMM0,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOVSXD (%RCX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VDIVSD 0x8(%RSI,%R12,1),%XMM2,%XMM10	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD213SD (%RAX),%XMM10,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM11,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM10,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM13,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4105af <advancePosition._omp_fn.0+0x2cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x600,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RDI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 410360 <advancePosition._omp_fn.0+0x80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	advancePosition._omp_fn.0
Source file and lines	timestep.c:88-94
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:88-94.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
18: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	76
loop length	346
used x86 registers	12
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.17 cycles
front end	13.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	11.00	10.00	10.00	4.50	5.47	8.50	4.50	4.50	4.50	5.53	10.00
cycles	11.50	11.00	10.00	10.00	4.50	5.47	8.50	4.50	4.50	4.50	5.53	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.17
Dispatch	11.50
DIV/SQRT	12.00
Overall L1	13.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.17 cycles. At this rate:

8% of peak load performance is reached (17.01 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.47 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 410360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD (%R10),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 4105af <advancePosition._omp_fn.0+0x2cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R11),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x10(%RDX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R9D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (%R12,%R8,4),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%RCX,4),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SHR $0x2,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV 0x20(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%R11),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x3,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4104a2 <advancePosition._omp_fn.0+0x1c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410451 <advancePosition._omp_fn.0+0x171>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 410408 <advancePosition._omp_fn.0+0x128>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD (%RDX),%XMM0,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOVSXD (%RCX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VDIVSD 0x8(%RSI,%R12,1),%XMM2,%XMM1	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM1,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM1,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM4,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM5,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM1,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDX),%XMM0,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOVSXD (%RCX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VDIVSD 0x8(%RSI,%R13,1),%XMM2,%XMM6	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD213SD -0x18(%RAX),%XMM6,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM8,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM9	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM9,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM6,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDX),%XMM0,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOVSXD (%RCX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VDIVSD 0x8(%RSI,%R12,1),%XMM2,%XMM10	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VFMADD213SD (%RAX),%XMM10,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x18,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM11,-0x18(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x10(%RDX),%XMM0,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x10(%RAX),%XMM10,%XMM12	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM12,-0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD -0x8(%RDX),%XMM0,%XMM13	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VFMADD213SD -0x8(%RAX),%XMM13,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD %XMM10,-0x8(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4105af <advancePosition._omp_fn.0+0x2cf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x600,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RDI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 410360 <advancePosition._omp_fn.0+0x80>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code