OV - exec - Function kineticEnergy._omp

	Function: kineticEnergy._omp_fn.0	Module: exec	Source: timestep.c:107-116	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

0x410d90 PUSH	%RBP

0x410d91 MOV	%RSP,%RBP

0x410d94 PUSH	%R15

0x410d96 PUSH	%R14

0x410d98 PUSH	%R13

0x410d9a PUSH	%R12

0x410d9c PUSH	%RBX

0x410d9d MOV	%RDI,%RBX

0x410da0 AND	$-0x20,%RSP

0x410da4 SUB	$0x40,%RSP

0x410da8 MOV	(%RDI),%RAX

0x410dab MOV	0x18(%RAX),%R13

0x410daf MOV	%RAX,0x20(%RSP)

0x410db4 CALL	403060 <omp_get_num_threads@plt>

0x410db9 MOV	%EAX,%R12D

0x410dbc CALL	403160 <omp_get_thread_num@plt>

0x410dc1 MOV	%EAX,%ECX

0x410dc3 MOV	0xc(%R13),%EAX

0x410dc7 CLTD

0x410dc8 IDIV	%R12D

0x410dcb CMP	%EDX,%ECX

0x410dcd JL	411272

0x410dd3 IMUL	%EAX,%ECX

0x410dd6 VXORPD	%XMM2,%XMM2,%XMM2

0x410dda ADD	%ECX,%EDX

0x410ddc LEA	(%RAX,%RDX,1),%ESI

0x410ddf CMP	%ESI,%EDX

0x410de1 JGE	411210

0x410de7 MOVSXD	%EDX,%R10

0x410dea MOV	0x78(%R13),%RDI

0x410dee MOV	%EAX,%R11D

0x410df1 ADD	%R10,%R11

0x410df4 LEA	(%RDI,%R11,4),%R14

0x410df8 VMOVSD	0x2d48(%RIP),%XMM13

0x410e00 LEA	(%R10,%R10,2),%R9

0x410e04 MOV	%R14,0x28(%RSP)

0x410e09 MOV	%RBX,0x18(%RSP)

0x410e0e MOV	%R10,%R12

0x410e11 SAL	$0x9,%R9

0x410e15 VMOVDQA	0x1fe3(%RIP),%YMM11

0x410e1d VMOVDQA	0x1ffb(%RIP),%YMM10

0x410e25 VMOVDQA	0x2013(%RIP),%YMM9

0x410e2d VMOVDQA	0x202b(%RIP),%YMM8

0x410e35 VMOVDQA	0x2043(%RIP),%YMM7

0x410e3d VMOVDQA	0x205b(%RIP),%YMM6

0x410e45 LEA	(%RDI,%R10,4),%R8

0x410e49 SAL	$0x6,%R12

0x410e4d VMOVDDUP	%XMM13,%XMM12

0x410e52 VBROADCASTSD	%XMM13,%YMM5

0x410e57 VMOVAPD	%XMM2,%XMM18

0x410e5d MOV	%R9,%R10

(109) 0x410e60 MOV	(%R8),%R13D

(109) 0x410e63 MOV	%R12D,%EBX

(109) 0x410e66 TEST	%R13D,%R13D

(109) 0x410e69 JLE	4111e8

(109) 0x410e6f MOV	0x20(%RSP),%R15

(109) 0x410e74 LEA	-0x1(%R13),%EAX

(109) 0x410e78 MOV	0x20(%R15),%RCX

(109) 0x410e7c MOV	0x28(%R15),%R9

(109) 0x410e80 MOV	0x10(%RCX),%R14

(109) 0x410e84 MOV	0x20(%RCX),%R15

(109) 0x410e88 CMP	$0x6,%EAX

(109) 0x410e8b JBE	411248

(109) 0x410e91 MOV	%R13D,%R11D

(109) 0x410e94 SHR	$0x3,%R11D

(109) 0x410e98 MOV	%R14,0x38(%RSP)

(109) 0x410e9d MOV	%R9,0x30(%RSP)

(109) 0x410ea2 LEA	(%R14,%R12,4),%RAX

(109) 0x410ea6 SAL	$0x5,%R11

(109) 0x410eaa LEA	0x8(%R9),%RCX

(109) 0x410eae LEA	(%R15,%R10,1),%RDX

(109) 0x410eb2 ADD	%RAX,%R11

(109) 0x410eb5 VXORPD	%XMM0,%XMM0,%XMM0

(109) 0x410eb9 NOPL	(%RAX)

  (110) 0x410ec0 VMOVUPD	0x20(%RDX),%YMM14

  (110) 0x410ec5 VMOVUPD	(%RDX),%YMM1

  (110) 0x410ec9 VMOVUPD	0x40(%RDX),%YMM3

  (110) 0x410ece VMOVAPD	%YMM1,%YMM4

  (110) 0x410ed2 VMOVAPD	%YMM1,%YMM15

  (110) 0x410ed6 VPERMT2PD	%YMM14,%YMM7,%YMM1

  (110) 0x410edc VPERMT2PD	%YMM3,%YMM6,%YMM1

  (110) 0x410ee2 VMOVAPD	%YMM1,%YMM2

  (110) 0x410ee6 VMOVUPD	0x60(%RDX),%YMM1

  (110) 0x410eeb VMOVUPD	0x80(%RDX),%YMM17

  (110) 0x410ef2 VMOVUPD	0xa0(%RDX),%YMM16

  (110) 0x410ef9 VPERMT2PD	%YMM14,%YMM11,%YMM4

  (110) 0x410eff VPERMT2PD	%YMM14,%YMM9,%YMM15

  (110) 0x410f05 VMOVAPD	%YMM1,%YMM14

  (110) 0x410f09 VPERMT2PD	%YMM17,%YMM9,%YMM14

  (110) 0x410f0f VPERMT2PD	%YMM3,%YMM8,%YMM15

  (110) 0x410f15 VPERMT2PD	%YMM16,%YMM8,%YMM14

  (110) 0x410f1b VMULPD	%YMM14,%YMM14,%YMM14

  (110) 0x410f20 VMULPD	%YMM15,%YMM15,%YMM15

  (110) 0x410f25 VPERMT2PD	%YMM3,%YMM10,%YMM4

  (110) 0x410f2b VMOVAPD	%YMM1,%YMM3

  (110) 0x410f2f VPERMT2PD	%YMM17,%YMM11,%YMM3

  (110) 0x410f35 VPERMT2PD	%YMM16,%YMM10,%YMM3

  (110) 0x410f3b VFMADD132PD	%YMM4,%YMM15,%YMM4

  (110) 0x410f40 VFMADD132PD	%YMM3,%YMM14,%YMM3

  (110) 0x410f45 MOVSXD	(%RAX),%RDI

  (110) 0x410f48 MOVSXD	0x8(%RAX),%R14

  (110) 0x410f4c VPERMT2PD	%YMM17,%YMM7,%YMM1

  (110) 0x410f52 MOVSXD	0x4(%RAX),%RSI

  (110) 0x410f56 MOVSXD	0xc(%RAX),%R9

  (110) 0x410f5a SAL	$0x4,%RDI

  (110) 0x410f5e SAL	$0x4,%R14

  (110) 0x410f62 VPERMT2PD	%YMM16,%YMM6,%YMM1

  (110) 0x410f68 VFMADD132PD	%YMM2,%YMM4,%YMM2

  (110) 0x410f6d VFMADD132PD	%YMM1,%YMM3,%YMM1

  (110) 0x410f72 VMOVSD	(%RCX,%R14,1),%XMM4

  (110) 0x410f78 VMOVSD	(%RCX,%RDI,1),%XMM3

  (110) 0x410f7d SAL	$0x4,%RSI

  (110) 0x410f81 SAL	$0x4,%R9

  (110) 0x410f85 VMOVHPD	(%RCX,%RSI,1),%XMM3,%XMM15

  (110) 0x410f8a VMOVHPD	(%RCX,%R9,1),%XMM4,%XMM14

  (110) 0x410f90 VINSERTF64X2	$0x1,%XMM14,%YMM15,%YMM4

  (110) 0x410f97 VDIVPD	%YMM4,%YMM5,%YMM14

  (110) 0x410f9b MOVSXD	0x10(%RAX),%RDI

  (110) 0x410f9f MOVSXD	0x18(%RAX),%R14

  (110) 0x410fa3 MOVSXD	0x14(%RAX),%RSI

  (110) 0x410fa7 MOVSXD	0x1c(%RAX),%R9

  (110) 0x410fab SAL	$0x4,%RDI

  (110) 0x410faf SAL	$0x4,%R14

  (110) 0x410fb3 VMOVSD	(%RCX,%RDI,1),%XMM15

  (110) 0x410fb8 SAL	$0x4,%RSI

  (110) 0x410fbc SAL	$0x4,%R9

  (110) 0x410fc0 VMOVHPD	(%RCX,%RSI,1),%XMM15,%XMM4

  (110) 0x410fc5 ADD	$0x20,%RAX

  (110) 0x410fc9 ADD	$0xc0,%RDX

  (110) 0x410fd0 VFMADD231PD	%YMM2,%YMM14,%YMM0

  (110) 0x410fd5 VMOVSD	(%RCX,%R14,1),%XMM2

  (110) 0x410fdb VMOVHPD	(%RCX,%R9,1),%XMM2,%XMM3

  (110) 0x410fe1 VINSERTF64X2	$0x1,%XMM3,%YMM4,%YMM14

  (110) 0x410fe8 VDIVPD	%YMM14,%YMM5,%YMM2

  (110) 0x410fed VFMADD231PD	%YMM1,%YMM2,%YMM0

  (110) 0x410ff2 CMP	%RAX,%R11

  (110) 0x410ff5 JNE	410ec0

(109) 0x410ffb VEXTRACTF64X2	$0x1,%YMM0,%XMM1

(109) 0x411002 VADDPD	%XMM0,%XMM1,%XMM0

(109) 0x411006 MOV	%R13D,%EAX

(109) 0x411009 AND	$-0x8,%EAX

(109) 0x41100c VUNPCKHPD	%XMM0,%XMM0,%XMM3

(109) 0x411010 VADDPD	%XMM0,%XMM3,%XMM15

(109) 0x411014 MOV	0x38(%RSP),%R14

(109) 0x411019 MOV	0x30(%RSP),%R9

(109) 0x41101e VADDSD	%XMM15,%XMM18,%XMM2

(109) 0x411024 MOV	%EAX,%EDI

(109) 0x411026 ADD	%EAX,%EBX

(109) 0x411028 CMP	%R13D,%EAX

(109) 0x41102b JE	411240

(109) 0x411031 MOV	%R13D,%ESI

(109) 0x411034 SUB	%EDI,%ESI

(109) 0x411036 LEA	-0x1(%RSI),%ECX

(109) 0x411039 CMP	$0x2,%ECX

(109) 0x41103c JBE	411267

(109) 0x411042 LEA	(%RDI,%RDI,2),%R11

(109) 0x411046 LEA	(%RDI,%R12,1),%RDX

(109) 0x41104a LEA	(%R10,%R11,8),%RDI

(109) 0x41104e ADD	%R15,%RDI

(109) 0x411051 VMOVUPD	(%RDI),%XMM4

(109) 0x411055 VMOVUPD	0x20(%RDI),%XMM14

(109) 0x41105a VMOVHPS	0xc(%RDI),%XMM4,%XMM19

(109) 0x411061 VMOVUPD	0x30(%RDI),%XMM2

(109) 0x411066 VMOVUPD	0x40(%RDI),%XMM20

(109) 0x41106d VMOVLPD	0x10(%RDI),%XMM14,%XMM3

(109) 0x411072 VSHUFPD	$0x1,%XMM14,%XMM4,%XMM1

(109) 0x411078 VMOVUPD	0x50(%RDI),%XMM4

(109) 0x41107d VMULPD	%XMM3,%XMM3,%XMM14

(109) 0x411081 VMOVSD	%XMM2,%XMM20,%XMM15

(109) 0x411087 VSHUFPD	$0x1,%XMM4,%XMM2,%XMM2

(109) 0x41108c VMOVSD	%XMM20,%XMM4,%XMM4

(109) 0x411092 VMULPD	%XMM4,%XMM4,%XMM3

(109) 0x411096 VFMADD132PD	%XMM1,%XMM14,%XMM1

(109) 0x41109b LEA	(%R14,%RDX,4),%RCX

(109) 0x41109f MOVSXD	(%RCX),%RDX

(109) 0x4110a2 MOVSXD	0x4(%RCX),%R11

(109) 0x4110a6 VFMADD132PD	%XMM2,%XMM3,%XMM2

(109) 0x4110ab SAL	$0x4,%RDX

(109) 0x4110af VFMADD132PD	%XMM19,%XMM1,%XMM19

(109) 0x4110b5 VMOVSD	0x8(%R9,%RDX,1),%XMM1

(109) 0x4110bc SAL	$0x4,%R11

(109) 0x4110c0 VFMADD132PD	%XMM15,%XMM2,%XMM15

(109) 0x4110c5 VMOVHPD	0x8(%R9,%R11,1),%XMM1,%XMM2

(109) 0x4110cc VDIVPD	%XMM2,%XMM12,%XMM4

(109) 0x4110d0 MOVSXD	0x8(%RCX),%RDI

(109) 0x4110d4 MOVSXD	0xc(%RCX),%RCX

(109) 0x4110d8 SAL	$0x4,%RDI

(109) 0x4110dc SAL	$0x4,%RCX

(109) 0x4110e0 MOV	%ESI,%EDX

(109) 0x4110e2 AND	$-0x4,%EDX

(109) 0x4110e5 ADD	%EDX,%EAX

(109) 0x4110e7 ADD	%EDX,%EBX

(109) 0x4110e9 AND	$0x3,%ESI

(109) 0x4110ec VFMADD132PD	%XMM19,%XMM0,%XMM4

(109) 0x4110f2 VMOVSD	0x8(%R9,%RDI,1),%XMM0

(109) 0x4110f9 VMOVHPD	0x8(%R9,%RCX,1),%XMM0,%XMM14

(109) 0x411100 VDIVPD	%XMM14,%XMM12,%XMM3

(109) 0x411105 VFMADD132PD	%XMM15,%XMM4,%XMM3

(109) 0x41110a VUNPCKHPD	%XMM3,%XMM3,%XMM15

(109) 0x41110e VADDPD	%XMM3,%XMM15,%XMM1

(109) 0x411112 VADDSD	%XMM1,%XMM18,%XMM18

(109) 0x411118 JE	4111e8

(109) 0x41111e MOVSXD	%EBX,%RBX

(109) 0x411121 LEA	(%RBX,%RBX,2),%R11

(109) 0x411125 SAL	$0x3,%R11

(109) 0x411129 LEA	(%R15,%R11,1),%RDI

(109) 0x41112d VMOVSD	0x8(%RDI),%XMM2

(109) 0x411132 VMOVSD	(%RDI),%XMM4

(109) 0x411136 VMULSD	%XMM2,%XMM2,%XMM0

(109) 0x41113a VMOVSD	0x10(%RDI),%XMM14

(109) 0x41113f MOVSXD	(%R14,%RBX,4),%RCX

(109) 0x411143 LEA	0x1(%RAX),%EDX

(109) 0x411146 SAL	$0x4,%RCX

(109) 0x41114a VFMADD132SD	%XMM4,%XMM0,%XMM4

(109) 0x41114f VDIVSD	0x8(%R9,%RCX,1),%XMM13,%XMM3

(109) 0x411156 LEA	(,%RBX,4),%RSI

(109) 0x41115e VFMADD132SD	%XMM14,%XMM4,%XMM14

(109) 0x411163 VFMADD231SD	%XMM14,%XMM3,%XMM18

(109) 0x411169 CMP	%R13D,%EDX

(109) 0x41116c JGE	4111e8

(109) 0x41116e LEA	0x18(%R15,%R11,1),%RBX

(109) 0x411173 VMOVSD	0x8(%RBX),%XMM1

(109) 0x411178 VMOVSD	(%RBX),%XMM15

(109) 0x41117c VMULSD	%XMM1,%XMM1,%XMM4

(109) 0x411180 VMOVSD	0x10(%RBX),%XMM2

(109) 0x411185 MOVSXD	0x4(%R14,%RSI,1),%RDI

(109) 0x41118a ADD	$0x2,%EAX

(109) 0x41118d SAL	$0x4,%RDI

(109) 0x411191 VFMADD132SD	%XMM15,%XMM4,%XMM15

(109) 0x411196 VDIVSD	0x8(%R9,%RDI,1),%XMM13,%XMM0

(109) 0x41119d VFMADD132SD	%XMM2,%XMM15,%XMM2

(109) 0x4111a2 VFMADD231SD	%XMM0,%XMM2,%XMM18

(109) 0x4111a8 CMP	%EAX,%R13D

(109) 0x4111ab JLE	4111e8

(109) 0x4111ad LEA	0x30(%R15,%R11,1),%R13

(109) 0x4111b2 VMOVSD	0x8(%R13),%XMM3

(109) 0x4111b8 VMOVSD	(%R13),%XMM14

(109) 0x4111be VMULSD	%XMM3,%XMM3,%XMM15

(109) 0x4111c2 VMOVSD	0x10(%R13),%XMM1

(109) 0x4111c8 MOVSXD	0x8(%R14,%RSI,1),%R15

(109) 0x4111cd SAL	$0x4,%R15

(109) 0x4111d1 VFMADD132SD	%XMM14,%XMM15,%XMM14

(109) 0x4111d6 VDIVSD	0x8(%R9,%R15,1),%XMM13,%XMM4

(109) 0x4111dd VFMADD132SD	%XMM1,%XMM14,%XMM1

(109) 0x4111e2 VFMADD231SD	%XMM1,%XMM4,%XMM18

(109) 0x4111e8 ADD	$0x4,%R8

(109) 0x4111ec ADD	$0x600,%R10

(109) 0x4111f3 ADD	$0x40,%R12

(109) 0x4111f7 CMP	%R8,0x28(%RSP)

(109) 0x4111fc JNE	410e60

0x411202 MOV	0x18(%RSP),%RBX

0x411207 VMOVAPD	%XMM18,%XMM2

0x41120d VZEROUPPER

0x411210 MOV	0x8(%RBX),%RAX

0x411214 LEA	0x8(%RBX),%R9

(108) 0x411218 VMOVQ	%RAX,%XMM5

(108) 0x41121d VADDSD	%XMM5,%XMM2,%XMM6

(108) 0x411221 VMOVQ	%XMM6,%R14

(108) 0x411226 LOCK CMPXCHG	%R14,(%R9)

(108) 0x41122b JNE	411218

0x41122d LEA	-0x28(%RBP),%RSP

0x411231 POP	%RBX

0x411232 POP	%R12

0x411234 POP	%R13

0x411236 POP	%R14

0x411238 POP	%R15

0x41123a POP	%RBP

0x41123b RET

0x41123c NOPL	(%RAX)

(109) 0x411240 VMOVAPD	%XMM2,%XMM18

(109) 0x411246 JMP	4111e8

(109) 0x411248 XOR	%EDI,%EDI

(109) 0x41124a MOV	%R13D,%ESI

(109) 0x41124d SUB	%EDI,%ESI

(109) 0x41124f LEA	-0x1(%RSI),%ECX

(109) 0x411252 VMOVAPD	%XMM18,%XMM2

(109) 0x411258 VXORPD	%XMM0,%XMM0,%XMM0

(109) 0x41125c XOR	%EAX,%EAX

(109) 0x41125e CMP	$0x2,%ECX

(109) 0x411261 JA	411042

(109) 0x411267 VMOVAPD	%XMM2,%XMM18

(109) 0x41126d JMP	41111e

0x411272 INC	%EAX

0x411274 XOR	%EDX,%EDX

0x411276 JMP	410dd3

0x41127b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.39	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.61	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 3.17 cycles (3.95x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 244 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	69
nb uops	75
loop length	263
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	6.67	6.67	5.50	4.00	4.00	5.50	5.50	5.50	4.00	6.67
cycles	4.00	5.73	6.67	6.67	5.50	4.00	4.00	5.50	5.50	5.50	4.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	12.50
Dispatch	6.67
DIV/SQRT	6.00
Overall L1	12.50

Vectorization ratios

INT

all	35%
load	100%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

INT+FP

all	38%
load	85%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	28%

Vector efficiency ratios

INT

all	22%
load	50%
store	12%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	21%
load	44%
store	12%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

10% of peak load performance is reached (19.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.50 to 6.67 cycles (1.88x speedup).

ASM code

In the binary file, the address of the function is: 410d90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xc(%R13),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 411272 <kineticEnergy._omp_fn.0+0x4e2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 411210 <kineticEnergy._omp_fn.0+0x480>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EDX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x78(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R10,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R11,4),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x2d48(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R10,%R10,2),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x9,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVDQA 0x1fe3(%RIP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x1ffb(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x2013(%RIP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x202b(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x2043(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x205b(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
LEA (%RDI,%R10,4),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVDDUP %XMM13,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBROADCASTSD %XMM13,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM2,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPD %XMM18,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV 0x8(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(%RBX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 410dd3 <kineticEnergy._omp_fn.0+0x43>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 3.17 cycles (3.95x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:108

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 244 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	69
nb uops	75
loop length	263
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	6.67	6.67	5.50	4.00	4.00	5.50	5.50	5.50	4.00	6.67
cycles	4.00	5.73	6.67	6.67	5.50	4.00	4.00	5.50	5.50	5.50	4.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	12.50
Dispatch	6.67
DIV/SQRT	6.00
Overall L1	12.50

Vectorization ratios

INT

all	35%
load	100%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

INT+FP

all	38%
load	85%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	28%

Vector efficiency ratios

INT

all	22%
load	50%
store	12%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	21%
load	44%
store	12%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.50 cycles. At this rate:

10% of peak load performance is reached (19.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 410d90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x40,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xc(%R13),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 411272 <kineticEnergy._omp_fn.0+0x4e2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 411210 <kineticEnergy._omp_fn.0+0x480>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EDX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x78(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R10,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R11,4),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x2d48(%RIP),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R10,%R10,2),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x9,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVDQA 0x1fe3(%RIP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x1ffb(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x2013(%RIP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x202b(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x2043(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQA 0x205b(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
LEA (%RDI,%R10,4),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVDDUP %XMM13,%XMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBROADCASTSD %XMM13,%YMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM2,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPD %XMM18,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV 0x8(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x8(%RBX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 410dd3 <kineticEnergy._omp_fn.0+0x43>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼kineticEnergy._omp_fn.0–	0.03	0.00
▼Loop 109 - timestep.c:110-116 - exec–	0.00	0.00
○Loop 110 - timestep.c:110-115 - exec	0.03	0.01
○Loop 108 - timestep.c:107-107 - exec	0.00	0.00

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512-bits vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code