OV - exec - Function advanceVelocity._omp

	Function: advanceVelocity._omp_fn.0	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 0.65% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x4105e0 PUSH	%RBP

0x4105e1 MOV	%RSP,%RBP

0x4105e4 PUSH	%R15

0x4105e6 PUSH	%R14

0x4105e8 PUSH	%R13

0x4105ea PUSH	%R12

0x4105ec PUSH	%RBX

0x4105ed MOV	%RDI,%RBX

0x4105f0 AND	$-0x20,%RSP

0x4105f4 SUB	$0x20,%RSP

0x4105f8 CALL	403060 <omp_get_num_threads@plt>

0x4105fd MOV	%EAX,%R12D

0x410600 CALL	403160 <omp_get_thread_num@plt>

0x410605 MOV	%EAX,%ESI

0x410607 MOV	0x10(%RBX),%EAX

0x41060a CLTD

0x41060b IDIV	%R12D

0x41060e CMP	%EDX,%ESI

0x410610 JL	410d3b

0x410616 IMUL	%EAX,%ESI

0x410619 ADD	%EDX,%ESI

0x41061b ADD	%ESI,%EAX

0x41061d MOV	%EAX,0x1c(%RSP)

0x410621 CMP	%EAX,%ESI

0x410623 JGE	410986

0x410629 MOV	(%RBX),%R15

0x41062c VMOVSD	0x8(%RBX),%XMM1

0x410631 MOV	0x18(%R15),%RCX

0x410635 MOVSXD	%ESI,%RSI

0x410638 MOV	0x78(%RCX),%RDI

0x41063c LEA	(%RSI,%RSI,2),%R9

0x410640 MOV	%RDI,0x10(%RSP)

0x410645 SAL	$0x9,%R9

0x410649 VMOVDDUP	%XMM1,%XMM3

0x41064d VBROADCASTSD	%XMM1,%YMM0

0x410652 NOPW	(%RAX,%RAX,1)

(105) 0x410658 MOV	0x10(%RSP),%R8

(105) 0x41065d MOVSXD	(%R8,%RSI,4),%RCX

(105) 0x410661 TEST	%ECX,%ECX

(105) 0x410663 JLE	41096f

(105) 0x410669 MOV	0x20(%R15),%R10

(105) 0x41066d MOV	0x20(%R10),%R8

(105) 0x410671 MOV	0x28(%R10),%RBX

(105) 0x410675 LEA	(%R8,%R9,1),%R11

(105) 0x410679 LEA	(%RBX,%R9,1),%R12

(105) 0x41067d CMP	$0x1,%ECX

(105) 0x410680 JE	410998

(105) 0x410686 LEA	0x60(%R9),%R13

(105) 0x41068a LEA	(%RBX,%R9,1),%R12

(105) 0x41068e LEA	(%R8,%R13,1),%R14

(105) 0x410692 LEA	(%R8,%R9,1),%R11

(105) 0x410696 CMP	%R14,%R12

(105) 0x410699 JAE	4106a7

(105) 0x41069b ADD	%RBX,%R13

(105) 0x41069e CMP	%R13,%R11

(105) 0x4106a1 JB	410998

(105) 0x4106a7 MOV	%ESI,%R10D

(105) 0x4106aa LEA	-0x1(%RCX),%EAX

(105) 0x4106ad SAL	$0x6,%R10D

(105) 0x4106b1 MOV	%ECX,%EDX

(105) 0x4106b3 CMP	$0x2,%EAX

(105) 0x4106b6 JBE	410d34

(105) 0x4106bc MOV	%ECX,%R13D

(105) 0x4106bf SHR	$0x2,%R13D

(105) 0x4106c3 LEA	(%R13,%R13,2),%RDI

(105) 0x4106c8 SAL	$0x5,%RDI

(105) 0x4106cc LEA	(%R11,%RDI,1),%R13

(105) 0x4106d0 SUB	$0x60,%RDI

(105) 0x4106d4 SHR	$0x5,%RDI

(105) 0x4106d8 MOV	$0x2aaaaaaaaaaaaab,%R14

(105) 0x4106e2 IMUL	%R14,%RDI

(105) 0x4106e6 MOV	%R11,%RAX

(105) 0x4106e9 MOV	%R12,%RDX

(105) 0x4106ec INC	%RDI

(105) 0x4106ef AND	$0x3,%EDI

(105) 0x4106f2 JE	4107b7

(105) 0x4106f8 CMP	$0x1,%RDI

(105) 0x4106fc JE	410778

(105) 0x4106fe CMP	$0x2,%RDI

(105) 0x410702 JE	410742

(105) 0x410704 VMOVUPD	(%R12),%YMM5

(105) 0x41070a VMOVUPD	0x20(%R12),%YMM4

(105) 0x410711 VMOVUPD	0x40(%R12),%YMM2

(105) 0x410718 VFMADD213PD	(%R11),%YMM0,%YMM5

(105) 0x41071d VFMADD213PD	0x20(%R11),%YMM0,%YMM4

(105) 0x410723 VFMADD213PD	0x40(%R11),%YMM0,%YMM2

(105) 0x410729 ADD	$0x60,%RAX

(105) 0x41072d ADD	$0x60,%RDX

(105) 0x410731 VMOVUPD	%YMM5,(%R11)

(105) 0x410736 VMOVUPD	%YMM4,0x20(%R11)

(105) 0x41073c VMOVUPD	%YMM2,0x40(%R11)

(105) 0x410742 VMOVUPD	(%RDX),%YMM6

(105) 0x410746 VMOVUPD	0x20(%RDX),%YMM7

(105) 0x41074b VMOVUPD	0x40(%RDX),%YMM8

(105) 0x410750 VFMADD213PD	(%RAX),%YMM0,%YMM6

(105) 0x410755 VFMADD213PD	0x20(%RAX),%YMM0,%YMM7

(105) 0x41075b VFMADD213PD	0x40(%RAX),%YMM0,%YMM8

(105) 0x410761 ADD	$0x60,%RDX

(105) 0x410765 ADD	$0x60,%RAX

(105) 0x410769 VMOVUPD	%YMM6,-0x60(%RAX)

(105) 0x41076e VMOVUPD	%YMM7,-0x40(%RAX)

(105) 0x410773 VMOVUPD	%YMM8,-0x20(%RAX)

(105) 0x410778 VMOVUPD	(%RDX),%YMM9

(105) 0x41077c VMOVUPD	0x20(%RDX),%YMM10

(105) 0x410781 VMOVUPD	0x40(%RDX),%YMM11

(105) 0x410786 VFMADD213PD	(%RAX),%YMM0,%YMM9

(105) 0x41078b VFMADD213PD	0x20(%RAX),%YMM0,%YMM10

(105) 0x410791 VFMADD213PD	0x40(%RAX),%YMM0,%YMM11

(105) 0x410797 ADD	$0x60,%RAX

(105) 0x41079b ADD	$0x60,%RDX

(105) 0x41079f VMOVUPD	%YMM9,-0x60(%RAX)

(105) 0x4107a4 VMOVUPD	%YMM10,-0x40(%RAX)

(105) 0x4107a9 VMOVUPD	%YMM11,-0x20(%RAX)

(105) 0x4107ae CMP	%RAX,%R13

(105) 0x4107b1 JE	4108c1

  (107) 0x4107b7 VMOVUPD	(%RDX),%YMM12

  (107) 0x4107bb VMOVUPD	0x20(%RDX),%YMM7

  (107) 0x4107c0 VMOVUPD	0x40(%RDX),%YMM13

  (107) 0x4107c5 VFMADD213PD	0x20(%RAX),%YMM0,%YMM7

  (107) 0x4107cb VFMADD213PD	(%RAX),%YMM0,%YMM12

  (107) 0x4107d0 VFMADD213PD	0x40(%RAX),%YMM0,%YMM13

  (107) 0x4107d6 ADD	$0x180,%RAX

  (107) 0x4107dc ADD	$0x180,%RDX

  (107) 0x4107e3 VMOVUPD	%YMM7,-0x160(%RAX)

  (107) 0x4107eb VMOVUPD	%YMM12,-0x180(%RAX)

  (107) 0x4107f3 VMOVUPD	%YMM13,-0x140(%RAX)

  (107) 0x4107fb VMOVUPD	-0x120(%RDX),%YMM14

  (107) 0x410803 VMOVUPD	-0x100(%RDX),%YMM15

  (107) 0x41080b VMOVUPD	-0xe0(%RDX),%YMM5

  (107) 0x410813 VFMADD213PD	-0x120(%RAX),%YMM0,%YMM14

  (107) 0x41081c VFMADD213PD	-0x100(%RAX),%YMM0,%YMM15

  (107) 0x410825 VFMADD213PD	-0xe0(%RAX),%YMM0,%YMM5

  (107) 0x41082e VMOVUPD	%YMM14,-0x120(%RAX)

  (107) 0x410836 VMOVUPD	%YMM15,-0x100(%RAX)

  (107) 0x41083e VMOVUPD	%YMM5,-0xe0(%RAX)

  (107) 0x410846 VMOVUPD	-0xc0(%RDX),%YMM4

  (107) 0x41084e VMOVUPD	-0xa0(%RDX),%YMM6

  (107) 0x410856 VMOVUPD	-0x80(%RDX),%YMM2

  (107) 0x41085b VFMADD213PD	-0xc0(%RAX),%YMM0,%YMM4

  (107) 0x410864 VFMADD213PD	-0xa0(%RAX),%YMM0,%YMM6

  (107) 0x41086d VFMADD213PD	-0x80(%RAX),%YMM0,%YMM2

  (107) 0x410873 VMOVUPD	%YMM4,-0xc0(%RAX)

  (107) 0x41087b VMOVUPD	%YMM6,-0xa0(%RAX)

  (107) 0x410883 VMOVUPD	%YMM2,-0x80(%RAX)

  (107) 0x410888 VMOVUPD	-0x60(%RDX),%YMM8

  (107) 0x41088d VMOVUPD	-0x40(%RDX),%YMM7

  (107) 0x410892 VMOVUPD	-0x20(%RDX),%YMM9

  (107) 0x410897 VFMADD213PD	-0x60(%RAX),%YMM0,%YMM8

  (107) 0x41089d VFMADD213PD	-0x40(%RAX),%YMM0,%YMM7

  (107) 0x4108a3 VFMADD213PD	-0x20(%RAX),%YMM0,%YMM9

  (107) 0x4108a9 VMOVUPD	%YMM8,-0x60(%RAX)

  (107) 0x4108ae VMOVUPD	%YMM7,-0x40(%RAX)

  (107) 0x4108b3 VMOVUPD	%YMM9,-0x20(%RAX)

  (107) 0x4108b8 CMP	%RAX,%R13

  (107) 0x4108bb JNE	4107b7

(105) 0x4108c1 MOV	%ECX,%EDI

(105) 0x4108c3 AND	$-0x4,%EDI

(105) 0x4108c6 TEST	$0x3,%CL

(105) 0x4108c9 JE	41096f

(105) 0x4108cf SUB	%EDI,%ECX

(105) 0x4108d1 ADD	%EDI,%R10D

(105) 0x4108d4 MOV	%ECX,%EDX

(105) 0x4108d6 CMP	$0x1,%ECX

(105) 0x4108d9 JE	41092e

(105) 0x4108db LEA	(%RDI,%RDI,2),%RCX

(105) 0x4108df LEA	(%R9,%RCX,8),%R11

(105) 0x4108e3 LEA	(%R8,%R11,1),%R12

(105) 0x4108e7 ADD	%RBX,%R11

(105) 0x4108ea VMOVUPD	(%R11),%XMM10

(105) 0x4108ef VMOVUPD	0x10(%R11),%XMM11

(105) 0x4108f5 VMOVUPD	0x20(%R11),%XMM12

(105) 0x4108fb VFMADD213PD	(%R12),%XMM3,%XMM10

(105) 0x410901 VFMADD213PD	0x10(%R12),%XMM3,%XMM11

(105) 0x410908 VFMADD213PD	0x20(%R12),%XMM3,%XMM12

(105) 0x41090f VMOVUPD	%XMM10,(%R12)

(105) 0x410915 VMOVUPD	%XMM11,0x10(%R12)

(105) 0x41091c VMOVUPD	%XMM12,0x20(%R12)

(105) 0x410923 TEST	$0x1,%DL

(105) 0x410926 JE	41096f

(105) 0x410928 AND	$-0x2,%EDX

(105) 0x41092b ADD	%EDX,%R10D

(105) 0x41092e MOVSXD	%R10D,%R10

(105) 0x410931 LEA	(%R10,%R10,2),%RAX

(105) 0x410935 SAL	$0x3,%RAX

(105) 0x410939 ADD	%RAX,%R8

(105) 0x41093c ADD	%RBX,%RAX

(105) 0x41093f VMOVSD	(%RAX),%XMM13

(105) 0x410943 VFMADD213SD	(%R8),%XMM1,%XMM13

(105) 0x410948 VMOVSD	%XMM13,(%R8)

(105) 0x41094d VMOVSD	0x8(%RAX),%XMM14

(105) 0x410952 VFMADD213SD	0x8(%R8),%XMM1,%XMM14

(105) 0x410958 VMOVSD	%XMM14,0x8(%R8)

(105) 0x41095e VMOVSD	0x10(%RAX),%XMM15

(105) 0x410963 VFMADD213SD	0x10(%R8),%XMM1,%XMM15

(105) 0x410969 VMOVSD	%XMM15,0x10(%R8)

(105) 0x41096f INC	%RSI

(105) 0x410972 ADD	$0x600,%R9

(105) 0x410979 CMP	%ESI,0x1c(%RSP)

(105) 0x41097d JG	410658

0x410983 VZEROUPPER

0x410986 LEA	-0x28(%RBP),%RSP

0x41098a POP	%RBX

0x41098b POP	%R12

0x41098d POP	%R13

0x41098f POP	%R14

0x410991 POP	%R15

0x410993 POP	%RBP

0x410994 RET

0x410995 NOPL	(%RAX)

(105) 0x410998 LEA	(%RCX,%RCX,2),%R8

(105) 0x41099c LEA	-0x18(,%R8,8),%R13

(105) 0x4109a4 SHR	$0x3,%R13

(105) 0x4109a8 MOV	$0xaaaaaaaaaaaaaab,%R14

(105) 0x4109b2 IMUL	%R14,%R13

(105) 0x4109b6 MOV	%R11,%RBX

(105) 0x4109b9 MOV	%R12,%RDX

(105) 0x4109bc INC	%R13

(105) 0x4109bf LEA	(%R11,%R8,8),%RDI

(105) 0x4109c3 AND	$0x7,%R13D

(105) 0x4109c7 JE	410b54

(105) 0x4109cd CMP	$0x1,%R13

(105) 0x4109d1 JE	410b14

(105) 0x4109d7 CMP	$0x2,%R13

(105) 0x4109db JE	410add

(105) 0x4109e1 CMP	$0x3,%R13

(105) 0x4109e5 JE	410aa6

(105) 0x4109eb CMP	$0x4,%R13

(105) 0x4109ef JE	410a6f

(105) 0x4109f1 CMP	$0x5,%R13

(105) 0x4109f5 JE	410a38

(105) 0x4109f7 CMP	$0x6,%R13

(105) 0x4109fb JNE	410d44

(105) 0x410a01 VMOVSD	(%RDX),%XMM2

(105) 0x410a05 ADD	$0x18,%RBX

(105) 0x410a09 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM2

(105) 0x410a0f ADD	$0x18,%RDX

(105) 0x410a13 VMOVSD	%XMM2,-0x18(%RBX)

(105) 0x410a18 VMOVSD	-0x10(%RDX),%XMM8

(105) 0x410a1d VFMADD213SD	-0x10(%RBX),%XMM1,%XMM8

(105) 0x410a23 VMOVSD	%XMM8,-0x10(%RBX)

(105) 0x410a28 VMOVSD	-0x8(%RDX),%XMM7

(105) 0x410a2d VFMADD213SD	-0x8(%RBX),%XMM1,%XMM7

(105) 0x410a33 VMOVSD	%XMM7,-0x8(%RBX)

(105) 0x410a38 VMOVSD	(%RDX),%XMM9

(105) 0x410a3c ADD	$0x18,%RBX

(105) 0x410a40 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM9

(105) 0x410a46 ADD	$0x18,%RDX

(105) 0x410a4a VMOVSD	%XMM9,-0x18(%RBX)

(105) 0x410a4f VMOVSD	-0x10(%RDX),%XMM10

(105) 0x410a54 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM10

(105) 0x410a5a VMOVSD	%XMM10,-0x10(%RBX)

(105) 0x410a5f VMOVSD	-0x8(%RDX),%XMM11

(105) 0x410a64 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM11

(105) 0x410a6a VMOVSD	%XMM11,-0x8(%RBX)

(105) 0x410a6f VMOVSD	(%RDX),%XMM12

(105) 0x410a73 ADD	$0x18,%RBX

(105) 0x410a77 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM12

(105) 0x410a7d ADD	$0x18,%RDX

(105) 0x410a81 VMOVSD	%XMM12,-0x18(%RBX)

(105) 0x410a86 VMOVSD	-0x10(%RDX),%XMM13

(105) 0x410a8b VFMADD213SD	-0x10(%RBX),%XMM1,%XMM13

(105) 0x410a91 VMOVSD	%XMM13,-0x10(%RBX)

(105) 0x410a96 VMOVSD	-0x8(%RDX),%XMM14

(105) 0x410a9b VFMADD213SD	-0x8(%RBX),%XMM1,%XMM14

(105) 0x410aa1 VMOVSD	%XMM14,-0x8(%RBX)

(105) 0x410aa6 VMOVSD	(%RDX),%XMM15

(105) 0x410aaa ADD	$0x18,%RBX

(105) 0x410aae VFMADD213SD	-0x18(%RBX),%XMM1,%XMM15

(105) 0x410ab4 ADD	$0x18,%RDX

(105) 0x410ab8 VMOVSD	%XMM15,-0x18(%RBX)

(105) 0x410abd VMOVSD	-0x10(%RDX),%XMM5

(105) 0x410ac2 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM5

(105) 0x410ac8 VMOVSD	%XMM5,-0x10(%RBX)

(105) 0x410acd VMOVSD	-0x8(%RDX),%XMM4

(105) 0x410ad2 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM4

(105) 0x410ad8 VMOVSD	%XMM4,-0x8(%RBX)

(105) 0x410add VMOVSD	(%RDX),%XMM6

(105) 0x410ae1 ADD	$0x18,%RBX

(105) 0x410ae5 VFMADD213SD	-0x18(%RBX),%XMM1,%XMM6

(105) 0x410aeb ADD	$0x18,%RDX

(105) 0x410aef VMOVSD	%XMM6,-0x18(%RBX)

(105) 0x410af4 VMOVSD	-0x10(%RDX),%XMM2

(105) 0x410af9 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM2

(105) 0x410aff VMOVSD	%XMM2,-0x10(%RBX)

(105) 0x410b04 VMOVSD	-0x8(%RDX),%XMM8

(105) 0x410b09 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM8

(105) 0x410b0f VMOVSD	%XMM8,-0x8(%RBX)

(105) 0x410b14 VMOVSD	(%RDX),%XMM7

(105) 0x410b18 ADD	$0x18,%RBX

(105) 0x410b1c VFMADD213SD	-0x18(%RBX),%XMM1,%XMM7

(105) 0x410b22 ADD	$0x18,%RDX

(105) 0x410b26 VMOVSD	%XMM7,-0x18(%RBX)

(105) 0x410b2b VMOVSD	-0x10(%RDX),%XMM9

(105) 0x410b30 VFMADD213SD	-0x10(%RBX),%XMM1,%XMM9

(105) 0x410b36 VMOVSD	%XMM9,-0x10(%RBX)

(105) 0x410b3b VMOVSD	-0x8(%RDX),%XMM10

(105) 0x410b40 VFMADD213SD	-0x8(%RBX),%XMM1,%XMM10

(105) 0x410b46 VMOVSD	%XMM10,-0x8(%RBX)

(105) 0x410b4b CMP	%RDI,%RBX

(105) 0x410b4e JE	41096f

  (106) 0x410b54 VMOVSD	(%RDX),%XMM11

  (106) 0x410b58 ADD	$0xc0,%RBX

  (106) 0x410b5f VFMADD213SD	-0xc0(%RBX),%XMM1,%XMM11

  (106) 0x410b68 ADD	$0xc0,%RDX

  (106) 0x410b6f VMOVSD	%XMM11,-0xc0(%RBX)

  (106) 0x410b77 VMOVSD	-0xb8(%RDX),%XMM12

  (106) 0x410b7f VFMADD213SD	-0xb8(%RBX),%XMM1,%XMM12

  (106) 0x410b88 VMOVSD	%XMM12,-0xb8(%RBX)

  (106) 0x410b90 VMOVSD	-0xb0(%RDX),%XMM13

  (106) 0x410b98 VFMADD213SD	-0xb0(%RBX),%XMM1,%XMM13

  (106) 0x410ba1 VMOVSD	%XMM13,-0xb0(%RBX)

  (106) 0x410ba9 VMOVSD	-0xa8(%RDX),%XMM14

  (106) 0x410bb1 VFMADD213SD	-0xa8(%RBX),%XMM1,%XMM14

  (106) 0x410bba VMOVSD	%XMM14,-0xa8(%RBX)

  (106) 0x410bc2 VMOVSD	-0xa0(%RDX),%XMM15

  (106) 0x410bca VFMADD213SD	-0xa0(%RBX),%XMM1,%XMM15

  (106) 0x410bd3 VMOVSD	%XMM15,-0xa0(%RBX)

  (106) 0x410bdb VMOVSD	-0x98(%RDX),%XMM5

  (106) 0x410be3 VFMADD213SD	-0x98(%RBX),%XMM1,%XMM5

  (106) 0x410bec VMOVSD	%XMM5,-0x98(%RBX)

  (106) 0x410bf4 VMOVSD	-0x90(%RDX),%XMM4

  (106) 0x410bfc VFMADD213SD	-0x90(%RBX),%XMM1,%XMM4

  (106) 0x410c05 VMOVSD	%XMM4,-0x90(%RBX)

  (106) 0x410c0d VMOVSD	-0x88(%RDX),%XMM6

  (106) 0x410c15 VFMADD213SD	-0x88(%RBX),%XMM1,%XMM6

  (106) 0x410c1e VMOVSD	%XMM6,-0x88(%RBX)

  (106) 0x410c26 VMOVSD	-0x80(%RDX),%XMM2

  (106) 0x410c2b VFMADD213SD	-0x80(%RBX),%XMM1,%XMM2

  (106) 0x410c31 VMOVSD	%XMM2,-0x80(%RBX)

  (106) 0x410c36 VMOVSD	-0x78(%RDX),%XMM8

  (106) 0x410c3b VFMADD213SD	-0x78(%RBX),%XMM1,%XMM8

  (106) 0x410c41 VMOVSD	%XMM8,-0x78(%RBX)

  (106) 0x410c46 VMOVSD	-0x70(%RDX),%XMM7

  (106) 0x410c4b VFMADD213SD	-0x70(%RBX),%XMM1,%XMM7

  (106) 0x410c51 VMOVSD	%XMM7,-0x70(%RBX)

  (106) 0x410c56 VMOVSD	-0x68(%RDX),%XMM9

  (106) 0x410c5b VFMADD213SD	-0x68(%RBX),%XMM1,%XMM9

  (106) 0x410c61 VMOVSD	%XMM9,-0x68(%RBX)

  (106) 0x410c66 VMOVSD	-0x60(%RDX),%XMM10

  (106) 0x410c6b VFMADD213SD	-0x60(%RBX),%XMM1,%XMM10

  (106) 0x410c71 VMOVSD	%XMM10,-0x60(%RBX)

  (106) 0x410c76 VMOVSD	-0x58(%RDX),%XMM11

  (106) 0x410c7b VFMADD213SD	-0x58(%RBX),%XMM1,%XMM11

  (106) 0x410c81 VMOVSD	%XMM11,-0x58(%RBX)

  (106) 0x410c86 VMOVSD	-0x50(%RDX),%XMM12

  (106) 0x410c8b VFMADD213SD	-0x50(%RBX),%XMM1,%XMM12

  (106) 0x410c91 VMOVSD	%XMM12,-0x50(%RBX)

  (106) 0x410c96 VMOVSD	-0x48(%RDX),%XMM13

  (106) 0x410c9b VFMADD213SD	-0x48(%RBX),%XMM1,%XMM13

  (106) 0x410ca1 VMOVSD	%XMM13,-0x48(%RBX)

  (106) 0x410ca6 VMOVSD	-0x40(%RDX),%XMM14

  (106) 0x410cab VFMADD213SD	-0x40(%RBX),%XMM1,%XMM14

  (106) 0x410cb1 VMOVSD	%XMM14,-0x40(%RBX)

  (106) 0x410cb6 VMOVSD	-0x38(%RDX),%XMM15

  (106) 0x410cbb VFMADD213SD	-0x38(%RBX),%XMM1,%XMM15

  (106) 0x410cc1 VMOVSD	%XMM15,-0x38(%RBX)

  (106) 0x410cc6 VMOVSD	-0x30(%RDX),%XMM5

  (106) 0x410ccb VFMADD213SD	-0x30(%RBX),%XMM1,%XMM5

  (106) 0x410cd1 VMOVSD	%XMM5,-0x30(%RBX)

  (106) 0x410cd6 VMOVSD	-0x28(%RDX),%XMM4

  (106) 0x410cdb VFMADD213SD	-0x28(%RBX),%XMM1,%XMM4

  (106) 0x410ce1 VMOVSD	%XMM4,-0x28(%RBX)

  (106) 0x410ce6 VMOVSD	-0x20(%RDX),%XMM6

  (106) 0x410ceb VFMADD213SD	-0x20(%RBX),%XMM1,%XMM6

  (106) 0x410cf1 VMOVSD	%XMM6,-0x20(%RBX)

  (106) 0x410cf6 VMOVSD	-0x18(%RDX),%XMM2

  (106) 0x410cfb VFMADD213SD	-0x18(%RBX),%XMM1,%XMM2

  (106) 0x410d01 VMOVSD	%XMM2,-0x18(%RBX)

  (106) 0x410d06 VMOVSD	-0x10(%RDX),%XMM8

  (106) 0x410d0b VFMADD213SD	-0x10(%RBX),%XMM1,%XMM8

  (106) 0x410d11 VMOVSD	%XMM8,-0x10(%RBX)

  (106) 0x410d16 VMOVSD	-0x8(%RDX),%XMM7

  (106) 0x410d1b VFMADD213SD	-0x8(%RBX),%XMM1,%XMM7

  (106) 0x410d21 VMOVSD	%XMM7,-0x8(%RBX)

  (106) 0x410d26 CMP	%RDI,%RBX

  (106) 0x410d29 JNE	410b54

(105) 0x410d2f JMP	41096f

(105) 0x410d34 XOR	%EDI,%EDI

(105) 0x410d36 JMP	4108db

0x410d3b INC	%EAX

0x410d3d XOR	%EDX,%EDX

0x410d3f JMP	410616

(105) 0x410d44 VMOVSD	(%R12),%XMM5

(105) 0x410d4a ADD	$0x18,%RBX

(105) 0x410d4e VFMADD213SD	(%R11),%XMM1,%XMM5

(105) 0x410d53 ADD	$0x18,%RDX

(105) 0x410d57 VMOVSD	%XMM5,(%R11)

(105) 0x410d5c VMOVSD	0x8(%R12),%XMM4

(105) 0x410d63 VFMADD213SD	0x8(%R11),%XMM1,%XMM4

(105) 0x410d69 VMOVSD	%XMM4,0x8(%R11)

(105) 0x410d6f VMOVSD	0x10(%R12),%XMM6

(105) 0x410d76 VFMADD213SD	0x10(%R11),%XMM1,%XMM6

(105) 0x410d7c VMOVSD	%XMM6,0x10(%R11)

(105) 0x410d82 JMP	410a01

0x410d87 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○96.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○3.22	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 2.00 cycles (4.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.33 to 8.83 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	50
nb uops	56
loop length	159
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	4.00	4.00	4.00	5.00	3.40	3.50	5.00	5.00	5.00	3.60	4.00
cycles	3.50	5.53	4.00	4.00	5.00	3.40	3.50	5.00	5.00	5.00	3.60	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	9.33
Dispatch	5.53
DIV/SQRT	6.00
Overall L1	9.33

Vectorization ratios

INT

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	9%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.33 cycles. At this rate:

2% of peak load performance is reached (3.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4105e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 410d3b <advanceVelocity._omp_fn.0+0x75b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EAX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 410986 <advanceVelocity._omp_fn.0+0x3a6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x78(%RCX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RSI,2),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x9,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 410616 <advanceVelocity._omp_fn.0+0x36>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 2.00 cycles (4.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.33 to 8.83 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 12 bytes.

General properties

nb instructions	50
nb uops	56
loop length	159
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	4.00	4.00	4.00	5.00	3.40	3.50	5.00	5.00	5.00	3.60	4.00
cycles	3.50	5.53	4.00	4.00	5.00	3.40	3.50	5.00	5.00	5.00	3.60	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	9.33
Dispatch	5.53
DIV/SQRT	6.00
Overall L1	9.33

Vectorization ratios

INT

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	9%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.33 cycles. At this rate:

2% of peak load performance is reached (3.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4105e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 410d3b <advanceVelocity._omp_fn.0+0x75b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %ESI,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %EAX,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %EAX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 410986 <advanceVelocity._omp_fn.0+0x3a6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ESI,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x78(%RCX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RSI,2),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x9,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVDDUP %XMM1,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 410616 <advanceVelocity._omp_fn.0+0x36>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity._omp_fn.0–	0.65	0.03
▼Loop 105 - timestep.c:71-78 - exec–	0.33	0.01
○Loop 107 - timestep.c:74-78 - exec	0.31	0.01
○Loop 106 - timestep.c:74-78 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code