OV - exec - Function advancePosition._omp

	Function: advancePosition._omp_fn.0	Module: exec	Source: timestep.c:85-94	Coverage (incl. loops): 0.85% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x4102e0 PUSH	%RBP

0x4102e1 MOV	%RSP,%RBP

0x4102e4 PUSH	%R13

0x4102e6 PUSH	%R12

0x4102e8 PUSH	%RBX

0x4102e9 MOV	%RDI,%RBX

0x4102ec SUB	$0x8,%RSP

0x4102f0 CALL	403060 <omp_get_num_threads@plt>

0x4102f5 MOV	%EAX,%R12D

0x4102f8 CALL	403160 <omp_get_thread_num@plt>

0x4102fd MOV	%EAX,%ECX

0x4102ff MOV	0x10(%RBX),%EAX

0x410302 CLTD

0x410303 IDIV	%R12D

0x410306 CMP	%EDX,%ECX

0x410308 JL	4105d2

0x41030e IMUL	%EAX,%ECX

0x410311 ADD	%ECX,%EDX

0x410313 LEA	(%RAX,%RDX,1),%ESI

0x410316 CMP	%ESI,%EDX

0x410318 JGE	4105c7

0x41031e MOV	(%RBX),%R11

0x410321 MOVSXD	%EDX,%R8

0x410324 MOV	0x18(%R11),%RDI

0x410328 MOV	%EAX,%R13D

0x41032b MOV	0x78(%RDI),%R9

0x41032f ADD	%R8,%R13

0x410332 VMOVSD	0x8(%RBX),%XMM0

0x410337 LEA	(%R9,%R8,4),%R10

0x41033b LEA	(%R8,%R8,2),%RDI

0x41033f MOV	%R8,%R9

0x410342 LEA	(%R13,%R13,2),%RBX

0x410347 VMOVSD	0x23d9(%RIP),%XMM2

0x41034f SAL	$0x9,%RDI

0x410353 SAL	$0x6,%R9

0x410357 SAL	$0x9,%RBX

0x41035b NOPL	(%RAX,%RAX,1)

(103) 0x410360 MOVSXD	(%R10),%R8

(103) 0x410363 TEST	%R8D,%R8D

(103) 0x410366 JLE	4105af

(103) 0x41036c MOV	0x20(%R11),%RDX

(103) 0x410370 ADD	%R9,%R8

(103) 0x410373 MOV	0x10(%RDX),%R12

(103) 0x410377 MOVSXD	%R9D,%RCX

(103) 0x41037a LEA	(%R12,%R8,4),%R8

(103) 0x41037e LEA	(%R12,%RCX,4),%RCX

(103) 0x410382 MOV	%R8,%R13

(103) 0x410385 SUB	%RCX,%R13

(103) 0x410388 SUB	$0x4,%R13

(103) 0x41038c MOV	0x18(%RDX),%RAX

(103) 0x410390 SHR	$0x2,%R13

(103) 0x410394 MOV	0x20(%RDX),%RDX

(103) 0x410398 INC	%R13

(103) 0x41039b MOV	0x28(%R11),%RSI

(103) 0x41039f ADD	%RDI,%RAX

(103) 0x4103a2 ADD	%RDI,%RDX

(103) 0x4103a5 AND	$0x3,%R13D

(103) 0x4103a9 JE	4104a2

(103) 0x4103af CMP	$0x1,%R13

(103) 0x4103b3 JE	410451

(103) 0x4103b9 CMP	$0x2,%R13

(103) 0x4103bd JE	410408

(103) 0x4103bf VMULSD	(%RDX),%XMM0,%XMM3

(103) 0x4103c3 MOVSXD	(%RCX),%R12

(103) 0x4103c6 ADD	$0x18,%RAX

(103) 0x4103ca SAL	$0x4,%R12

(103) 0x4103ce VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM1

(103) 0x4103d5 VFMADD213SD	-0x18(%RAX),%XMM1,%XMM3

(103) 0x4103db ADD	$0x4,%RCX

(103) 0x4103df ADD	$0x18,%RDX

(103) 0x4103e3 VMOVSD	%XMM3,-0x18(%RAX)

(103) 0x4103e8 VMULSD	-0x10(%RDX),%XMM0,%XMM4

(103) 0x4103ed VFMADD213SD	-0x10(%RAX),%XMM1,%XMM4

(103) 0x4103f3 VMOVSD	%XMM4,-0x10(%RAX)

(103) 0x4103f8 VMULSD	-0x8(%RDX),%XMM0,%XMM5

(103) 0x4103fd VFMADD213SD	-0x8(%RAX),%XMM5,%XMM1

(103) 0x410403 VMOVSD	%XMM1,-0x8(%RAX)

(103) 0x410408 VMULSD	(%RDX),%XMM0,%XMM7

(103) 0x41040c MOVSXD	(%RCX),%R13

(103) 0x41040f ADD	$0x18,%RAX

(103) 0x410413 SAL	$0x4,%R13

(103) 0x410417 VDIVSD	0x8(%RSI,%R13,1),%XMM2,%XMM6

(103) 0x41041e VFMADD213SD	-0x18(%RAX),%XMM6,%XMM7

(103) 0x410424 ADD	$0x4,%RCX

(103) 0x410428 ADD	$0x18,%RDX

(103) 0x41042c VMOVSD	%XMM7,-0x18(%RAX)

(103) 0x410431 VMULSD	-0x10(%RDX),%XMM0,%XMM8

(103) 0x410436 VFMADD213SD	-0x10(%RAX),%XMM6,%XMM8

(103) 0x41043c VMOVSD	%XMM8,-0x10(%RAX)

(103) 0x410441 VMULSD	-0x8(%RDX),%XMM0,%XMM9

(103) 0x410446 VFMADD213SD	-0x8(%RAX),%XMM9,%XMM6

(103) 0x41044c VMOVSD	%XMM6,-0x8(%RAX)

(103) 0x410451 VMULSD	(%RDX),%XMM0,%XMM11

(103) 0x410455 MOVSXD	(%RCX),%R12

(103) 0x410458 ADD	$0x4,%RCX

(103) 0x41045c SAL	$0x4,%R12

(103) 0x410460 VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM10

(103) 0x410467 VFMADD213SD	(%RAX),%XMM10,%XMM11

(103) 0x41046c ADD	$0x18,%RDX

(103) 0x410470 ADD	$0x18,%RAX

(103) 0x410474 VMOVSD	%XMM11,-0x18(%RAX)

(103) 0x410479 VMULSD	-0x10(%RDX),%XMM0,%XMM12

(103) 0x41047e VFMADD213SD	-0x10(%RAX),%XMM10,%XMM12

(103) 0x410484 VMOVSD	%XMM12,-0x10(%RAX)

(103) 0x410489 VMULSD	-0x8(%RDX),%XMM0,%XMM13

(103) 0x41048e VFMADD213SD	-0x8(%RAX),%XMM13,%XMM10

(103) 0x410494 VMOVSD	%XMM10,-0x8(%RAX)

(103) 0x410499 CMP	%RCX,%R8

(103) 0x41049c JE	4105af

  (104) 0x4104a2 VMULSD	(%RDX),%XMM0,%XMM15

  (104) 0x4104a6 MOVSXD	(%RCX),%R13

  (104) 0x4104a9 MOVSXD	0x4(%RCX),%R12

  (104) 0x4104ad SAL	$0x4,%R13

  (104) 0x4104b1 VDIVSD	0x8(%RSI,%R13,1),%XMM2,%XMM14

  (104) 0x4104b8 VFMADD213SD	(%RAX),%XMM14,%XMM15

  (104) 0x4104bd SAL	$0x4,%R12

  (104) 0x4104c1 MOVSXD	0x8(%RCX),%R13

  (104) 0x4104c5 ADD	$0x10,%RCX

  (104) 0x4104c9 SAL	$0x4,%R13

  (104) 0x4104cd VMOVSD	%XMM15,(%RAX)

  (104) 0x4104d1 VMULSD	0x8(%RDX),%XMM0,%XMM1

  (104) 0x4104d6 ADD	$0x60,%RAX

  (104) 0x4104da ADD	$0x60,%RDX

  (104) 0x4104de VFMADD213SD	-0x58(%RAX),%XMM14,%XMM1

  (104) 0x4104e4 VMOVSD	%XMM1,-0x58(%RAX)

  (104) 0x4104e9 VMULSD	-0x50(%RDX),%XMM0,%XMM3

  (104) 0x4104ee VFMADD213SD	-0x50(%RAX),%XMM3,%XMM14

  (104) 0x4104f4 VMOVSD	%XMM14,-0x50(%RAX)

  (104) 0x4104f9 VMULSD	-0x48(%RDX),%XMM0,%XMM5

  (104) 0x4104fe VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM4

  (104) 0x410505 VFMADD213SD	-0x48(%RAX),%XMM4,%XMM5

  (104) 0x41050b VMOVSD	%XMM5,-0x48(%RAX)

  (104) 0x410510 VMULSD	-0x40(%RDX),%XMM0,%XMM6

  (104) 0x410515 VFMADD213SD	-0x40(%RAX),%XMM4,%XMM6

  (104) 0x41051b VMOVSD	%XMM6,-0x40(%RAX)

  (104) 0x410520 VMULSD	-0x38(%RDX),%XMM0,%XMM7

  (104) 0x410525 VFMADD213SD	-0x38(%RAX),%XMM7,%XMM4

  (104) 0x41052b VMOVSD	%XMM4,-0x38(%RAX)

  (104) 0x410530 VMULSD	-0x30(%RDX),%XMM0,%XMM9

  (104) 0x410535 VDIVSD	0x8(%RSI,%R13,1),%XMM2,%XMM8

  (104) 0x41053c VFMADD213SD	-0x30(%RAX),%XMM8,%XMM9

  (104) 0x410542 VMOVSD	%XMM9,-0x30(%RAX)

  (104) 0x410547 VMULSD	-0x28(%RDX),%XMM0,%XMM10

  (104) 0x41054c VFMADD213SD	-0x28(%RAX),%XMM8,%XMM10

  (104) 0x410552 VMOVSD	%XMM10,-0x28(%RAX)

  (104) 0x410557 VMULSD	-0x20(%RDX),%XMM0,%XMM11

  (104) 0x41055c VFMADD213SD	-0x20(%RAX),%XMM11,%XMM8

  (104) 0x410562 VMOVSD	%XMM8,-0x20(%RAX)

  (104) 0x410567 VMULSD	-0x18(%RDX),%XMM0,%XMM13

  (104) 0x41056c MOVSXD	-0x4(%RCX),%R12

  (104) 0x410570 SAL	$0x4,%R12

  (104) 0x410574 VDIVSD	0x8(%RSI,%R12,1),%XMM2,%XMM12

  (104) 0x41057b VFMADD213SD	-0x18(%RAX),%XMM12,%XMM13

  (104) 0x410581 VMOVSD	%XMM13,-0x18(%RAX)

  (104) 0x410586 VMULSD	-0x10(%RDX),%XMM0,%XMM14

  (104) 0x41058b VFMADD213SD	-0x10(%RAX),%XMM12,%XMM14

  (104) 0x410591 VMOVSD	%XMM14,-0x10(%RAX)

  (104) 0x410596 VMULSD	-0x8(%RDX),%XMM0,%XMM15

  (104) 0x41059b VFMADD213SD	-0x8(%RAX),%XMM15,%XMM12

  (104) 0x4105a1 VMOVSD	%XMM12,-0x8(%RAX)

  (104) 0x4105a6 CMP	%RCX,%R8

  (104) 0x4105a9 JNE	4104a2

(103) 0x4105af ADD	$0x600,%RDI

(103) 0x4105b6 ADD	$0x4,%R10

(103) 0x4105ba ADD	$0x40,%R9

(103) 0x4105be CMP	%RDI,%RBX

(103) 0x4105c1 JNE	410360

0x4105c7 ADD	$0x8,%RSP

0x4105cb POP	%RBX

0x4105cc POP	%R12

0x4105ce POP	%R13

0x4105d0 POP	%RBP

0x4105d1 RET

0x4105d2 INC	%EAX

0x4105d4 XOR	%EDX,%EDX

0x4105d6 JMP	41030e

0x4105db NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○98.63	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.37	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 1.17 cycles (7.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.67 to 1.50 cycles (5.78x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.67 to 8.17 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	52
loop length	153
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	4.00	3.67	3.67	3.00	3.47	3.50	3.00	3.00	3.00	3.53	3.67
cycles	3.50	5.53	3.67	3.67	3.00	3.47	3.50	3.00	3.00	3.00	3.53	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	8.67
Dispatch	5.53
DIV/SQRT	6.00
Overall L1	8.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

2% of peak load performance is reached (5.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4102e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 4105d2 <advancePosition._omp_fn.0+0x2f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4105c7 <advancePosition._omp_fn.0+0x2e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x18(%R11),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R9,%R8,4),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R8,2),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R13,2),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x23d9(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x9,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x9,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41030e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.67 to 1.17 cycles (7.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.67 to 8.17 cycles (1.06x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	52
loop length	153
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	4.00	3.67	3.67	3.00	3.47	3.50	3.00	3.00	3.00	3.53	3.67
cycles	3.50	5.53	3.67	3.67	3.00	3.47	3.50	3.00	3.00	3.00	3.53	3.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	8.67
Dispatch	5.53
DIV/SQRT	6.00
Overall L1	8.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.67 cycles. At this rate:

2% of peak load performance is reached (5.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4102e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 4105d2 <advancePosition._omp_fn.0+0x2f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 4105c7 <advancePosition._omp_fn.0+0x2e7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%R8	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x18(%R11),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R9,%R8,4),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R8,2),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%R13,2),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x23d9(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x9,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
SAL $0x9,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41030e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼advancePosition._omp_fn.0–	0.85	0.04
▼Loop 103 - timestep.c:88-94 - exec–	0.14	0.01
○Loop 104 - timestep.c:88-94 - exec	0.71	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code