OV - exec - Function mkSeed

	Function: mkSeed	Module: exec	Source: random.c:45-75 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.05%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 75

--------------------------------------------------------------------------------

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

[...]

68:    uint32_t s2 = (id+callSite) * UINT32_C(2654435761);

69:

70:    uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2;

71:    for (unsigned jj=0; jj<10; ++jj)

72:       lcg61(&iSeed);

73:

74:    return iSeed;

75: }

0x410130 IMUL	$-0x61c8864f,%EDI,%ECX

0x410136 ADD	%ESI,%EDI

0x410138 IMUL	$-0x61c8864f,%EDI,%EDI

0x41013e SAL	$0x20,%RCX

0x410142 MOV	$0x613606df9756715,%R8

0x41014c ADD	%RDI,%RCX

0x41014f IMUL	%R8,%RCX

0x410153 MOV	$0x9,%ESI

0x410158 MOV	%RCX,%RAX

0x41015b MUL	%RSI

0x41015e MOV	%RCX,%R9

0x410161 SUB	%RDX,%R9

0x410164 SHR	$0x1,%R9

0x410167 ADD	%R9,%RDX

0x41016a SHR	$0x3c,%RDX

0x41016e MOV	%RDX,%R10

0x410171 SAL	$0x3d,%R10

0x410175 SUB	%RDX,%R10

0x410178 SUB	%R10,%RCX

0x41017b IMUL	%R8,%RCX

0x41017f MOV	%RCX,%RAX

0x410182 MUL	%RSI

0x410185 MOV	%RCX,%R11

0x410188 SUB	%RDX,%R11

0x41018b SHR	$0x1,%R11

0x41018e ADD	%R11,%RDX

0x410191 SHR	$0x3c,%RDX

0x410195 MOV	%RDX,%RDI

0x410198 SAL	$0x3d,%RDI

0x41019c SUB	%RDX,%RDI

0x41019f SUB	%RDI,%RCX

0x4101a2 IMUL	%R8,%RCX

0x4101a6 MOV	%RCX,%RAX

0x4101a9 MUL	%RSI

0x4101ac MOV	%RCX,%R9

0x4101af SUB	%RDX,%R9

0x4101b2 SHR	$0x1,%R9

0x4101b5 ADD	%R9,%RDX

0x4101b8 SHR	$0x3c,%RDX

0x4101bc MOV	%RDX,%R10

0x4101bf SAL	$0x3d,%R10

0x4101c3 SUB	%RDX,%R10

0x4101c6 SUB	%R10,%RCX

0x4101c9 IMUL	%R8,%RCX

0x4101cd MOV	%RCX,%RAX

0x4101d0 MUL	%RSI

0x4101d3 MOV	%RCX,%R11

0x4101d6 SUB	%RDX,%R11

0x4101d9 SHR	$0x1,%R11

0x4101dc ADD	%R11,%RDX

0x4101df SHR	$0x3c,%RDX

0x4101e3 MOV	%RDX,%RDI

0x4101e6 SAL	$0x3d,%RDI

0x4101ea SUB	%RDX,%RDI

0x4101ed SUB	%RDI,%RCX

0x4101f0 IMUL	%R8,%RCX

0x4101f4 MOV	%RCX,%RAX

0x4101f7 MUL	%RSI

0x4101fa MOV	%RCX,%R9

0x4101fd SUB	%RDX,%R9

0x410200 SHR	$0x1,%R9

0x410203 ADD	%R9,%RDX

0x410206 SHR	$0x3c,%RDX

0x41020a MOV	%RDX,%R10

0x41020d SAL	$0x3d,%R10

0x410211 SUB	%RDX,%R10

0x410214 SUB	%R10,%RCX

0x410217 IMUL	%R8,%RCX

0x41021b MOV	%RCX,%RAX

0x41021e MUL	%RSI

0x410221 MOV	%RCX,%R11

0x410224 SUB	%RDX,%R11

0x410227 SHR	$0x1,%R11

0x41022a ADD	%R11,%RDX

0x41022d SHR	$0x3c,%RDX

0x410231 MOV	%RDX,%RDI

0x410234 SAL	$0x3d,%RDI

0x410238 SUB	%RDX,%RDI

0x41023b SUB	%RDI,%RCX

0x41023e IMUL	%R8,%RCX

0x410242 MOV	%RCX,%RAX

0x410245 MUL	%RSI

0x410248 MOV	%RCX,%R9

0x41024b SUB	%RDX,%R9

0x41024e SHR	$0x1,%R9

0x410251 ADD	%R9,%RDX

0x410254 SHR	$0x3c,%RDX

0x410258 MOV	%RDX,%R10

0x41025b SAL	$0x3d,%R10

0x41025f SUB	%RDX,%R10

0x410262 SUB	%R10,%RCX

0x410265 IMUL	%R8,%RCX

0x410269 MOV	%RCX,%RAX

0x41026c MUL	%RSI

0x41026f MOV	%RCX,%R11

0x410272 SUB	%RDX,%R11

0x410275 SHR	$0x1,%R11

0x410278 ADD	%R11,%RDX

0x41027b SHR	$0x3c,%RDX

0x41027f MOV	%RDX,%RDI

0x410282 SAL	$0x3d,%RDI

0x410286 SUB	%RDX,%RDI

0x410289 SUB	%RDI,%RCX

0x41028c IMUL	%R8,%RCX

0x410290 MOV	%RCX,%RAX

0x410293 MUL	%RSI

0x410296 MOV	%RCX,%R9

0x410299 SUB	%RDX,%R9

0x41029c SHR	$0x1,%R9

0x41029f ADD	%R9,%RDX

0x4102a2 SHR	$0x3c,%RDX

0x4102a6 MOV	%RDX,%R10

0x4102a9 SAL	$0x3d,%R10

0x4102ad SUB	%RDX,%R10

0x4102b0 SUB	%R10,%RCX

0x4102b3 IMUL	%R8,%RCX

0x4102b7 MOV	%RCX,%RAX

0x4102ba MUL	%RSI

0x4102bd MOV	%RCX,%R8

0x4102c0 MOV	%RCX,%RAX

0x4102c3 SUB	%RDX,%R8

0x4102c6 SHR	$0x1,%R8

0x4102c9 ADD	%R8,%RDX

0x4102cc SHR	$0x3c,%RDX

0x4102d0 MOV	%RDX,%RSI

0x4102d3 SAL	$0x3d,%RSI

0x4102d7 SUB	%RDX,%RSI

0x4102da SUB	%RSI,%RAX

0x4102dd RET

0x4102de XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
○96.88	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○3.12	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run gcc_3

Source file and lines	random.c:45-75
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 30.80 to 3.66 cycles (8.41x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	21.40	22.00	0.33	0.33	0.00	21.60	21.40	0.00	0.00	0.00	21.60	0.33
cycles	21.40	30.80	0.33	0.33	0.00	21.60	21.40	0.00	0.00	0.00	21.60	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	30.80
Overall L1	30.80

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.80 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410130

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
IMUL $-0x61c8864f,%EDI,%ECX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ESI,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
IMUL $-0x61c8864f,%EDI,%EDI	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
SAL $0x20,%RCX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV $0x613606df9756715,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.28	scal (12.5%)
ADD %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV $0x9,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R8	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R8,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3d,%RSI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SUB %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
RET	1	0.50	0	0.33	0.33	0	0.50	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run gcc_3

Source file and lines	random.c:45-75
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	21.40	22.00	0.33	0.33	0.00	21.60	21.40	0.00	0.00	0.00	21.60	0.33
cycles	21.40	30.80	0.33	0.33	0.00	21.60	21.40	0.00	0.00	0.00	21.60	0.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	30.80
Overall L1	30.80

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.80 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 410130

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
IMUL $-0x61c8864f,%EDI,%ECX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ESI,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
IMUL $-0x61c8864f,%EDI,%EDI	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
SAL $0x20,%RCX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV $0x613606df9756715,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.28	scal (12.5%)
ADD %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV $0x9,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R11	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R11,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %RDI,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R9	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R9,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
SUB %RDX,%R10	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SUB %R10,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MUL %RSI	2	0	1	0	0	1	0	0	0	3-4	1	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%R8	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x1,%R8	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
ADD %R8,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
SHR $0x3c,%RDX	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x3d,%RSI	1	0.50	0	0	0	0	0.50	0	0	0-2	0.50	N/A
SUB %RDX,%RSI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
SUB %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
RET	1	0.50	0	0.33	0.33	0	0.50	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
○mkSeed	0.05	0.00

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Vectorization

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code