OV - exec - Function gasdev

	Function: gasdev	Module: exec	Source: random.c:22-48 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.04%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 22 - 48

--------------------------------------------------------------------------------

22: {

23:    real_t rsq,v1,v2;

24:    do

25:    {

26:       v1 = 2.0*lcg61(seed)-1.0;

27:       v2 = 2.0*lcg61(seed)-1.0;

28:       rsq = v1*v1+v2*v2;

29:    } while (rsq >= 1.0 || rsq == 0.0);

30:

31:    return v2 * sqrt(-2.0*log(rsq)/rsq);

32: }

[...]

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

47:

48:    return *seed*convertToDouble;

0x40fff0 PUSH	%RBP

0x40fff1 MOV	%RDI,%R8

0x40fff4 VXORPS	%XMM5,%XMM5,%XMM5

0x40fff8 MOV	%RSP,%RBP

0x40fffb SUB	$0x10,%RSP

0x40ffff VMOVSD	0x3b29(%RIP),%XMM4

0x410007 VMOVSD	0x2ec1(%RIP),%XMM3

0x41000f VMOVSD	0x2711(%RIP),%XMM6

0x410017 MOV	(%RDI),%RCX

0x41001a MOV	$0x9,%ESI

0x41001f MOV	$0x613606df9756715,%RDI

0x410029 VXORPD	%XMM7,%XMM7,%XMM7

0x41002d NOPL	(%RAX)

(102) 0x410030 IMUL	%RDI,%RCX

(102) 0x410034 MOV	%RCX,%RAX

(102) 0x410037 MUL	%RSI

(102) 0x41003a MOV	%RCX,%R9

(102) 0x41003d SUB	%RDX,%R9

(102) 0x410040 SHR	$0x1,%R9

(102) 0x410043 ADD	%R9,%RDX

(102) 0x410046 SHR	$0x3c,%RDX

(102) 0x41004a MOV	%RDX,%R10

(102) 0x41004d SAL	$0x3d,%R10

(102) 0x410051 SUB	%RDX,%R10

(102) 0x410054 SUB	%R10,%RCX

(102) 0x410057 VCVTSI2SD	%RCX,%XMM5,%XMM0

(102) 0x41005c IMUL	%RDI,%RCX

(102) 0x410060 MOV	%RCX,%RAX

(102) 0x410063 MUL	%RSI

(102) 0x410066 MOV	%RCX,%R11

(102) 0x410069 VFMADD132SD	%XMM4,%XMM3,%XMM0

(102) 0x41006e SUB	%RDX,%R11

(102) 0x410071 SHR	$0x1,%R11

(102) 0x410074 ADD	%R11,%RDX

(102) 0x410077 SHR	$0x3c,%RDX

(102) 0x41007b MOV	%RDX,%R9

(102) 0x41007e SAL	$0x3d,%R9

(102) 0x410082 SUB	%RDX,%R9

(102) 0x410085 SUB	%R9,%RCX

(102) 0x410088 VCVTSI2SD	%RCX,%XMM5,%XMM2

(102) 0x41008d VFMADD132SD	%XMM4,%XMM3,%XMM2

(102) 0x410092 VMULSD	%XMM2,%XMM2,%XMM1

(102) 0x410096 VFMADD231SD	%XMM0,%XMM0,%XMM1

(102) 0x41009b VCOMISD	%XMM6,%XMM1

(102) 0x41009f JAE	410030

(102) 0x4100a1 VCOMISD	%XMM7,%XMM1

(102) 0x4100a5 JE	410030

0x4100a7 MOV	%RCX,(%R8)

0x4100aa VMOVAPD	%XMM1,%XMM0

0x4100ae VMOVSD	%XMM2,-0x10(%RBP)

0x4100b3 VMOVSD	%XMM1,-0x8(%RBP)

0x4100b8 CALL	403150 <log@plt>

0x4100bd VMULSD	0x3a73(%RIP),%XMM0,%XMM8

0x4100c5 VMOVSD	-0x8(%RBP),%XMM9

0x4100ca VMOVSD	-0x10(%RBP),%XMM11

0x4100cf LEAVE

0x4100d0 VDIVSD	%XMM9,%XMM8,%XMM10

0x4100d5 VSQRTSD	%XMM10,%XMM10,%XMM10

0x4100da VMULSD	%XMM11,%XMM10,%XMM0

0x4100df RET

Coverage (%)	Name	Source Location	Module
○48.23	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►34.75+	setTemperature._omp_fn.0	initAtoms.c:160	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►8.51+	setTemperature._omp_fn.0	initAtoms.c:162	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
►7.80+	setTemperature._omp_fn.0	initAtoms.c:161	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run gcc_3

Source file and lines	random.c:22-48
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:22-32,45-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.50 to 4.25 cycles (2.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 4.83 cycles (1.76x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.50 to 4.83 cycles (1.76x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

log@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:31

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEAVE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:32

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: multiply
1: divide
1: square root

The binary function is loading 56 bytes (7 double precision FP elements). The binary function is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	29
loop length	121
used x86 registers	7
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.00	3.00	3.00	2.50	2.00	2.00	2.50	2.50	2.50	2.00	3.00
cycles	2.00	2.00	3.00	3.00	2.50	2.00	2.00	2.50	2.50	2.50	2.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

8.50

Cycles summary

Front-end	4.83
Dispatch	3.00
DIV/SQRT	8.50
Overall L1	8.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	21%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	100%

INT+FP

all	17%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	75%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	25%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (6.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40fff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x3b29(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x2ec1(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x2711(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x9,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x613606df9756715,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,-0x10(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 403150 <log@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMULSD 0x3a73(%RIP),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD -0x8(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x10(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
VDIVSD %XMM9,%XMM8,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VSQRTSD %XMM10,%XMM10,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run gcc_3

Source file and lines	random.c:22-48
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:22-32,45-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.50 to 4.83 cycles (1.76x speedup).

CALL instructions

Detected function call instructions.

Details

log@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:31

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEAVE: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:32

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

2: multiply
1: divide
1: square root

The binary function is loading 56 bytes (7 double precision FP elements). The binary function is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	29
loop length	121
used x86 registers	7
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.00	3.00	3.00	2.50	2.00	2.00	2.50	2.50	2.50	2.00	3.00
cycles	2.00	2.00	3.00	3.00	2.50	2.00	2.00	2.50	2.50	2.50	2.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

8.50

Cycles summary

Front-end	4.83
Dispatch	3.00
DIV/SQRT	8.50
Overall L1	8.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	21%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	100%

INT+FP

all	17%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	75%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	15%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	25%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (6.59 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40fff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x10,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x3b29(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x2ec1(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x2711(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $0x9,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x613606df9756715,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVSD %XMM2,-0x10(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 403150 <log@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMULSD 0x3a73(%RIP),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD -0x8(%RBP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x10(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEAVE	3	0.60	0.60	0.33	0.33	0	0.60	0.60	0	0	0	0.60	0.33	2-6	2	N/A
VDIVSD %XMM9,%XMM8,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4	scal (12.5%)
VSQRTSD %XMM10,%XMM10,%XMM10	1	1	0	0	0	0	0	0	0	0	0	0	0	13-19	4.50	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
▼gasdev–	0.07	0.00
○Loop 102 - random.c:26-48 - exec	0.03	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code