OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.1	Module: exec	Source: ljForce.c:172-216 [...]	Coverage (incl. loops): 70.33% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

0x40d540 PUSH	%RBP

0x40d541 MOV	%RSP,%RBP

0x40d544 PUSH	%R15

0x40d546 PUSH	%R14

0x40d548 PUSH	%R13

0x40d54a PUSH	%R12

0x40d54c PUSH	%RBX

0x40d54d MOV	%RDI,%RBX

0x40d550 SUB	$0x58,%RSP

0x40d554 MOV	(%RDI),%RAX

0x40d557 MOV	0x18(%RAX),%R13

0x40d55b MOV	%RAX,-0x58(%RBP)

0x40d55f CALL	403060 <omp_get_num_threads@plt>

0x40d564 MOV	%EAX,%R12D

0x40d567 CALL	403160 <omp_get_thread_num@plt>

0x40d56c MOV	%EAX,%ECX

0x40d56e MOV	0xc(%R13),%EAX

0x40d572 CLTD

0x40d573 IDIV	%R12D

0x40d576 CMP	%EDX,%ECX

0x40d578 JL	40dbbd

0x40d57e IMUL	%EAX,%ECX

0x40d581 ADD	%ECX,%EDX

0x40d583 LEA	(%RAX,%RDX,1),%ESI

0x40d586 CMP	%ESI,%EDX

0x40d588 JGE	40db80

0x40d58e MOVSXD	%EDX,%RDI

0x40d591 MOV	%RDI,%R11

0x40d594 MOVSXD	0x30(%RBX),%R8

0x40d598 VMOVSD	0x5c18(%RIP),%XMM8

0x40d5a0 NOT	%R11

0x40d5a3 SAL	$0x6,%EDX

0x40d5a6 ADD	%ESI,%R11D

0x40d5a9 VMULSD	0x8(%RBX),%XMM8,%XMM8

0x40d5ae VMOVSD	0x20(%RBX),%XMM9

0x40d5b3 VMOVSD	0x18(%RBX),%XMM10

0x40d5b8 VMOVSD	0x10(%RBX),%XMM4

0x40d5bd MOV	0x78(%R13),%R15

0x40d5c1 MOV	%R8,%R10

0x40d5c4 MOV	%EDX,%R9D

0x40d5c7 LEA	(,%R8,4),%R14

0x40d5cf AND	$0x7,%R11D

0x40d5d3 TEST	%R8D,%R8D

0x40d5d6 JLE	40dac4

0x40d5dc MOV	(%R15,%RDI,4),%R11D

0x40d5e0 MOV	0x80(%R13),%R8

0x40d5e7 VMOVSD	0x5bd1(%RIP),%XMM7

0x40d5ef VMOVSD	0x5bd1(%RIP),%XMM6

0x40d5f7 VMOVSD	0x5bd1(%RIP),%XMM12

0x40d5ff VMOVSD	0x5bd1(%RIP),%XMM11

0x40d607 VXORPD	%XMM5,%XMM5,%XMM5

0x40d60b MOV	%R9D,%EDX

0x40d60e MOV	%R14,%RCX

(92) 0x40d611 MOV	%EDI,%R10D

(92) 0x40d614 SAL	$0x6,%R10D

(92) 0x40d618 MOV	(%R8,%RDI,8),%RAX

(92) 0x40d61c MOVSXD	%R10D,%R9

(92) 0x40d61f LEA	(%RCX,%RAX,1),%R12

(92) 0x40d623 LEA	(,%R9,8),%R13

(92) 0x40d62b MOV	%R12,-0x60(%RBP)

(92) 0x40d62f MOV	%R13,-0x48(%RBP)

(92) 0x40d633 MOV	%ESI,-0x64(%RBP)

(92) 0x40d636 MOV	%R15,-0x50(%RBP)

(92) 0x40d63a MOV	%RDI,-0x70(%RBP)

(92) 0x40d63e MOV	%RCX,-0x78(%RBP)

(92) 0x40d642 MOV	%R11D,-0x38(%RBP)

(92) 0x40d646 MOV	%RBX,-0x80(%RBP)

(92) 0x40d64a LEA	(%R11,%RDX,1),%R14D

(92) 0x40d64e MOV	%R8,%R10

  (91) 0x40d651 MOV	(%RAX),%R13D

  (91) 0x40d654 TEST	%R13D,%R13D

  (91) 0x40d657 JS	40dbc6

  (91) 0x40d65d MOV	-0x50(%RBP),%RBX

  (91) 0x40d661 MOV	-0x38(%RBP),%R15D

  (91) 0x40d665 MOVSXD	%R13D,%RDI

  (91) 0x40d668 MOV	(%RBX,%RDI,4),%ESI

  (91) 0x40d66b TEST	%R15D,%R15D

  (91) 0x40d66e JLE	40d73f

  (91) 0x40d674 MOV	%EDX,%ECX

  (91) 0x40d676 NOT	%ECX

  (91) 0x40d678 SAL	$0x6,%R13D

  (91) 0x40d67c LEA	(%RDI,%RDI,2),%R15

  (91) 0x40d680 ADD	%R14D,%ECX

  (91) 0x40d683 MOV	-0x48(%RBP),%R8

  (91) 0x40d687 LEA	(%RSI,%R13,1),%R9D

  (91) 0x40d68b SAL	$0x9,%R15

  (91) 0x40d68f MOV	%EDX,%R12D

  (91) 0x40d692 AND	$0x7,%ECX

  (91) 0x40d695 TEST	%ESI,%ESI

  (91) 0x40d697 JG	40d77a

  (91) 0x40d69d LEA	0x1(%RDX),%R12D

  (91) 0x40d6a1 LEA	0x8(%R8),%R8

  (91) 0x40d6a5 CMP	%R14D,%R12D

  (91) 0x40d6a8 JGE	40d73f

  (91) 0x40d6ae TEST	%ECX,%ECX

  (91) 0x40d6b0 JE	40d72e

  (91) 0x40d6b2 CMP	$0x1,%ECX

  (91) 0x40d6b5 JE	40d71e

  (91) 0x40d6b7 CMP	$0x2,%ECX

  (91) 0x40d6ba JE	40d713

  (91) 0x40d6bc CMP	$0x3,%ECX

  (91) 0x40d6bf JE	40d708

  (91) 0x40d6c1 CMP	$0x4,%ECX

  (91) 0x40d6c4 JE	40d6fd

  (91) 0x40d6c6 CMP	$0x5,%ECX

  (91) 0x40d6c9 JE	40d6ee

  (91) 0x40d6cb CMP	$0x6,%ECX

  (91) 0x40d6ce JE	40d6df

  (91) 0x40d6d0 TEST	%ESI,%ESI

  (91) 0x40d6d2 JG	40d77a

  (91) 0x40d6d8 INC	%R12D

  (91) 0x40d6db ADD	$0x8,%R8

  (91) 0x40d6df TEST	%ESI,%ESI

  (91) 0x40d6e1 JG	40d77a

  (91) 0x40d6e7 INC	%R12D

  (91) 0x40d6ea ADD	$0x8,%R8

  (91) 0x40d6ee TEST	%ESI,%ESI

  (91) 0x40d6f0 JG	40d77a

  (91) 0x40d6f6 INC	%R12D

  (91) 0x40d6f9 ADD	$0x8,%R8

  (91) 0x40d6fd TEST	%ESI,%ESI

  (91) 0x40d6ff JG	40d77a

  (91) 0x40d701 INC	%R12D

  (91) 0x40d704 ADD	$0x8,%R8

  (91) 0x40d708 TEST	%ESI,%ESI

  (91) 0x40d70a JG	40d77a

  (91) 0x40d70c INC	%R12D

  (91) 0x40d70f ADD	$0x8,%R8

  (91) 0x40d713 TEST	%ESI,%ESI

  (91) 0x40d715 JG	40d77a

  (91) 0x40d717 INC	%R12D

  (91) 0x40d71a ADD	$0x8,%R8

  (91) 0x40d71e TEST	%ESI,%ESI

  (91) 0x40d720 JG	40d77a

  (91) 0x40d722 INC	%R12D

  (91) 0x40d725 ADD	$0x8,%R8

  (91) 0x40d729 CMP	%R14D,%R12D

  (91) 0x40d72c JGE	40d73f

    (95) 0x40d72e TEST	%ESI,%ESI

    (95) 0x40d730 JG	40d77a

    (95) 0x40d732 ADD	$0x8,%R12D

    (95) 0x40d736 ADD	$0x40,%R8

    (95) 0x40d73a CMP	%R14D,%R12D

    (95) 0x40d73d JL	40d72e

  (91) 0x40d73f ADD	$0x4,%RAX

  (91) 0x40d743 CMP	%RAX,-0x60(%RBP)

  (91) 0x40d747 JNE	40d651

(92) 0x40d74d MOV	-0x70(%RBP),%RDI

(92) 0x40d751 MOV	-0x64(%RBP),%ESI

(92) 0x40d754 INC	%RDI

(92) 0x40d757 MOV	-0x50(%RBP),%R15

(92) 0x40d75b MOV	-0x78(%RBP),%RCX

(92) 0x40d75f MOV	-0x80(%RBP),%RBX

(92) 0x40d763 MOV	%R10,%R8

(92) 0x40d766 ADD	$0x40,%EDX

(92) 0x40d769 CMP	%EDI,%ESI

(92) 0x40d76b JLE	40db84

(92) 0x40d771 MOV	(%R15,%RDI,4),%R11D

(92) 0x40d775 JMP	40d611

  (91) 0x40d77a MOV	-0x58(%RBP),%R11

  (91) 0x40d77e MOV	%EDX,-0x34(%RBP)

  (91) 0x40d781 MOV	%RAX,-0x40(%RBP)

  (91) 0x40d785 MOV	0x20(%R11),%R11

  (91) 0x40d789 VXORPD	%XMM3,%XMM3,%XMM3

  (91) 0x40d78d NOPL	(%RAX)

    (93) 0x40d790 MOV	0x18(%R11),%RSI

    (93) 0x40d794 LEA	(%R8,%R8,2),%RBX

    (93) 0x40d798 LEA	(%RSI,%RBX,1),%RDX

    (93) 0x40d79c VMOVSD	0x8(%RDX),%XMM1

    (93) 0x40d7a1 ADD	%R15,%RSI

    (93) 0x40d7a4 VSUBSD	0x8(%RSI),%XMM1,%XMM1

    (93) 0x40d7a9 VMOVSD	(%RDX),%XMM2

    (93) 0x40d7ad VMOVSD	0x10(%RDX),%XMM13

    (93) 0x40d7b2 VMULSD	%XMM1,%XMM1,%XMM0

    (93) 0x40d7b6 VSUBSD	(%RSI),%XMM2,%XMM2

    (93) 0x40d7ba VSUBSD	0x10(%RSI),%XMM13,%XMM13

    (93) 0x40d7bf MOV	%R13D,%EDI

    (93) 0x40d7c2 NOT	%EDI

    (93) 0x40d7c4 VFMADD231SD	%XMM2,%XMM2,%XMM0

    (93) 0x40d7c9 ADD	%R9D,%EDI

    (93) 0x40d7cc AND	$0x1,%EDI

    (93) 0x40d7cf VFMADD231SD	%XMM13,%XMM13,%XMM0

    (93) 0x40d7d4 VCOMISD	%XMM3,%XMM0

    (93) 0x40d7d8 JBE	40d854

    (93) 0x40d7da VCOMISD	%XMM0,%XMM4

    (93) 0x40d7de JB	40d854

    (93) 0x40d7e0 VDIVSD	%XMM0,%XMM7,%XMM0

    (93) 0x40d7e4 MOV	0x30(%R11),%RAX

    (93) 0x40d7e8 MOV	0x28(%R11),%RCX

    (93) 0x40d7ec ADD	%R8,%RAX

    (93) 0x40d7ef ADD	%RBX,%RCX

    (93) 0x40d7f2 VMULSD	%XMM0,%XMM8,%XMM15

    (93) 0x40d7f6 VMULSD	%XMM0,%XMM0,%XMM14

    (93) 0x40d7fa VMULSD	%XMM0,%XMM10,%XMM0

    (93) 0x40d7fe VMULSD	%XMM0,%XMM14,%XMM14

    (93) 0x40d802 VSUBSD	%XMM7,%XMM14,%XMM0

    (93) 0x40d806 VFMSUB132SD	%XMM14,%XMM9,%XMM0

    (93) 0x40d80b VMOVAPD	%XMM0,%XMM16

    (93) 0x40d811 VFMADD231SD	%XMM6,%XMM0,%XMM5

    (93) 0x40d816 VMOVAPD	%XMM14,%XMM0

    (93) 0x40d81a VFMADD132SD	%XMM12,%XMM11,%XMM0

    (93) 0x40d81f VFMADD213SD	(%RAX),%XMM6,%XMM16

    (93) 0x40d825 VMULSD	%XMM14,%XMM0,%XMM14

    (93) 0x40d82a VMOVSD	%XMM16,(%RAX)

    (93) 0x40d830 VMULSD	%XMM15,%XMM14,%XMM15

    (93) 0x40d835 VFNMADD213SD	(%RCX),%XMM15,%XMM2

    (93) 0x40d83a VFNMADD213SD	0x8(%RCX),%XMM15,%XMM1

    (93) 0x40d840 VFNMADD213SD	0x10(%RCX),%XMM13,%XMM15

    (93) 0x40d846 VMOVSD	%XMM2,(%RCX)

    (93) 0x40d84a VMOVSD	%XMM1,0x8(%RCX)

    (93) 0x40d84f VMOVSD	%XMM15,0x10(%RCX)

    (93) 0x40d854 LEA	0x1(%R13),%ECX

    (93) 0x40d858 LEA	0x18(%RSI),%RAX

    (93) 0x40d85c CMP	%ECX,%R9D

    (93) 0x40d85f JLE	40da9a

    (93) 0x40d865 TEST	%EDI,%EDI

    (93) 0x40d867 JE	40d930

    (93) 0x40d86d VMOVSD	0x8(%RDX),%XMM1

    (93) 0x40d872 VMOVSD	(%RDX),%XMM2

    (93) 0x40d876 VSUBSD	0x8(%RAX),%XMM1,%XMM1

    (93) 0x40d87b VSUBSD	0x18(%RSI),%XMM2,%XMM2

    (93) 0x40d880 VMOVSD	0x10(%RDX),%XMM13

    (93) 0x40d885 VMULSD	%XMM1,%XMM1,%XMM0

    (93) 0x40d889 VSUBSD	0x10(%RAX),%XMM13,%XMM13

    (93) 0x40d88e VFMADD231SD	%XMM2,%XMM2,%XMM0

    (93) 0x40d893 VFMADD231SD	%XMM13,%XMM13,%XMM0

    (93) 0x40d898 VCOMISD	%XMM3,%XMM0

    (93) 0x40d89c JBE	40d918

    (93) 0x40d89e VCOMISD	%XMM0,%XMM4

    (93) 0x40d8a2 JB	40d918

    (93) 0x40d8a4 VDIVSD	%XMM0,%XMM7,%XMM0

    (93) 0x40d8a8 MOV	0x30(%R11),%RSI

    (93) 0x40d8ac MOV	0x28(%R11),%RDI

    (93) 0x40d8b0 ADD	%R8,%RSI

    (93) 0x40d8b3 ADD	%RBX,%RDI

    (93) 0x40d8b6 VMULSD	%XMM0,%XMM8,%XMM15

    (93) 0x40d8ba VMULSD	%XMM0,%XMM0,%XMM14

    (93) 0x40d8be VMULSD	%XMM0,%XMM10,%XMM0

    (93) 0x40d8c2 VMULSD	%XMM0,%XMM14,%XMM14

    (93) 0x40d8c6 VSUBSD	%XMM7,%XMM14,%XMM0

    (93) 0x40d8ca VFMSUB132SD	%XMM14,%XMM9,%XMM0

    (93) 0x40d8cf VMOVAPD	%XMM0,%XMM17

    (93) 0x40d8d5 VFMADD231SD	%XMM6,%XMM0,%XMM5

    (93) 0x40d8da VMOVAPD	%XMM14,%XMM0

    (93) 0x40d8de VFMADD132SD	%XMM12,%XMM11,%XMM0

    (93) 0x40d8e3 VFMADD213SD	(%RSI),%XMM6,%XMM17

    (93) 0x40d8e9 VMULSD	%XMM14,%XMM0,%XMM14

    (93) 0x40d8ee VMOVSD	%XMM17,(%RSI)

    (93) 0x40d8f4 VMULSD	%XMM15,%XMM14,%XMM15

    (93) 0x40d8f9 VFNMADD213SD	(%RDI),%XMM15,%XMM2

    (93) 0x40d8fe VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

    (93) 0x40d904 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

    (93) 0x40d90a VMOVSD	%XMM2,(%RDI)

    (93) 0x40d90e VMOVSD	%XMM1,0x8(%RDI)

    (93) 0x40d913 VMOVSD	%XMM15,0x10(%RDI)

    (93) 0x40d918 INC	%ECX

    (93) 0x40d91a ADD	$0x18,%RAX

    (93) 0x40d91e CMP	%ECX,%R9D

    (93) 0x40d921 JLE	40da9a

    (93) 0x40d927 NOPW	(%RAX,%RAX,1)

      (94) 0x40d930 VMOVSD	0x8(%RDX),%XMM1

      (94) 0x40d935 VMOVSD	(%RDX),%XMM2

      (94) 0x40d939 VSUBSD	0x8(%RAX),%XMM1,%XMM1

      (94) 0x40d93e VSUBSD	(%RAX),%XMM2,%XMM2

      (94) 0x40d942 VMOVSD	0x10(%RDX),%XMM13

      (94) 0x40d947 VMULSD	%XMM1,%XMM1,%XMM0

      (94) 0x40d94b VSUBSD	0x10(%RAX),%XMM13,%XMM13

      (94) 0x40d950 VFMADD231SD	%XMM2,%XMM2,%XMM0

      (94) 0x40d955 VFMADD231SD	%XMM13,%XMM13,%XMM0

      (94) 0x40d95a VCOMISD	%XMM3,%XMM0

      (94) 0x40d95e JBE	40d9da

      (94) 0x40d960 VCOMISD	%XMM0,%XMM4

      (94) 0x40d964 JB	40d9da

      (94) 0x40d966 VDIVSD	%XMM0,%XMM7,%XMM0

      (94) 0x40d96a MOV	0x30(%R11),%RSI

      (94) 0x40d96e MOV	0x28(%R11),%RDI

      (94) 0x40d972 ADD	%R8,%RSI

      (94) 0x40d975 ADD	%RBX,%RDI

      (94) 0x40d978 VMULSD	%XMM0,%XMM8,%XMM15

      (94) 0x40d97c VMULSD	%XMM0,%XMM0,%XMM14

      (94) 0x40d980 VMULSD	%XMM0,%XMM10,%XMM0

      (94) 0x40d984 VMULSD	%XMM0,%XMM14,%XMM14

      (94) 0x40d988 VSUBSD	%XMM7,%XMM14,%XMM0

      (94) 0x40d98c VFMSUB132SD	%XMM14,%XMM9,%XMM0

      (94) 0x40d991 VMOVAPD	%XMM0,%XMM18

      (94) 0x40d997 VFMADD231SD	%XMM6,%XMM0,%XMM5

      (94) 0x40d99c VMOVAPD	%XMM14,%XMM0

      (94) 0x40d9a0 VFMADD132SD	%XMM12,%XMM11,%XMM0

      (94) 0x40d9a5 VFMADD213SD	(%RSI),%XMM6,%XMM18

      (94) 0x40d9ab VMULSD	%XMM14,%XMM0,%XMM14

      (94) 0x40d9b0 VMOVSD	%XMM18,(%RSI)

      (94) 0x40d9b6 VMULSD	%XMM15,%XMM14,%XMM15

      (94) 0x40d9bb VFNMADD213SD	(%RDI),%XMM15,%XMM2

      (94) 0x40d9c0 VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

      (94) 0x40d9c6 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

      (94) 0x40d9cc VMOVSD	%XMM2,(%RDI)

      (94) 0x40d9d0 VMOVSD	%XMM1,0x8(%RDI)

      (94) 0x40d9d5 VMOVSD	%XMM15,0x10(%RDI)

      (94) 0x40d9da VMOVSD	0x8(%RDX),%XMM1

      (94) 0x40d9df VMOVSD	(%RDX),%XMM2

      (94) 0x40d9e3 VSUBSD	0x20(%RAX),%XMM1,%XMM1

      (94) 0x40d9e8 VSUBSD	0x18(%RAX),%XMM2,%XMM2

      (94) 0x40d9ed VMOVSD	0x10(%RDX),%XMM13

      (94) 0x40d9f2 VMULSD	%XMM1,%XMM1,%XMM0

      (94) 0x40d9f6 VSUBSD	0x28(%RAX),%XMM13,%XMM13

      (94) 0x40d9fb INC	%ECX

      (94) 0x40d9fd LEA	0x18(%RAX),%RSI

      (94) 0x40da01 VFMADD231SD	%XMM2,%XMM2,%XMM0

      (94) 0x40da06 VFMADD231SD	%XMM13,%XMM13,%XMM0

      (94) 0x40da0b VCOMISD	%XMM3,%XMM0

      (94) 0x40da0f JBE	40da8b

      (94) 0x40da11 VCOMISD	%XMM0,%XMM4

      (94) 0x40da15 JB	40da8b

      (94) 0x40da17 VDIVSD	%XMM0,%XMM7,%XMM0

      (94) 0x40da1b MOV	0x30(%R11),%RAX

      (94) 0x40da1f MOV	0x28(%R11),%RDI

      (94) 0x40da23 ADD	%R8,%RAX

      (94) 0x40da26 ADD	%RBX,%RDI

      (94) 0x40da29 VMULSD	%XMM0,%XMM8,%XMM15

      (94) 0x40da2d VMULSD	%XMM0,%XMM0,%XMM14

      (94) 0x40da31 VMULSD	%XMM0,%XMM10,%XMM0

      (94) 0x40da35 VMULSD	%XMM0,%XMM14,%XMM14

      (94) 0x40da39 VSUBSD	%XMM7,%XMM14,%XMM0

      (94) 0x40da3d VFMSUB132SD	%XMM14,%XMM9,%XMM0

      (94) 0x40da42 VMOVAPD	%XMM0,%XMM19

      (94) 0x40da48 VFMADD231SD	%XMM6,%XMM0,%XMM5

      (94) 0x40da4d VMOVAPD	%XMM14,%XMM0

      (94) 0x40da51 VFMADD132SD	%XMM12,%XMM11,%XMM0

      (94) 0x40da56 VFMADD213SD	(%RAX),%XMM6,%XMM19

      (94) 0x40da5c VMULSD	%XMM14,%XMM0,%XMM14

      (94) 0x40da61 VMOVSD	%XMM19,(%RAX)

      (94) 0x40da67 VMULSD	%XMM15,%XMM14,%XMM15

      (94) 0x40da6c VFNMADD213SD	(%RDI),%XMM15,%XMM2

      (94) 0x40da71 VFNMADD213SD	0x8(%RDI),%XMM15,%XMM1

      (94) 0x40da77 VFNMADD213SD	0x10(%RDI),%XMM13,%XMM15

      (94) 0x40da7d VMOVSD	%XMM2,(%RDI)

      (94) 0x40da81 VMOVSD	%XMM1,0x8(%RDI)

      (94) 0x40da86 VMOVSD	%XMM15,0x10(%RDI)

      (94) 0x40da8b INC	%ECX

      (94) 0x40da8d LEA	0x18(%RSI),%RAX

      (94) 0x40da91 CMP	%ECX,%R9D

      (94) 0x40da94 JG	40d930

    (93) 0x40da9a INC	%R12D

    (93) 0x40da9d ADD	$0x8,%R8

    (93) 0x40daa1 CMP	%R12D,%R14D

    (93) 0x40daa4 JG	40d790

  (91) 0x40daaa MOV	-0x40(%RBP),%RAX

  (91) 0x40daae MOV	-0x34(%RBP),%EDX

  (91) 0x40dab1 ADD	$0x4,%RAX

  (91) 0x40dab5 CMP	%RAX,-0x60(%RBP)

  (91) 0x40dab9 JNE	40d651

(92) 0x40dabf JMP	40d74d

0x40dac4 INC	%RDI

0x40dac7 ADD	$0x40,%R9D

0x40dacb CMP	%EDI,%ESI

0x40dacd JLE	40db80

0x40dad3 TEST	%R11D,%R11D

0x40dad6 JE	40db68

0x40dadc CMP	$0x1,%R11D

0x40dae0 JE	40db54

0x40dae2 CMP	$0x2,%R11D

0x40dae6 JE	40db44

0x40dae8 CMP	$0x3,%R11D

0x40daec JE	40db34

0x40daee CMP	$0x4,%R11D

0x40daf2 JE	40db24

0x40daf4 CMP	$0x5,%R11D

0x40daf8 JE	40db14

0x40dafa CMP	$0x6,%R11D

0x40dafe JNE	40dbdf

0x40db04 TEST	%R10D,%R10D

0x40db07 JG	40d5dc

0x40db0d INC	%RDI

0x40db10 ADD	$0x40,%R9D

0x40db14 TEST	%R10D,%R10D

0x40db17 JG	40d5dc

0x40db1d INC	%RDI

0x40db20 ADD	$0x40,%R9D

0x40db24 TEST	%R10D,%R10D

0x40db27 JG	40d5dc

0x40db2d INC	%RDI

0x40db30 ADD	$0x40,%R9D

0x40db34 TEST	%R10D,%R10D

0x40db37 JG	40d5dc

0x40db3d INC	%RDI

0x40db40 ADD	$0x40,%R9D

0x40db44 TEST	%R10D,%R10D

0x40db47 JG	40d5dc

0x40db4d INC	%RDI

0x40db50 ADD	$0x40,%R9D

0x40db54 TEST	%R10D,%R10D

0x40db57 JG	40d5dc

0x40db5d INC	%RDI

0x40db60 ADD	$0x40,%R9D

0x40db64 CMP	%EDI,%ESI

0x40db66 JLE	40db80

(96) 0x40db68 TEST	%R10D,%R10D

(96) 0x40db6b JG	40d5dc

(96) 0x40db71 ADD	$0x8,%RDI

(96) 0x40db75 ADD	$0x200,%R9D

(96) 0x40db7c CMP	%EDI,%ESI

(96) 0x40db7e JG	40db68

0x40db80 VXORPD	%XMM5,%XMM5,%XMM5

0x40db84 MOV	0x28(%RBX),%R11

0x40db88 LEA	0x28(%RBX),%R12

(90) 0x40db8c VMOVQ	%R11,%XMM2

(90) 0x40db91 VADDSD	%XMM2,%XMM5,%XMM1

(90) 0x40db95 MOV	%R11,%RAX

(90) 0x40db98 VMOVQ	%XMM1,%R9

(90) 0x40db9d LOCK CMPXCHG	%R9,(%R12)

(90) 0x40dba3 MOV	%R11,%R10

(90) 0x40dba6 MOV	%RAX,%R11

(90) 0x40dba9 CMP	%RAX,%R10

(90) 0x40dbac JNE	40db8c

0x40dbae ADD	$0x58,%RSP

0x40dbb2 POP	%RBX

0x40dbb3 POP	%R12

0x40dbb5 POP	%R13

0x40dbb7 POP	%R14

0x40dbb9 POP	%R15

0x40dbbb POP	%RBP

0x40dbbc RET

0x40dbbd INC	%EAX

0x40dbbf XOR	%EDX,%EDX

0x40dbc1 JMP	40d57e

0x40dbc6 MOV	$0x4131a8,%ECX

0x40dbcb MOV	$0xb6,%EDX

0x40dbd0 MOV	$0x4130c0,%ESI

0x40dbd5 MOV	$0x41319f,%EDI

0x40dbda CALL	4030c0 <__assert_fail@plt>

0x40dbdf TEST	%R8D,%R8D

0x40dbe2 JG	40d5dc

0x40dbe8 INC	%RDI

0x40dbeb ADD	$0x40,%R9D

0x40dbef JMP	40db04

0x40dbf4 NOPW	%CS:(%RAX,%RAX,1)

0x40dbff NOP

Coverage (%)	Name	Source Location	Module
○98.16	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.84	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.50 to 9.50 cycles (2.26x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 21.50 to 1.50 cycles (14.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 124 bytes (15 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	123
nb uops	129
loop length	467
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.50 cycles
front end	21.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.10	13.00	8.00	8.00	5.00	13.07	12.90	5.00	5.00	5.00	12.93	8.00
cycles	13.10	13.00	8.00	8.00	5.00	13.07	12.90	5.00	5.00	5.00	12.93	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	21.50
Dispatch	13.10
DIV/SQRT	6.00
Overall L1	21.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	7%
load	9%
store	12%
mul	6%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	11%
store	12%
mul	9%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.50 cycles. At this rate:

3% of peak load performance is reached (5.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.50 to 13.10 cycles (1.64x speedup).

ASM code

In the binary file, the address of the function is: 40d540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xc(%R13),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 40dbbd <ljForce._omp_fn.1+0x67d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40db80 <ljForce._omp_fn.1+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EDX,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVSXD 0x30(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x5c18(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOT %R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SAL $0x6,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %ESI,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VMULSD 0x8(%RBX),%XMM8,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x20(%RBX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R8,4),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40dac4 <ljForce._omp_fn.1+0x584>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RDI,4),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x80(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x5bd1(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x5bd1(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x5bd1(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x5bd1(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40db80 <ljForce._omp_fn.1+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R11D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40db68 <ljForce._omp_fn.1+0x628>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db54 <ljForce._omp_fn.1+0x614>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db44 <ljForce._omp_fn.1+0x604>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db34 <ljForce._omp_fn.1+0x5f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db24 <ljForce._omp_fn.1+0x5e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db14 <ljForce._omp_fn.1+0x5d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40dbdf <ljForce._omp_fn.1+0x69f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40db80 <ljForce._omp_fn.1+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x28(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x28(%RBX),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40d57e <ljForce._omp_fn.1+0x3e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x4131a8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xb6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4130c0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41319f,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40db04 <ljForce._omp_fn.1+0x5c4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.50 to 9.50 cycles (2.26x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-1858/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 124 bytes (15 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	123
nb uops	129
loop length	467
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.50 cycles
front end	21.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.10	13.00	8.00	8.00	5.00	13.07	12.90	5.00	5.00	5.00	12.93	8.00
cycles	13.10	13.00	8.00	8.00	5.00	13.07	12.90	5.00	5.00	5.00	12.93	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	21.50
Dispatch	13.10
DIV/SQRT	6.00
Overall L1	21.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	7%
load	9%
store	12%
mul	6%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	9%
load	11%
store	12%
mul	9%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.50 cycles. At this rate:

3% of peak load performance is reached (5.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40d540

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0xc(%R13),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 40dbbd <ljForce._omp_fn.1+0x67d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 40db80 <ljForce._omp_fn.1+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVSXD %EDX,%RDI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOVSXD 0x30(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x5c18(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOT %R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SAL $0x6,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %ESI,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
VMULSD 0x8(%RBX),%XMM8,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD 0x20(%RBX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (,%R8,4),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 40dac4 <ljForce._omp_fn.1+0x584>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R15,%RDI,4),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x80(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x5bd1(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x5bd1(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x5bd1(%RIP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x5bd1(%RIP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40db80 <ljForce._omp_fn.1+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R11D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 40db68 <ljForce._omp_fn.1+0x628>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db54 <ljForce._omp_fn.1+0x614>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db44 <ljForce._omp_fn.1+0x604>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db34 <ljForce._omp_fn.1+0x5f4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db24 <ljForce._omp_fn.1+0x5e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 40db14 <ljForce._omp_fn.1+0x5d4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 40dbdf <ljForce._omp_fn.1+0x69f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EDI,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 40db80 <ljForce._omp_fn.1+0x640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x28(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x28(%RBX),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 40d57e <ljForce._omp_fn.1+0x3e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x4131a8,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xb6,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x4130c0,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x41319f,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JG 40d5dc <ljForce._omp_fn.1+0x9c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 40db04 <ljForce._omp_fn.1+0x5c4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.1–	70.33	3.33
▼Loop 92 - ljForce.c:175-216 - exec–	0.02	0.01
▼Loop 91 - ljForce.c:178-216 - exec–	0.36	0.01
▼Loop 93 - ljForce.c:187-216 - exec–	11.61	0.45
○Loop 94 - ljForce.c:191-216 - exec	58.34	2.27
○Loop 95 - ljForce.c:187-191 - exec	0.00	0.00
○Loop 90 - ljForce.c:172-172 - exec	0.00	0.00
○Loop 96 - ljForce.c:178-178 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code